Two-wire Serial EEPROMs AT24C128 AT24C256

Transcription

1 Faturs Low-voltag and Standard-voltag Opration 2.7 (V CC = 2.7V to 5.5V).8 (V CC =.8V to 3.6V) Intrnally Organizd 6,384 x 8 and 32,768 x 8 Two-wir Srial Intrfac Schmitt Triggr, Filtrd Inputs for Nois Supprssion Bidirctional Data Transfr Protocol MHz (5V), 400 khz (2.7V, 2.5V) and 00 khz (.8V) Compatibility Writ Protct Pin for Hardwar and Softwar Data Protction 64-byt Pag Writ Mod (Partial Pag Writs Allowd) Slf-timd Writ Cycl (5 ms Max) High Rliability Enduranc: On Million Writ Cycls Data Rtntion: 40 Yars Extndd Tmpratur and Lad-fr/Halogn-fr Dvics Availabl 8-lad JEDEC PDIP, 8-lad JEDEC and EIAJ SOIC, 8-lad MAP, 8-lad TSSOP, 8-lad SAP and 8-ball dbga2 Packags Di Sals: Wafr Form, Waffl Pack, and Bumpd Wafrs Dscription Th AT24C28/256 provids 3,072/262,44 bits of srial lctrically rasabl and programmabl rad only mmory (EEPROM) organizd as 6,384/32,768 words of 8 bits ach. Th dvic s cascadabl fatur allows up to 4 dvics to shar a common Two-wir bus. Th dvic is optimizd for us in many industrial and commrcial applications whr low powr and low voltag opration ar ssntial. Th dvics ar availabl in spac-saving 8-lad JEDEC PDIP, 8-lad JEDEC SOIC, 8-lad EIAJ SOIC, 8-lad MAP (24C28), 8-lad TSSOP, 8-lad SOIC Array Packag and 8-ball dbga2 packags. In addition, th ntir family is availabl in 2.7V (2.7V to 5.5V) and.8v (.8V to 3.6V) vrsions. 8-lad PDIP 8-lad TSSOP Tabl. Pin Configuration Pin Nam A0 - A SDA SCL WP NC GND Function Addrss Inputs Srial Data Srial Clock Input Writ Protct No Connct Ground A0 A NC GND A0 A NC GND lad SOIC VCC WP SCL SDA VCC WP SCL SDA A0 A NC GND VCC WP SCL SDA lad MAP VCC WP SCL SDA A0 A NC GND Two-wir Srial EEPROMs 28K (6,384 x 8) 256K (32,768 x 8) AT24C28 AT24C256 8-ball dbga2 VCC WP SCL SDA Bottom Viw A0 A NC GND VCC WP SCL SDA Bottom Viw 8-lad SAP Bottom Viw A0 A NC GND

2 Absolut Maximum Ratings* Oprating Tmpratur C to +25 C Storag Tmpratur C to +50 C Voltag on Any Pin with Rspct to Ground....0V to +7.0V Maximum Oprating Voltag V *NOTICE: Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. This is a strss rating only and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of this spcification is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct dvic rliability. DC Output Currnt ma Figur. Block Diagram 2 AT24C28/256

3 AT24C28/256 Pin Dscription Mmory Organization SERIAL CLOCK (SCL): Th SCL input is usd to positiv dg clock data into ach EEPROM dvic and ngativ dg clock data out of ach dvic. SERIAL DATA (SDA): Th SDA pin is bidirctional for srial data transfr. This pin is opndrain drivn and may b wir-ord with any numbr of othr opn-drain or opn collctor dvics. DEVICE/ADDRESSES (A, A0): Th A and A0 pins ar dvic addrss inputs that ar hardwird or lft not connctd for hardwar compatibility with othr AT24CXX dvics. Whn th pins ar hardwird, as many as four 28K/256K dvics may b addrssd on a singl bus systm (dvic addrssing is discussd in dtail undr th Dvic Addrssing sction). If th pins ar lft floating, th A and A0 pins will b intrnally pulld down to GND if th capacitiv coupling to th circuit board V CC plan is <3 pf. If coupling is >3 pf, Atml rcommnds conncting th addrss pins to GND. WRITE PROTECT (WP): Th writ protct input, whn connctd to GND, allows normal writ oprations. Whn WP is connctd high to V CC, all writ oprations to th mmory ar inhibitd. If th pin is lft floating, th WP pin will b intrnally pulld down to GND if th capacitiv coupling to th circuit board V CC plan is <3 pf. If coupling is >3 pf, Atml rcommnds conncting th pin to GND. AT24C28/256, 28K/256K SERIAL EEPROM: Th 28K/256K is intrnally organizd as 256/52 pags of 64-byts ach. Random word addrssing rquirs a 4/5-bit data word addrss. 3

4 Tabl 2. Pin Capacitanc () Applicabl ovr rcommndd oprating rang from T A = 25 C, f =.0 MHz, V CC = +.8V. Symbol Tst Condition Max Units Conditions C I/O Input/Output Capacitanc (SDA) 8 pf V I/O = 0V C IN Input Capacitanc (A 0, A, SCL) 6 pf V IN = 0V Not:. This paramtr is charactrizd and is not 00% tstd. Tabl 3. DC Charactristics () Applicabl ovr rcommndd oprating rang from: T AI = 40 C to +85 C, V CC = +.8V to +5.5V; T AE = 40 C to +25 C (2), V CC = +2.7V to +5.5V(unlss othrwis notd). Symbol Paramtr Tst Condition Min Typ Max Units V CC Supply Voltag V V CC2 Supply Voltag V V CC3 Supply Voltag V I CC Supply Currnt V CC = 5.0V READ at 400 khz ma I CC2 Supply Currnt V CC = 5.0V WRITE at 400 khz ma I SB I SB2 Standby Currnt (.8V option) Standby Currnt (2.5V option) V CC =.8V 0.2 µa V IN = V CC or V SS V CC = 3.6V 2.0 V CC = 2.5V 0.5 µa V IN = V CC or V SS V CC = 5.5V 6.0 I SB3 Standby Currnt (5.0V option) V CC = V V IN = V CC or V SS 6.0 µa I LI Input Lakag Currnt V IN = V CC or V SS µa I LO Output Lakag Currnt V OUT = V CC or V SS µa V IL Input Low Lvl () 0.6 V CC x 0.3 V V IH Input High Lvl () V CC x 0.7 V CC V V OL2 Output Low Lvl V CC = 3.0V I OL = 2. ma 0.4 V V OL Output Low Lvl V CC =.8V I OL = 0.5 ma 0.2 V Nots:. V IL min and V IH max ar rfrnc only and ar not tstd. 2. Th AT24C28/256 baring th procss lttr B on th packag (th mark is locatd in th lowr right cornr on th topsid of th packag) ar approvd for opration in th xtndd tmpratur rang. 4 AT24C28/256

5 AT24C28/256 Tabl 4. AC Charactristics Industrial Tmpraturs Applicabl ovr rcommndd oprating rang from T AI = 40 C to +85 C, V CC = +.8V to +5.5V, CL = 00 pf (unlss othrwis notd). Tst conditions ar listd in Not 2..8-volt 2.5-volt 5.0-volt Symbol Paramtr Min Max Min Max Min Max Units f SCL Clock Frquncy, SCL khz t LOW Clock Puls Width Low µs t HIGH Clock Puls Width High µs t AA Clock Low to Data Out Valid µs t BUF Tim th bus must b fr bfor a nw transmission can start () µs t HD.STA Start Hold Tim µs t SU.STA Start St-up Tim µs t HD.DAT Data In Hold Tim µs t SU.DAT Data In St-up Tim ns t R Inputs Ris Tim () µs t F Inputs Fall Tim () ns t SU.STO Stop St-up Tim µs t DH Data Out Hold Tim ns t WR Writ Cycl Tim 20 or 5 (3) 0 or 5 (3) 0 or 5 (3) ms Enduranc () 25 C, Pag Mod 00k or,000,000 (4) Writ Cycls Nots:. This paramtr is charactrizd and is not 00% tstd. 2. AC masurmnt conditions: R L (conncts to V CC ):.3 kω (2.5V, 5V), 0 kω (.8V) Input puls voltags: 0.3 V CC to 0.7 V CC Input ris and fall tims: 50 ns Input and output timing rfrnc voltags: 0.5 V CC 3. Th Writ Cycl Tim of 5 ms only applis to th AT24C28/256 dvics baring th procss lttr B on th packag (th mark is locatd in th lowr right cornr on th top sid of th packag). 4. Th AT24C28/256 baring th procss lttr B in th packag (th mark is locatd in th lowr right cornr on th top sid of th packag), guarants million writ cycl nduranc (.8 3.6V). 5

6 Tabl 5. AC Charactristics (5) Extndd Tmpraturs Applicabl ovr rcommndd oprating rang from T AE = 40 C to +25 C, V CC = +2.7V to +5.5V, CL = 00 pf (unlss othrwis notd). Tst conditions ar listd in Not volt 5.0-volt Symbol Paramtr Min Max Min Max Units f SCL Clock Frquncy, SCL khz t LOW Clock Puls Width Low µs t HIGH Clock Puls Width High µs t AA Clock Low to Data Out Valid µs t BUF Tim th bus must b fr bfor a nw transmission can start () µs t HD.STA Start Hold Tim µs t SU.STA Start St-up Tim µs t HD.DAT Data In Hold Tim 0 0 µs t SU.DAT Data In St-up Tim ns t R Inputs Ris Tim () µs t F Inputs Fall Tim () ns t SU.STO Stop St-up Tim µs t DH Data Out Hold Tim ns t WR Writ Cycl Tim 0 or 5 (3) 0 or 5 (3) ms Enduranc () 25 C, Pag Mod 00k or,000,000 (4) Writ Cycls Nots:. This paramtr is charactrizd and is not 00% tstd. 2. AC masurmnt conditions: R L (conncts to V CC ):.3 kω (2.5V, 5V), 0 kω (.8V) Input puls voltags: 0.3 V CC to 0.7 V CC Input ris and fall tims: 50 ns Input and output timing rfrnc voltags: 0.5 V CC 3. Th Writ Cycl Tim of 5 ms only applis to th AT24C28/256 dvics baring th procss lttr B on th packag (th mark is locatd in th lowr right cornr on th top sid of th packag). 4. Th AT24C28/256 baring th procss lttr B in th packag (th mark is locatd in th lowr right cornr on th top sid of th packag), guarants million writ cycl nduranc (.8 3.6V). 5. Th AT24C28/256 baring th procss lttr B on th packag (th mark is locatd in th lowr right cornr on th topsid of th packag) ar approvd for opration in th xtndd tmpratur rang. 6 AT24C28/256

7 AT24C28/256 Dvic Opration CLOCK and DATA TRANSITIONS: Th SDA pin is normally pulld high with an xtrnal dvic. Data on th SDA pin may chang only during SCL low tim priods (s Figur 4 on pag 8). Data changs during SCL high priods will indicat a start or stop condition as dfind blow. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must prcd any othr command (s Figur 5 on pag 9). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. Aftr a rad squnc, th stop command will plac th EEPROM in a standby powr mod (s Figur 5 on pag 9). ACKNOWLEDGE: All addrsss and data words ar srially transmittd to and from th EEPROM in 8-bit words. Th EEPROM snds a zro during th ninth clock cycl to acknowldg that it has rcivd ach word. STANDBY MODE: Th AT24C28/256 faturs a low powr standby mod which is nabld: a) upon powr-up and b) aftr th rcipt of th STOP bit and th compltion of any intrnal oprations. MEMORY RESET: Aftr an intrruption in protocol, powr loss or systm rst, any two-wir part can b rst by following ths stps: (a) Clock up to 9 cycls, (b) look for SDA high in ach cycl whil SCL is high and thn (c) crat a start condition as SDA is high. 7

8 Figur 2. Bus Timing (SCL: Srial Clock, SDA: Srial Data I/O) Figur 3. Writ Cycl Timing (SCL: Srial Clock, SDA: Srial Data I/O) SCL SDA 8th BIT ACK WORDn STOP CONDITION t wr () START CONDITION Not:. Th writ cycl tim t WR is th tim from a valid stop condition of a writ squnc to th nd of th intrnal clar/writ cycl. Figur 4. Data Validity 8 AT24C28/256

9 AT24C28/256 Figur 5. Start and Stop Dfinition Figur 6. Output Acknowldg Dvic Addrssing Th 28K/256K EEPROM rquirs an 8-bit dvic addrss word following a start condition to nabl th chip for a rad or writ opration (s Figur 7 on pag ). Th dvic addrss word consists of a mandatory on, zro squnc for th first fiv most significant bits as shown. This is common to all two-wir EEPROM dvics. Th 28K/256K uss th two dvic addrss bits A, A0 to allow as many as four dvics on th sam bus. Ths bits must compar to thir corrsponding hardwird input pins. Th A and A0 pins us an intrnal propritary circuit that biass thm to a logic low condition if th pins ar allowd to float. Th ighth bit of th dvic addrss is th rad/writ opration slct bit. A rad opration is initiatd if this bit is high and a writ opration is initiatd if this bit is low. Upon a compar of th dvic addrss, th EEPROM will output a zro. If a compar is not mad, th dvic will rturn to a standby stat. DATA SECURITY: Th AT24C28/256 has a hardwar data protction schm that allows th usr to writ protct th whol mmory whn th WP pin is at V CC. 9

10 Writ Oprations BYTE WRITE: A writ opration rquirs two 8-bit data word addrsss following th dvic addrss word and acknowldgmnt. Upon rcipt of this addrss, th EEPROM will again rspond with a zro and thn clock in th first 8-bit data word. Following rcipt of th 8-bit data word, th EEPROM will output a zro. Th addrssing dvic, such as a microcontrollr, thn must trminat th writ squnc with a stop condition. At this tim th EEPROM ntrs an intrnally-timd writ cycl, t WR, to th nonvolatil mmory. All inputs ar disabld during this writ cycl and th EEPROM will not rspond until th writ is complt (s Figur 8 on pag ). PAGE WRITE: Th 28K/256K EEPROM is capabl of 64-byt pag writs. A pag writ is initiatd th sam way as a byt writ, but th microcontrollr dos not snd a stop condition aftr th first data word is clockd in. Instad, aftr th EEPROM acknowldgs rcipt of th first data word, th microcontrollr can transmit up to 63 mor data words. Th EEPROM will rspond with a zro aftr ach data word rcivd. Th microcontrollr must trminat th pag writ squnc with a stop condition (s Figur 9 on pag 2). Th data word addrss lowr 6 bits ar intrnally incrmntd following th rcipt of ach data word. Th highr data word addrss bits ar not incrmntd, rtaining th mmory pag row location. Whn th word addrss, intrnally gnratd, rachs th pag boundary, th following byt is placd at th bginning of th sam pag. If mor than 64 data words ar transmittd to th EEPROM, th data word addrss will roll ovr and prvious data will b ovrwrittn. Th addrss roll ovr during writ is from th last byt of th currnt pag to th first byt of th sam pag. ACKNOWLEDGE POLLING: Onc th intrnally-timd writ cycl has startd and th EEPROM inputs ar disabld, acknowldg polling can b initiatd. This involvs snding a start condition followd by th dvic addrss word. Th rad/writ bit is rprsntativ of th opration dsird. Only if th intrnal writ cycl has compltd will th EEPROM rspond with a zro, allowing th rad or writ squnc to continu. 0 AT24C28/256

11 AT24C28/256 Rad Oprations Rad oprations ar initiatd th sam way as writ oprations with th xcption that th rad/writ slct bit in th dvic addrss word is st to on. Thr ar thr rad oprations: currnt addrss rad, random addrss rad and squntial rad. CURRENT ADDRESS READ: Th intrnal data word addrss countr maintains th last addrss accssd during th last rad or writ opration, incrmntd by on. This addrss stays valid btwn oprations as long as th chip powr is maintaind. Th addrss roll ovr during rad is from th last byt of th last mmory pag, to th first byt of th first pag. Onc th dvic addrss with th rad/writ slct bit st to on is clockd in and acknowldgd by th EEPROM, th currnt addrss data word is srially clockd out. Th microcontrollr dos not rspond with an input zro but dos gnrat a following stop condition (s Figur 0 on pag 2). RANDOM READ: A random rad rquirs a dummy byt writ squnc to load in th data word addrss. Onc th dvic addrss word and data word addrss ar clockd in and acknowldgd by th EEPROM, th microcontrollr must gnrat anothr start condition. Th microcontrollr now initiats a currnt addrss rad by snding a dvic addrss with th rad/writ slct bit high. Th EEPROM acknowldgs th dvic addrss and srially clocks out th data word. Th microcontrollr dos not rspond with a zro but dos gnrat a following stop condition (s Figur on pag 2). SEQUENTIAL READ: Squntial rads ar initiatd by ithr a currnt addrss rad or a random addrss rad. Aftr th microcontrollr rcivs a data word, it rsponds with an acknowldg. As long as th EEPROM rcivs an acknowldg, it will continu to incrmnt th data word addrss and srially clock out squntial data words. Whn th mmory addrss limit is rachd, th data word addrss will roll ovr and th squntial rad will continu. Th squntial rad opration is trminatd whn th microcontrollr dos not rspond with a zro but dos gnrat a following stop condition (s Figur 2 on pag 2). Figur 7. Dvic Addrss Figur 8. Byt Writ

12 Figur 9. Pag Writ Nots: (* = DON T CARE bit) ( = DON T CARE bit for th 28K) Figur 0. Currnt Addrss Rad Figur. Random Rad Nots: (* = DON T CARE bit) ( = DON T CARE bit for th 28K) Figur 2. Squntial Rad 2 AT24C28/256

13 AT24C28 Ordring Information () AT24C28/256 Ordring Cod Packag Opration Rang AT24C28-0PI-2.7 AT24C28N-0SI-2.7 AT24C28W-0SI-2.7 AT24C28-0TI-2.7 AT24C28-0PI-.8 AT24C28N-0SI-.8 AT24C28W-0SI-.8 AT24C28-0TI-.8 AT24C28-0PU-2.7 (2) AT24C28-0PU-.8 (2) AT24C28N-0SU-2.7 (2) AT24C28N-0SU-.8 (2) AT24C28W-0SU-2.7 (2) AT24C28W-0SU-.8 (2) AT24C28-0TU-2.7 (2) AT24C28-0TU-.8 (2) AT24C28U2-0UU-.8 (2) AT24C28Y-0YU-.8 (2) AT24C28Y4-0YU-.8 (2) AT24C28-W2.7- (3) AT24C28-W.8- (3) Nots:. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabls. 2. U dsignats Grn packag + RoHS compliant. 3. Availabl in waffl pack and wafr form; ordr as SL79 for wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM Markting. 8P3 8S 8S2 8A2 8P3 8S 8S2 8A2 8P3 8P3 8S 8S 8S2 8S2 8A2 8A2 8U2-8Y 8Y4 Di Sal Di Sal Industrial Tmpratur ( 40 C to 85 C) Industrial Tmpratur ( 40 C to 85 C) Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) Industrial Tmpratur ( 40 C to 85 C) Packag Typ 8P3 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8S 8-lad, 0.50" Wid, Plastic Gull Wing Small Outlin Packag (JEDEC SOIC) 8S2 8-lad, 0.200" Wid, Plastic Gull Wing Small Outlin Packag (EIAJ SOIC) 8U2-8-ball, di Ball Grid Array Packag (dbga2) 8Y 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 8Y4 8-lad, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-ladd, Small Array Packag (SAP) 8A2 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) Options 2.7 Low-voltag (2.7V to 5.5V).8 Low-voltag (.8V to 3.6V) 3

14 AT24C256 Ordring Information () Ordring Cod Packag Opration Rang AT24C256-0PI-2.7 AT24C256N-0SI-2.7 AT24C256W-0SI-2.7 AT24C256-0TI-2.7 AT24C256-0PI-.8 AT24C256N-0SI-.8 AT24C256W-0SI-.8 AT24C256-0TI-.8 AT24C256-0PU-2.7 (2) AT24C256-0PU-.8 (2) AT24C256N-0SU-2.7 (2) AT24C256N-0SU-.8 (2) AT24C256W-0SU-2.7 (2) AT24C256W-0SU-.8 (2) AT24C256-0TU-2.7 (2) AT24C256-0TU-.8 (2) AT24C256U2-0UU-.8 (2) AT24C256Y-0YU-.8 (2) AT24C256Y4-0YU-.8 (2) AT24C256-W2.7- (3) AT24C256-W.8- (3) Nots:. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabls. 2. U dsignats Grn Packag + RoHS compliant. 3. Availabl in waffl pack and wafr form; ordr as SL79 for wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM Markting. 8P3 8S 8S2 8A2 8P3 8S 8S2 8A2 8P3 8P3 8S 8S 8S2 8S2 8A2 8A2 8U2-8Y 8Y4 Di Sal Di Sal Industrial Tmpratur ( 40 C to 85 C) Industrial Tmpratur ( 40 C to 85 C) Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) Industrial Tmpratur ( 40 C to 85 C) Packag Typ 8P3 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8S 8-lad, 0.50" Wid, Plastic Gull Wing Small Outlin Packag (JEDEC SOIC) 8S2 8-lad, 0.200" Wid, Plastic Gull Wing Small Outlin Packag (EIAJ SOIC) 8U2-8-ball, di Ball Grid Array Packag (dbga2) 8Y 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 8Y4 8-lad, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-ladd, Small Array Packag (SAP) 8A2 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) Options 2.7 Low-voltag (2.7V to 5.5V).8 Low-voltag (.8V to 3.6V) 4 AT24C28/256

15 AT24C28/256 Packaging Information 8P3 PDIP E E N Top Viw c A End Viw D D A2 A COMMON DIMENSIONS (Unit of Masur = inchs) SYMBOL MIN NOM MAX NOTE A A b b b c b3 4 PLCS b2 b L D D E E Sid Viw 0.00 BSC A BSC 4 L Nots: R. This drawing is for gnral information only; rfr to JEDEC Drawing MS-00, Variation BA for additional information. 2. Dimnsions A and L ar masurd with th packag satd in JEDEC sating plan Gaug GS D, D and E dimnsions do not includ mold Flash or protrusions. Mold Flash or protrusions shall not xcd 0.00 inch. 4. E and A masurd with th lads constraind to b prpndicular to datum. 5. Pointd or roundd lad tips ar prfrrd to as insrtion. 6. b2 and b3 maximum dimnsions do not includ Dambar protrusions. Dambar protrusions shall not xcd 0.00 (0.25 mm) Orchard Parkway San Jos, CA 953 TITLE 8P3, 8-lad, 0.300" Wid Body, Plastic Dual In-lin Packag (PDIP) DRAWING NO. 8P3 0/09/02 REV. B 5

16 8S JEDEC SOIC C E E N L Top Viw End Viw B A COMMON DIMENSIONS (Unit of Masur = mm) D Sid Viw A SYMBOL MIN NOM MAX NOTE A A b C D E E BSC L Not: Ths drawings ar for gnral information only. Rfr to JEDEC Drawing MS-02, Variation AA for propr dimnsions, tolrancs, datums, tc. 0/7/03 R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 8S, 8-lad (0.50" Wid Body), Plastic Gull Wing Small Outlin (JEDEC SOIC) DRAWING NO. 8S REV. B 6 AT24C28/256

17 AT24C28/256 8S2 EIAJ SOIC C E E N L Top Viw D Sid Viw b A A End Viw COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A A b C D E , 3 E L BSC 4 Nots:. This drawing is for gnral information only; rfr to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of th uppr and lowr dis and rsin burrs ar not includd. 3. It is rcommndd that uppr and lowr cavitis b qual. If thy ar diffrnt, th largr dimnsion shall b rgardd. 4. Dtrmins th tru gomtric position. 5. Valus b and C apply to pb/sn soldr platd trminal. Th standard thicknss of th soldr layr shall b / mm. R 2325 Orchard Parkway San Jos, CA 953 TITLE 8S2, 8-lad, 0.209" Body, Plastic Small Outlin Packag (EIAJ) DRAWING NO. 8S2 0/7/03 REV. C 7

18 8U2- dbga2 A BALL PAD CORNER D. b E A Top Viw A2 A A BALL PAD CORNER Sid Viw 2 A B C () D d (d) Bottom Viw 8 Soldr Balls. This drawing is for gnral information only. 2. Dimnsion b is masurd at th maximum soldr ball diamtr. COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A A A b D 2.35 BSC E 3.73 BSC 0.75 BSC 0.74 REF d 0.75 BSC d 0.80 REF R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 8U2-, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Small Di Ball Grid Array Packag (dbga2) 6/24/03 DRAWING NO. REV. PO8U2- A 8 AT24C28/256

19 AT24C28/256 8Y MAP PIN INDEX AREA A PIN INDEX AREA E D D L E A b Top Viw End Viw Bottom Viw Sid Viw A COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 0.90 A D E D E b TYP L /28/03 R 2325 Orchard Parkway San Jos, CA 953 TITLE 8Y, 8-lad (4.90 x 3.00 mm Body) MSOP Array Packag (MAP) Y DRAWING NO. 8Y REV. C 9

20 AT24C28/256 8Y4 SAP PIN INDEX AREA A PIN ID D E D L E A A b COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 0.90 A D E D E b TYP 3.8 REF L /24/04 R 50 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 8Y4, 8-lad (6.00 x 4.90 mm Body) SOIC Array Packag (SAP) Y4 DRAWING NO. 8Y4 REV. A 20

21 AT24C28/256 8A2 TSSOP 3 2 Pin indicator this cornr E E L N Top Viw L End Viw b D Sid Viw A2 A COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE D , 5 E 6.40 BSC E , 5 A.20 A b BSC L L.00 REF Nots:. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-53, Variation AA, for propr dimnsions, tolrancs, datums, tc. 2. Dimnsion D dos not includ mold Flash, protrusions or gat burrs. Mold Flash, protrusions and gat burrs shall not xcd 0.5 mm (0.006 in) pr sid. 3. Dimnsion E dos not includ intr-lad Flash or protrusions. Intr-lad Flash and protrusions shall not xcd 0.25 mm (0.00 in) pr sid. 4. Dimnsion b dos not includ Dambar protrusion. Allowabl Dambar protrusion shall b 0.08 mm total in xcss of th b dimnsion at maximum matrial condition. Dambar cannot b locatd on th lowr radius of th foot. Minimum spac btwn protrusion and adjacnt lad is 0.07 mm. 5. Dimnsion D and E to b dtrmind at Datum Plan H. 5/30/02 R 2325 Orchard Parkway San Jos, CA 953 TITLE 8A2, 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) DRAWING NO. 8A2 REV. B 2

22 Atml Corporation 2325 Orchard Parkway San Jos, CA 953, USA Tl: (408) Fax: (408) Rgional Hadquartrs Europ Atml Sarl Rout ds Arsnaux 4 Cas Postal 80 CH-705 Fribourg Switzrland Tl: (4) Fax: (4) Asia Room 29 Chinachm Goldn Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tl: (852) Fax: (852) Japan 9F, Tontsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan Tl: (8) Fax: (8) Atml Oprations Mmory 2325 Orchard Parkway San Jos, CA 953, USA Tl: (408) Fax: (408) Microcontrollrs 2325 Orchard Parkway San Jos, CA 953, USA Tl: (408) Fax: (408) La Chantrri BP Nants Cdx 3, Franc Tl: (33) Fax: (33) ASIC/ASSP/Smart Cards Zon Industrill 306 Rousst Cdx, Franc Tl: (33) Fax: (33) East Chynn Mtn. Blvd. Colorado Springs, CO 80906, USA Tl: (79) Fax: (79) Scottish Entrpris Tchnology Park Maxwll Building East Kilbrid G75 0QR, Scotland Tl: (44) Fax: (44) RF/Automotiv Thrsinstrass 2 Postfach Hilbronn, Grmany Tl: (49) Fax: (49) East Chynn Mtn. Blvd. Colorado Springs, CO 80906, USA Tl: (79) Fax: (79) Biomtrics/Imaging/Hi-Rl MPU/ High Spd Convrtrs/RF Datacom Avnu d Rochplin BP Saint-Egrv Cdx, Franc Tl: (33) Fax: (33) Litratur Rqusts Disclaimr: Th information in this documnt is providd in connction with Atml products. No licns, xprss or implid, by stoppl or othrwis, to any intllctual proprty right is grantd by this documnt or in connction with th sal of Atml products. EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atml maks no rprsntations or warrantis with rspct to th accuracy or compltnss of th contnts of this documnt and rsrvs th right to mak changs to spcifications and product dscriptions at any tim without notic. Atml dos not mak any commitmnt to updat th information containd hrin. Unlss spcifically providd othrwis, Atml products ar not suitabl for, and shall not b usd in, automotiv applications. Atml s products ar not intndd, authorizd, or warrantd for us as componnts in applications intndd to support or sustain lif. Atml Corporation All rights rsrvd. Atml, logo and combinations throf, Evrywhr You Ar and othrs, ar rgistrd tradmarks or tradmarks of Atml Corporation or its subsidiaris. Othr trms and product nams may b tradmarks of othrs. Printd on rcycld papr.