FM75 Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm

Transcription

1 Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Features User Configurable to 9, 10, 11 or 12-bit Resolution Precision Calibrated to ±1 C, 0 C to 100 C Typical Temperature Range: -40 C to 125 C Low Operating Current (less than 250µA) Low Self Heating (0.2 C max. in still air) Operating Voltage Range: 2.7V to 5.5V Applications Battery Management FAX Management Printers Portable Medical Instruments HVAC Systems Power Supply Modules Disk Drives Computers Automotive Components Application Diagram Description December 2006 The contains a high-precision CMOS temperature sensor, a Delta-Sigma analog-to-digital converter, and a SMBus-compatible serial digital interface. Typical accuracy is ±2 C over the full temperature range of 40 C to 125 C and to ±1 C over the range of 0 C to 100 C, with 9- to 12-bit resolution (default is 9). Thermal alarm output, over-limit signal (OS) supports interrupt and comparator modes. OS is active if the userprogrammable trip-temperature is exceeded. When the temperature falls below the trip temperature, plus the user-programmable hysteresis limit, the OS is disabled. Available in a surface mount SOIC-8 (SOP-8) package. 2.7 to 5.5V 8 tm Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm A0 7 User Programmable Address SMBus Interface A1 A Pin Configuration 3 OS 4 Ordering Information Figure 1. Typical Application Diagram Part Number Package Temperature Range Packing Method M8x 8-Lead SOIC -40 C to +125 C 2500 Units, Tape and Reel Rev

2 Pin Assignments Pin Descriptions OS GND Figure 2. Pin Assignments Pin # Name Direction Description 1 Input/Output Serial Data. Open drain to I/O-data pin for two-wire interface. 2 Input Serial Clock. Clock for two-wire serial interface. 3 OS Output Over-Limit Signal. Open drain thermostat output that indicates if the temperature exceeds user-programmable limits. Default is active LOW. 4 GND Supply Ground 5, 6, 7 A0, A1, A2 Input Address Least Significant Bits (LSBs). User selectable address pins for the three LSBs of the serial interface address. 8 V DD Supply Supply Voltage V DD A0 A1 A2 Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Rev

3 Absolute Maximum Ratings The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table defines the conditions for actual device operation. Parameter Min. Typ. Max. Units Supply Voltage +7 V Output Voltage V CC V Output Current 10 ma Storage Temperature Range C Lead Soldering Temperature 220 C ESD (1) Human Body Model Machine Model V V Note: 1. Human Body Model: 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Machine Model: 200pF capacitor discharged directly into each pin. Electrical Characteristics (2) -40 C ð T A ð +125 C, V CC = 5.0V unless otherwise noted. Specifications are subject to change without notice. Symbol Parameter Conditions Min. Typ. Max. Units T MIN, T MAX Specified Temperature Range C Temperature Conversion Time (3) 90 ms Accuracy (4) T A = +25 C T A = +100 C T A = -40 C (T MIN ) C T A = +125 C (T MAX ) Notes: 2. These specifications are guaranteed only for the test conditions listed. 3. This specification only indicates how often temperature information is updated to the temperature register. The can be read at any time without interrupting the temperature conversion process. 4. Accuracy (expressed in C) = the difference between the output temperature and the measured temperature. Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Rev

4 Logic Electrical Characteristics Symbol Parameter Conditions Min. Typ. Max. Units V IH Minimum Input Voltage V DD x 0.7 V DD V Logic HIGH V IL Maximum Input Voltage Logic LOW -0.3 V DD x 0.3 V V OL Maximum Output Voltage Logic LOW V DD = 5V, I OL = -3mA V DD = 3V, I OL = -1.5mA I DD Quiescent Supply Current Interface Inactive R/W Activity on I DD-SD Shutdown Current Interface Inactive R/W Activity on I IN Input Leakage Current V IN = 0V or 5V, T A = 25 C -40 C < T A < 125 C I OL Output Sink Current T A = 25 C, V OL = 0.4V 3 ma I LEAK Output Leakage Current V OH = 5V, V DD = 0V µa t F Output Transition Time C L = 400pF, I OL = -3mA 250 ns C IN Input Capacitance All Digital Inputs 20 pf ±0.1 ±1.0 V V µa µa µa Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Rev

5 Serial Port Timing Symbol Parameter Conditions Min. Typ. Max. Units t Clock Period µs t T:LH, t T:HL Clock Transition Time 300 ns t LOW Clock LOW Period µs t HIGH Clock HIGH Period µs t BUF Bus free time between a Stop and 1.0 µs a new Start Condition t SU:DAT Data In Set-up to HIGH 100 ns t HD:DAT Data In Hold Time 100 ns t HD Data Out Stable after LOW 0 ns t SU:STA LOW Set-up to LOW 100 ns (Repeated Start Condition) t HD:STA HIGH Hold after LOW 100 ns (Start Condition) t SU:STO HIGH after HIGH 100 ns (Stop Condition) t POR Time in which a must be operational after a power-on reset 500 ms Data In t HD:STA t BUF t t SU:DAT t SU:STA t HD:DAT t SU:STO Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm t LOW t HIGH t T:LH t T:HL 90% 90% 10% 10% Data Out t HD Figure 3. Serial Port Timing Diagram Rev

6 Basic Operation The temperature sensing circuitry continuously produces analog voltage proportional to the device temperature. At regular intervals, the converts the analog voltage to a two s complement digital value, which is placed into the temperature register. The has an SMBus-compatible digital serial interface that allows access to the data in the temperature register at any time. In addition, the serial interface provides access to all other registers to customize operation of the device. The temperature-to-digital conversion can have 9, 10, 11, or 12-bit resolution selected, providing 0.5 C, 0.25 C, C, and C temperature resolution, respectively. At power-up, the default conversion resolution is 9-bits. The conversion resolution is controlled by the R0 and R1 bits in the configuration register. Table 1 gives examples of the relationship between the output digital data and the external temperature. The 9-bit, 10-bit, 11-bit, and 12-bit columns in Table 1 indicate the right-most bit in the output data stream that can contain temperature information for each conversion accuracy. Since the output digital data is in two s-complement format, the most significant bit of the temperature is the sign bit. If the sign bit is zero, the temperature is positive; if the sign bit is one, the temperature is negative. The has a shutdown mode that reduces the operating current to 150nA. This mode is controlled by the SD bit in the configuration register. Power-Up Default Conditions The powers up in the following default state: Thermostat mode: comparator mode OS polarity: active LOW Fault tolerance: 1 fault (i.e., F0 = 0 and F1 = 0 in the configuration register) T OS : 80 C T HYST : 75 C Register pointer: 00 (temperature register) Conversion resolution: 9 bits (i.e., R0 = 0 and R1 = 0 in the configuration register) After power-up, these conditions can be reprogrammed via the serial interface. Refer to the Serial Data Bus Operation section for programming instructions. Thermal Alarm Function The thermal alarm function provides programmable thermostat capability and allows the to function as a stand-alone thermostat without using the serial interface. The Over-Limit Signal (OS) output is the alarm output. This signal is an open-drain output and, at power-up, this pin is configured with active-low polarity. Table 1. Relationship Between Temperature and Digital Output Temperature All Temperatures Sig Number of bits used by conversion resolution Digital Output The OS polarity is controlled by the POL bit in the configuration register. The programmable upper trip-point temperature for the thermal alarm is stored in the T OS register. The programmable hysteresis temperature (i.e., the lower trip point) is stored in the T HYST register. The thermal alarm has two modes of operation: comparator mode and interrupt mode. At power-up, the default is comparator mode. The alarm mode is controlled by the CMP/INTR bit in the configuration register. Fault Tolerance For both comparator and Interrupt modes, the alarm fault tolerance setting plays a role in determining when the OS output is activated. Fault tolerance refers to the number of consecutive times an error condition must be detected before the user is notified. Higher fault tolerance settings can help eliminate false alarms caused by noise in the system. The alarm fault tolerance is controlled by bits F0 and F1 in the configuration register. These bits can be used to set the fault tolerance to 1, 2, 4, or 6, as shown in Table 4. At power-up, these bits both default to 0 (fault tolerance = 1). bit 9 bit 10 bit 11 bit 12 Always zero 12-Bit Resolution Bit Resolution Bit Resolution Bit Resolution C C C C C C C C C Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Rev

7 Comparator Mode In comparator mode, each time a temperature-to-digital (T-to-D) temperature conversion occurs, the new digital temperature is compared to the value stored in the T OS and T HYST registers. If a fault tolerance number of consecutive temperature measurements are greater than the value stored in the T OS register, the OS output is activated. For example, if bits F1 and F0 are equal to 10 (fault tolerance = 4), four consecutive temperature measurements must exceed T OS to activate the OS output. Once the OS output is active, it remains active until the first time the measured temperature drops below the temperature stored in the T HYST register. The operation of the alarm in comparator mode with fault tolerance = 2 is illustrated in Figure 4. Temperature-to-Digital Conversion T OS T HYST OS (Comparator Mode) OS (Interrupt Mode) Interrupt Mode In interrupt mode, the OS output first becomes active after a fault tolerance number of consecutive temperature measurements exceed the value stored in the T OS register (similar to comparator mode). Once OS is active, it can only be cleared by a user read any of the registers (temperature, configuration, T OS, or T HYST ) or by putting the into shutdown mode (i.e., by setting the shutdown bit in the configuration register to 1 ). Once cleared, the OS output can only be activated the next time by a fault tolerance number of consecutive temperature measurements lower than the value stored in T HYST. Once it is activated, the OS output can only be deactivated by a user read or shutdown. In interrupt mode, the activate/clear cycle for OS has the following pattern: temperature > T OS, clear, temperature < T HYST, clear, temperature > T OS, clear, etc. The operation of the alarm in interrupt mode with fault tolerance = 2 is illustrated in Figure 4. Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm For this example: Fault Tolerance = 2 Output Polarity = Active Low Read (or Shutdown) Figure 4. Thermal Alarm Operation in Comparator and Interrupt Modes Rev

8 Registers The contains the following five registers: Command Register Temperature Register Configuration Register Over-Limit-Signal Temperature Register (T OS ) Hysteresis Temperature Register (T HYST ) Command Register SD A Serial Interface Command (Pointer) Data Command Register 1-byte Write Only Read/Write Data The command register is a one-byte (8-bit) write-only register. The data stored in the command register indicates which of the other registers (temperature, configuration, T OS, or T HYST ) to read or write to during an upcoming operation. The command register points to the selected register, as shown in Figure 11. The command register is illustrated in Figure 9. The P1 and P0 bits of the command register determine which register is accessed, as shown in Table 2. The six Most Significant Bits (MSBs) of the command register must always be zero. Writing a one into any of these bits causes the current operation to be terminated. The command register retains pointer information between operations; therefore, this register only needs to be updated once for consecutive read operations the same register. All bits in the command register default to zero at power-up. Figure 5. Register Hierarchy All of these registers can be accessed by the user via the digital serial interface at any time (see Serial Interface Operation for instructions). A detailed description of these registers and their functions is provided in the following sections. A diagram of the register hierarchy is shown in Figure 5. MSB Temperature Register 2-byte Read Only Command Reg. = Configuration Register 1-byte Read/Write Command Reg. = T HYST Register 2-byte Read/Write Command Reg. = T OS Register 2-byte Read/Write Command Reg. = LSB P1 P0 Figure 6. Command Register Format Table 2. Register Assignments for Command Bits P1 and P2 Register P1 P0 Temperature Register 0 0 Configuration Register 0 1 T HYST Register 1 0 T OS Register 1 1 Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Rev

9 Temperature Register The temperature register is a two-byte (16-bit) read-only register. Digital temperatures the T-to-D converter are stored in the temperature register in two s complement format and the contents of this register are updated at regular intervals, each time the T-to-D conversion is finished. The user can read data the temperature register at any time. When a T-to-D conversion is completed, the new data is loaded into a comparator buffer to evaluate fault conditions and updates the temperature register if a read cycle is not ongoing. The is continuously evaluating fault conditions regardless of read or write activity on the bus. If a read is ongoing, the previous temperature is read. The readable temperature is updated upon the completion of the next T-to-D conversion not masked by a read cycle. The temperature register is illustrated in Figure 7. Depending on the resolution of the T-to-D conversion, the 9, 10, 11, or 12 MSBs of the register contain temperature data. All unused bits following the digital temperature are zero. The MSB position of the temperature register always contains the sign bit for the digital temperature and bit 14 contains the temperature MSB. Bits in the temperature register default to zero at power-up. MSB SB TMSB T T T T T T LSB 9-bit 10-bit 11-bit 12-bit LSB LSB LSB LSB SB = Two s complement sign bit TMSB = Temperature MSB T = Temperature data 9-bit LSB = Temperature LSB for 9-bit conversions 10-bit LSB = Temperature LSB for 10-bit conversions 11-bit LSB = Temperature LSB for 11-bit conversions 12-bit LSB = Temperature LSB for 12-bit conversions Figure 7. Temperature Register Format Configuration Register The configuration register is a one-byte (8-bit) read/write register (see Figure 8). This register allows the user to control the shutdown mode as well as the following thermal alarm features: polarity, operating mode, and fault tolerance. The configuration register contains two bits that set the fault tolerance trip point. The fault tolerance trip point is the number of consecutive times the internal circuit reads the temperature and finds the temperature outside the limits programmed. The programmed limits are defined by the T OS register for the upper limit and by the T HYST register for the lower limit. Table 4 shows the relationship between F1 and F0 and the number of consecutive errors or trips needed to activate the alarm. The configuration register also contains the two bits that set the T-to-D conversion resolution to 9, 10, 11, or 12 bits. Table 3 shows the relationship between R1 and T0 and the conversion resolution. All bits in the configuration register default to zero at power-up. MSB X R1 R0 F1 F0 POL CMP/ INT LSB SD R1 = Resolution bit 1 (see Table 3). R0 = Resolution bit 0 (see Table 3). F1 = Fault tolerance bit 1 (see Table 4). F0 = Fault tolerance bit 0 (see Table 4). POL = OS output polarity: 0 = active low, 1 = active high. CMP/INT = thermostat mode: 0 = comparator mode, 1 = inerrupt mode. SD = shutdown: 0 = normal operation, 1 = shutdown mode. Figure 8. Configuration Register Format Table 3. Conversion Resolution Settings A-to-D Conversion Resolution R1 R0 9 Bits Bits Bits Bits 1 1 Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Table 4. Fault Tolerance Settings Fault Tolerance R1 R Rev

10 Over-Limit Signal Temperature Register (T OS ) The T OS register is a two-byte (16-bit) read/write register that stores the user-programmable upper trip-point temperature for the thermal alarm in two s-complement format. At power-up, this register defaults to 80 C (i.e ). The format of the T OS register is identical to that of the temperature register (see Figure 9). The four LSBs of the T OS register are hardwired to zero, so data written to these register bits is ignored. The MSB position of the T OS register contains the sign bit for the digital temperature and bit 14 contains the temperature MSB. The resolution setting for the T-to-D conversion determines how many bits of the T OS register are used by the thermal alarm. For example, for 9-bit conversions, the trip-point temperature is defined by the nine MSBs of the T OS register and all remaining bits are ignored. MSB SB TMSB T T T T T T Figure 9. T HYST Register and T OS Register Format Hysteresis Temperature Register (T HYST ) The T HYST register is a two-byte (16-bit) read/write register that stores the programmable lower trip-point temperature for the thermal alarm in two s-complement format. At power-up, this register defaults to 75 C (i.e ). The T HYST register is illustrated in Figure 9. The format of this register is the same as that of the temperature register. The four LSBs of the T HYST register are hardwired to zero, so data written to these bits is ignored. The resolution setting for the T-to-D conversion determines how many bits of the T HYST register are used by the thermal alarm. For example, for 9-bit conversions, the hysteresis temperature is defined by the nine MSBs of the T HYST register and all remaining bits are ignored LSB 9-bit 10-bit 11-bit 12-bit LSB LSB LSB LSB SB = Two s complement sign bit TMSB = Temperature MSB T = Temperature data 9-bit LSB = Temperature LSB for 9-bit conversions 10-bit LSB = Temperature LSB for 10-bit conversions 11-bit LSB = Temperature LSB for 11-bit conversions 12-bit LSB = Temperature LSB for 12-bit conversions Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Rev

11 Serial Data Bus Operation General Operation Writing to and reading the registers is accomplished via the SMBus-compatible two-wire serial interface. SMBus protocol requires that one device on the bus initiates and controls all read and write operations. This device is called the master device. The master device also generates the signal, which is the clock signal for all other devices on the bus. All other devices on the bus are called slave devices. The is a slave device. Both the master and slave devices can send and receive data on the bus. During SMBus operations, one data bit is transmitted per clock cycle. All SMBus operations follow a repeating nine clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ACK) or not acknowledge (NACK) the receiving device. Note that there are no unused clock cycles during any operation therefore there must be no breaks in the stream of data and ACKs/NACKs during data transfers. Conversely, too few clock cycles can lead to incorrect operation if an inadvertent 8-bit read a 16-bit register occurs. For most operations, SMBus protocol requires the line to remain stable (unmoving) whenever is HIGH i.e., transitions on the line can only occur when is LOW. The exceptions to this rule are when the master device issues a start or stop signal. The slave device cannot issue a start or stop signal. Start Condition: This condition occurs when the line transitions HIGH to LOW while is HIGH. The master device uses this condition to indicate that a data transfer is about to begin. Stop Condition: This condition occurs when the line transitions LOW to HIGH while is HIGH. The master device uses this condition to signal the end of a data transfer. nowledge and Not nowledge: When data is transferred to the slave device, it sends an acknowledge (ACK) after receiving every byte of data. A master device sends an acknowledge (ACK) following only the first byte read a two-byte register. The receiving device sends an ACK by pulling LOW for one clock cycle. Following the last byte, a master device sends a not acknowledge (NACK) followed by a stop condition. A NACK is indicated by leaving HIGH during the clock after the last byte. Slave Address Each slave device on the bus has a unique 7-bit address so the master can identify which device is sending or receiving data. The address is as follows: A2 A1 A0 The four MSBs of the address are hardwired to The three LSBs are user configurable by tying the A0, A1, and A2 pins to either V DD or ground. This provides eight different addresses, which allows up to eight s to be connected to the same bus. Writing to and Reading the All read and write operations must begin with a start signal generated by the master device. After the start condition, the master device must immediately send a slave address (7 bits), followed by a read/write bit. If the slave address matches the address of the, the sends an ACK after receiving the read/write bit by pulling the line LOW for one clock cycle. Figures provide timing diagrams for all operations. Setting the Pointer For all operations, the pointer stored in the command register must be pointing to the register (temperature, configuration, T OS or T HYST ) that is going to be written to or read. To change the pointer value in the command register, the read/write bit following the address must be 0. This indicates that the master will write new information into the command register. After the sends an ACK in response to receiving the address and read/write bit, the master device must transmit an appropriate 8-bit pointer value, as explained in the Registers section. The sends an ACK after receiving the new pointer data. The pointer set operation is illustrated in Figure 11. Anytime a pointer set is performed, it must be immediately followed by a read or write operation. Note that the six MSBs of the pointer value must be zero. If the six MSBs are not zero, the does not send an ACK and internally terminates the operation. The command register retains the current pointer value between operations; therefore, once a register is indicated, subsequent read operations do not require a pointer set cycle. Write operations always require the pointer be reset. Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Rev

12 Reading If the pointer is already pointing to the desired register, the master can read that register by setting the read/write bit (following the slave address) to a one. After sending an ACK, the begins transmitting data during the following clock cycle. If the configuration register is being read, the transmits one byte of data (see Figure 13). The master should respond with a NACK, followed by a stop condition. If the temperature, T OS, or T HYST register is being read, the transmits two bytes of data (see Figure 12). The master must respond to the first byte of data with an ACK and to the second byte of data with a NACK followed by a stop condition. To read a register other than the one currently indicated by the command register, a pointer to the desired register must be set. Immediately following the pointer set, the master must perform a repeat start condition (see Figure 11 and Figure 15), which indicates to the that a new operation is about to occur. If the repeat start condition does not occur, the assumes that a write is taking place and the selected register is overwritten by the upcoming data on the data bus. After the start condition, the master must again send the device address and read/write bit. This time, the read/ write bit must be set to one to indicate a read. The rest of the read cycle is the same as described in the previous paragraph for reading a preset pointer location. Start A2 A1 A0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 Most Significant Data Byte ( ) Writing All writes must be proceeded by a pointer set, even if the pointer is already pointing to the desired register. Immediately following the pointer set, the master must begin transmitting the data to be written. If the master is writing to the configuration register, one byte of data must be sent (see Figure 16). If the T OS or T HYST register is being written, the master must send two bytes of data (see Figure 14). After transmitting each byte of data, the master must release the Serial Data () line for one clock cycle to allow the to acknowledge receiving the byte. The write operation should be terminated by a stop signal the master. Caution: Inadvertent 8-Bit Read a 16-Bit Register An inadvertent 8-bit read a 16-bit register, with the D7 bit LOW, can cause the to pause in a state where the line is pulled LOW by the output data and is incapable of receiving either a stop or a start condition the master. The only way to remove the this state is to continue clocking for nine cycles until goes HIGH, at which time issuing a stop condition resets the, shown in Figure 10. N No D7 Stop intended by, but line locked low Nine additional clock cycles to reset the D6 D5 D4 D3 D2 D1 D0 must detect error condition on N No Stop Condition Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Figure 10. Inadvertent 8-Bit Read 16-Bit Register Where D7 = 0 and Forces Output LOW Rev

13 Timing Diagrams S A2 A1 A0 R/W A P1 P0 A S Repeat Start S Note: This segment of this timing diagram is a generic pointer set cycle that must be followed by either an immediate read cycle or write cycle, as shown in this figure and in figures 10, 11, and 12. Pointer Byte Most Significant Data Byte ( ) ats A2 A1 A0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D N Least Significant Data Byte ( ) Figure 11. Pointer Set Followed by Immediate Read a Two-byte Register (Temperature, T OS, or T HYST Register) A2 A1 A0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D N Address Byte Most Significant Data Byte ( ) Least Significant Data Byte ( ) No P No P Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Figure 12. Two-byte Read Preset Pointer Location (Temperature, T OS, or T HYST Register) S A2 A1 A0 R/W A X D6 D5 D4 D3 D2 D1 D0 N P Data Byte ( ) No Figure 13. One-byte Read Configuration Register with Preset Pointer Rev

14 Timing Diagrams (Continued) S A2 A1 A0 R/W A A P1 P0 Pointer Byte Figure 14. Pointer Set Followed by Immediate Write to A 2-byte Register (T OS or T HYST Register) A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D Most Significant Data Byte ( ) S A2 A1 A0 R/W A P1 P0 A Pointer Byte 0 1 A2 A1 A0 R/W A (repeated here for clarity, transmitted only once in the actual sequence) Least Significant Data Byte ( ) S Repeat Start A A2 A1 A0 R/W X D6 D5 D4 D3 D2 D1 D0 Data Byte ( ) N No P P Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Figure 15. Pointer Set Followed by Immediate Read Configuration Register S A2 A1 A0 R/W A P1 P0 A Pointer Byte X D6 D5 D4 D3 D2 D1 D0 P A Data Byte ( ) Figure 16. Pointer Set Followed by Immediate Write to the Configuration Register Rev

15 Mechanical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm Figure 17. Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8) Rev

16 Rev Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm