256K (32K x 8) OTP EPROM AT27C256R 256K EPROM. Features. Description. Pin Configurations
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1 Features Fast Read Access Time - 45 ns Low-Power CMOS Operation 100 µa max. Standby 20 ma max. Active at 5 MHz JEDEC Standard Packages 28-Lead 600-mil PDIP 32-Lead PLCC 28-Lead TSOP and SOIC 5V ± 10% Supply High Reliability CMOS Technology 2,000V ESD Protection 200 ma Latchup Immunity Rapid Programming Algorithm µs/byte (typical) CMOS and TTL Compatible Inputs and Outputs Integrated Product Identification Code Commercial, Industrial and Automotive Temperature Ranges Description The is a low-power, high-performance 262,144-bit one-time programmable read only memory (OTP EPROM) organized 32K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 45 ns, eliminating the need for speed reducing WAIT states on high-performance microprocessor systems. Atmel s scaled CMOS technology provides low-active power consumption, and fast programming. Power consumption is typically only 8 ma in Active Mode and less than 10 µa in Standby. (continued) PDIP, SOIC Top View Pin Configurations Pin Name A0 - A14 O0 - O7 CE OE NC Note: A6 A5 A4 A3 A2 A1 A0 NC O0 Function Addresses Outputs Chip Enable Output Enable No Connect PLCC Top View A7 A12 VPP NC VCC A14 A O1 O2 GND NC O3 O4 O A8 A9 A11 NC OE A10 CE O7 O6 PLCC Package Pins 1 and 17 are DON T CONNECT. OE A11 A9 A8 A13 A14 VCC VPP A12 A7 A6 A5 A4 A VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND VCC A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 TSOP Top View Type A10 CE O7 O6 O5 O4 O3 GND O2 O1 O0 A0 A1 A2 256K (32K x 8) OTP EPROM 256K EPROM Rev. 0014H 07/98 1
2 The is available in a choice of industry standard JEDEC-approved one time programmable (OTP) plastic DIP, PLCC, SOIC, and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention. With 32K byte storage capability, the allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel s 27C256R has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages. System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µf high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µf bulk electrolytic capacitor should be utilized, again connected between the V CC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. Block Diagram 2
3 Absolute Maximum Ratings* Temperature Under Bias C to +125 C Storage Temperature C to +150 C Voltage on Any Pin with Respect to Ground V to +7.0V (1) Voltage on A9 with Respect to Ground V to +14.0V (1) *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V PP Supply Voltage with Respect to Ground V to +14.0V (1) Note: 1. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns.maximum output pin voltage is V CC V dc which may overshoot to +7.0 volts for pulses of less than 20 ns. Operating Modes Mode\Pin CE OE Ai V PP Outputs Read V IL V IL Ai V CC D OUT Output Disable V IL V IH X (1) V CC High Z Standby V IH X (1) X (1) V CC High Z Rapid Program (2) V IL V IH Ai V PP D IN PGM Verify (2) X (1) V IL Ai V PP D OUT Optional PGM Verify (2) V IL V IL Ai V CC D OUT PGM Inhibit (2) V IH V IH X (1) V PP High Z V Identification Code Product Identification (4) V IL V IL A0 = V IH or V IL (3) A9 = V H A1 - A14 = V IL CC Notes: 1. X can be V IL or V IH. 2. Refer to Programming Characteristics. 3. V H = 12.0 ± 0.5V. 4. Two identifier bytes may be selected. All Ai inputs are held low (V IL ), except A9 which is set to V H and A0 which is toggled low (V IL ) to select the Manufacturer s Identification byte and high (V IH ) to select the Device Code byte. 3
4 DC and AC Operating Conditions for Read Operation Operating Temp. (Case) Com. 0 C - 70 C 0 C - 70 C 0 C - 70 C 0 C - 70 C 0 C - 70 C 0 C - 70 C Ind. -40 C - 85 C -40 C - 85 C -40 C - 85 C -40 C - 85 C -40 C - 85 C -40 C - 85 C Auto. -40 C C -40 C C -40 C C -40 C C V CC Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% DC and Operating Characteristics for Read Operation Symbol Parameter Condition Min Max Units I LI Input Load V IN = 0V to Current V Com., Ind. ±1 µa CC Auto. ±5 µa I LO Output Leakage Current V OUT = 0V to V CC Com., Ind. ±5 µa Auto. ±10 µa I PP1 (2) V PP (1) Read/Standby Current V PP = V CC 10 µa I SB V CC (1) Standby Current I SB1 (CMOS), CE = V CC ± 0.3V 100 µa I SB2 (TTL), CE = 2.0 to V CC + 0.5V 1 ma I CC V CC Active Current f = 5 MHz, I OUT = 0 ma, E = V IL 20 ma V IL Input Low Voltage V V IH Input High Voltage 2.0 V CC V V OL Output Low Voltage I OL = 2.1 ma 0.4 V V OH Output High Voltage I OH = -400 µa 2.4 V Notes: 1. V CC must be applied simultaneously with or before V PP, and removed simultaneously with or after V PP.. 2. V PP may be connected directly to V CC, except during programming. The supply current would then be the sum of I CC and I PP.. AC Characteristics for Read Operation Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Units t ACC (3) t CE (2) t OE (2)(3) Address to Output Delay CE = OE = V IL ns CE to Output Delay OE = V IL ns OE to Output Delay CE = V IL ns t DF (4)(5) OE or CE High to Output Float, whichever occurred first ns t OH Note: Output Hold from Address, CE or OE, ns whichever occurred first 2, 3, 4, 5. - see AC Waveforms for Read Operation. 4
5 AC Waveforms for Read Operation (1) Notes: 1. Timing measurement reference level is 1.5V for -45 and -55 devices. Input AC drive levels are V IL = 0.0V and V IH = 3.0V. Timing measurement reference levels for all other speed grades are V OL = 0.8V and V OH = 2.0V. Input AC drive levels are V IL = 0.45V and V IH = 2.4V. 2. OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE. 3. OE may be delayed up to t ACC - t OE after the address is valid without impact on t ACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven. Input Test Waveforms and Measurement Levels For -45 and -55 devices only: Output Test Load t R, t F < 5 ns (10% to 90%) For -70, -90, -12, and -15 devices: Note: C L = 100 pf including jig capacitance, except for the -45 and -55 devices, where C L =30 pf. t R, t F < 20 ns (10% to 90%) Pin Capacitance f = 1 MHz, T = 25 C (1) Symbol Typ Max Units Conditions C IN 4 6 pf V IN = 0V C OUT 8 12 pf V OUT = 0V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 5
6 Programming Waveforms (1) Notes: 1. The Input Timing Reference is 0.8V for V IL and 2.0V for V IH. 2. t OE and t DFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the a 0.1 µf capacitor is required across V PP and ground to suppress spurious voltage transients. DC Programming Characteristics T A = 25 ± 5 C, V CC = 6.5 ± 0.25V, V PP = 13.0 ± 0.25V Limits Symbol Parameter Test Conditions Min Max Units I LI Input Load Current V IN = V IL,V IH ±10 µa V IL Input Low Level V V IH Input High Level 2.0 V CC + 1 V V OL Output Low Volt I OL = 2.1 ma 0.4 V V OH Output High Volt I OH = -400 µa 2.4 V I CC2 V CC Supply Current (Program and Verify) 25 ma I PP2 V PP Current CE = V IL 25 ma V ID A9 Product Identification Voltage V 6
7 AC Programming Characteristics T A = 25 ± 5 C, V CC = 6.5 ± 0.25V, V PP = 13.0 ± 0.25V Symbol Parameter Test Conditions (1) Min Max Units Limits t AS Address Setup Time 2 µs t OES OE Setup Time 2 µs t DS Data Setup Time Input Rise and Fall Times 2 µs t AH Address Hold Time (10% to 90%) 20ns 0 µs t DH Data Hold Time Input Pulse Levels 2 µs t DFP OE High to 0.45V to 2.4V Output Float Delay (2) ns t Input Timing Reference Level VPS V PP Setup Time 2 µs 0.8V to 2.0V t VCS V CC Setup Time 2 µs t PW CE Program Pulse Width (3) Output Timing Reference Level µs t OE Data Valid from OE (2) 0.8V to 2.0V 150 ns V t PP Pulse Rise Time PRT During Programming 50 ns Notes: 1. V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP.. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven see timing diagram. 3. Program Pulse width tolerance is 100 µsec ± 5%. Atmel s 27C256R Integrated Product Identification Code Codes Pins A0 O7 O6 O5 O4 O3 O2 O1 O0 Manufacturer E Device Type C Hex Data 7
8 Rapid Programming Algorithm A 100 µs CE pulse width is used to program. The address is set to the first location. V CC is raised to 6.5V and V PP is raised to 13.0V. Each address is first programmed with one 100 µs CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. V PP is then lowered to 5.0V and V CC to 5.0V. All bytes are read again and compared with the original data to determine if the device passes or fails. 8
9 Ordering Information t ACC I CC (ma) (ns) Active Standby JC -45PC -45RC -45TC JI -45PI -45RI -45TI JC -55PC -55RC -55TC JI -55PI -55RI -55TI JC -70PC -70RC -70TC JI -70PI -70RI -70TI JA -70PA -70RA Ordering Code Package Operation Range Commercial (0 C to 70 C) Industrial (-40 C to 85 C) Commercial (0 C to 70 C) Industrial (-40 C to 85 C) Commercial (0 C to 70 C) Industrial (-40 C to 85 C) Automotive (-40 C to 125 C) (continued) Package Type 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28-Lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) 28-Lead, Thin Small Outline Package (TSOP) 9
10 Ordering Information (Continued) t ACC (ns) Active I CC (ma) Standby JC -90PC -90RC -90TC JI -90PI -90RI -90TI JA -90PA -90RA JC -12PC -12RC -12TC JI -12PI -12RI -12TI JA -12PA -12RA JC -15PC -15RC -15TC JI -15PI -15RI -15TI JA -15PA -15RA Ordering Code Package Operation Range Commercial (0 C to 70 C) Industrial (-40 C to 85 C) Automotive (-40 C to 125 C) Commercial (0 C to 70 C) Industrial (-40 C to 85 C) Automotive (-40 C to 125 C) Commercial (0 C to 70 C) Industrial (-40 C to 85 C) Automotive (-40 C to 125 C) Package Type 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28-Lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) 28-Lead, Thin Small Outline Package (TSOP) 10
11 Packaging Information, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE, 28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-011 AB.045(1.14) X 45 PIN NO. 1 IDENTIFY.025(.635) X (.305).008(.203) 1.47(37.3) 1.44(36.6) PIN 1.032(.813).026(.660).050(1.27) TYP.453(11.5).447(11.4).495(12.6).485(12.3).553(14.0).547(13.9).595(15.1).585(14.9).300(7.62) REF.430(10.9).390(9.90) AT CONTACT POINTS.022(.559) X 45 MAX (3X).530(13.5).490(12.4).021(.533).013(.330).030(.762).015(.381).095(2.41).060(1.52).140(3.56).120(3.05) SEATING PLANE.220(5.59) MAX.161(4.09).125(3.18).110(2.79).090(2.29).012(.305).008(.203) 1.300(33.02) REF.065(1.65).041(1.04).630(16.0).590(15.0).690(17.5).610(15.5) 0 15 REF.566(14.4).530(13.5).090(2.29) MAX.005(.127) MIN.065(1.65).015(.381).022(.559).014(.356), 28-Lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters), 28-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* INDEX MARK AREA 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516) 0.55 (0.022) BSC 0.27 (0.011) 0.18 (0.007) 7.15 (0.281) REF 8.10 (0.319) 7.90 (0.311) 1.25 (0.049) 1.05 (0.041) 0.20 (0.008) 0.10 (0.004) 0 5 REF 0.20 (0.008) 0.15 (0.006) 0.70 (0.028) 0.30 (0.012) *Controlling dimension: millimeters 11
12 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA TEL (408) FAX (408) Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) FAX (44) Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO TEL (719) FAX (719) Atmel Rousset Zone Industrielle Rousset Cedex, France TEL (33) FAX (33) Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon, Hong Kong TEL (852) FAX (852) Japan Atmel Japan K.K. Tonetsu Shinkawa Bldg., 9F Shinkawa Chuo-ku, Tokyo Japan TEL (81) FAX (81) Fax-on-Demand North America: 1-(800) International: 1-(408) [email protected] Web Site BBS 1-(408) Atmel Corporation Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s website. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 0014H 07/98/xM
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AVR097: Migration between ATmega128 and ATmega2561 Features General Porting Considerations Memory Clock sources Interrupts Power Management BOD WDT Timers/Counters USART & SPI ADC Analog Comparator ATmega103
DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control
August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation
ICS379. Quad PLL with VCXO Quick Turn Clock. Description. Features. Block Diagram
Quad PLL with VCXO Quick Turn Clock Description The ICS379 QTClock TM generates up to 9 high quality, high frequency clock outputs including a reference from a low frequency pullable crystal. It is designed
DM74157 Quad 2-Line to 1-Line Data Selectors/Multiplexers
DM74157 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four out-put gates.
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary General Description This device contains two independent negative-edge-triggered
MM74HC4538 Dual Retriggerable Monostable Multivibrator
MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicon-gate CMOS technology. They feature
DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation
4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
DM74184 DM74185A BCD-to-Binary and Binary-to-BCD Converters
DM74184 DM74185A BCD-to-Binary and Binary-to-BCD Converters General Description These monolithic converters are derived from the 256-bit read only memories DM5488 and DM7488 Emitter connections are made
DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs
DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7-segment decoder driver incorporating input latches and constant current output circuits
Quad 2-Line to 1-Line Data Selectors Multiplexers
54LS157 DM54LS157 DM74LS157 54LS158 DM54LS158 DM74LS158 Quad 2-Line to 1-Line Data Selectors Multiplexers General Description These data selectors multiplexers contain inverters and drivers to supply full
CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
How To Power A Power Supply On A Microprocessor (Mii) Or Microprocessor Power Supply (Miio) (Power Supply) (Microprocessor) (Miniio) Or Power Supply Power Control (Power) (Mio) Power Control
November 200 HI-010, HI-110 CMOS High oltage Display Driver GENERAL DESCRIPTION PIN CONFIGURATION (Top iew) The HI-010 & HI-110 high voltage display drivers are constructed of MOS P Channel and N Channel
8-bit Microcontroller. Application Note. AVR222: 8-point Moving Average Filter
AVR222: 8-point Moving Average Filter Features 31-word Subroutine Filters Data Arrays up to 256 Bytes Runable Demo Program Introduction The moving average filter is a simple Low Pass FIR (Finite Impulse
DM54161 DM74161 DM74163 Synchronous 4-Bit Counters
DM54161 DM74161 DM74163 Synchronous 4-Bit Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The 161
ATF1500AS Device Family. Application Note. In-System Programming of Atmel ATF1500AS Devices on the HP3070. Introduction.
In-System Programming of Atmel ATF1500AS Devices on the HP3070 Introduction In-System Programming (ISP) support of Programmable Logic Devices (PLD) is becoming a requirement for customers using Automated
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control
54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control General Description This circuit is a synchronous reversible up down counter The 191 is a 4-bit binary counter Synchronous
Step Motor Controller. Application Note. AVR360: Step Motor Controller. Theory of Operation. Features. Introduction
AVR360: Step Motor Controller Features High-Speed Step Motor Controller Interrupt Driven Compact Code (Only 10 Bytes Interrupt Routine) Very High Speed Low Computing Requirement Supports all AVR Devices
DM74LS157 DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers
September 1986 Revised April 2000 DM74LS157 DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description These data selectors/multiplexers contain inverters and drivers to supply full
54157 DM54157 DM74157 Quad 2-Line to 1-Line Data Selectors Multiplexers
54157 DM54157 DM74157 Quad 2-Line to 1-Line Data Selectors Multiplexers General Description These data selectors multiplexers contain inverters and drivers to supply full on-chip data selection to the
HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION
BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION QUIESCENT CURRENT SPECIF. UP TO 20V OPERATION OF LIQUID CRYSTALS WITH CMOS CIRCUITS PROVIDES ULTRA LOW POWER DISPLAY. EQUIVALENT AC OUTPUT DRIVE
INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook
INTEGRATED CIRCUITS 1996 Jan 05 IC15 Data Handbook FEATURES Non-inverting outputs Separate enable for each section Common select inputs See 74F253 for 3-State version PIN CONFIGURATION Ea 1 S1 2 I3a 3
74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops
HCC/HCF4032B HCC/HCF4038B
HCC/HCF4032B HCC/HCF4038B TRIPLE SERIAL ADDERS INERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS FULLY STATIC OPERATION...DC TO 10MHz (typ.) @ DD = 10 BUFFERED INPUTS AND OUTPUTS SINGLE-PHASE
Two-wire Serial EEPROM AT24C1024 (1)
Features Low-voltage Operation 2.7 (V CC = 2.7V to 5.5V) Internally Organized 131,072 x 8 Two-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol
54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock
54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock General Description This circuit is a synchronous up down 4-bit binary counter Synchronous operation is provided by
1 Mbit (128K x8) Page-Write EEPROM GLS29EE010
1 Mbit (128K x8) Page-Write EEPROM 1Mb (x8) Page-Write, Small-Sector flash memories FEATURES: Single Voltage Read and Write Operations 4.5-5.5V for Superior Reliability Endurance: 100,000 Cycles (typical)
54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter
54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting
DM74LS169A Synchronous 4-Bit Up/Down Binary Counter
Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation
3-output Laser Driver for HD-DVD/ Blu-ray/DVD/ CD-ROM ATR0885. Preliminary. Summary. Features. Applications. 1. Description
Features Three Selectable Outputs All Outputs Can Be Used Either for Standard (5V) or High Voltage (9V) Maximum Output Current at All Outputs Up to 150 ma On-chip Low-EMI RF Oscillator With Spread-spectrum
LOW POWER SCHOTTKY. http://onsemi.com GUARANTEED OPERATING RANGES ORDERING INFORMATION
The TTL/MSI SN74LS151 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS151 can be used as a universal function
HCC4541B HCF4541B PROGRAMMABLE TIMER
HCC4541B HCF4541B PROGRAMMABLE TIMER 16 STAGE BINARI COUNTER LOW SYMMETRICAL OUTPUT RESISTANCE, TYPICALLY 100 OHM AT DD = 15 OSCILLATOR FREQUENCY RANGE : DC TO 100kHz AUTO OR MASTER RESET DISABLES OSCIL-
The 74LVC1G11 provides a single 3-input AND gate.
Rev. 8 17 September 2015 Product data sheet 1. General description The provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
DS2187 Receive Line Interface
Receive Line Interface www.dalsemi.com FEATURES Line interface for T1 (1.544 MHz) and CEPT (2.048 MHz) primary rate networks Extracts clock and data from twisted pair or coax Meets requirements of PUB
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides
DS1621 Digital Thermometer and Thermostat
www.maxim-ic.com FEATURES Temperature measurements require no external components Measures temperatures from -55 C to +125 C in 0.5 C increments. Fahrenheit equivalent is -67 F to 257 F in 0.9 F increments
AVR305: Half Duplex Compact Software UART. 8-bit Microcontrollers. Application Note. Features. 1 Introduction
AVR305: Half Duplex Compact Software UART Features 32 Words of Code, Only Handles Baud Rates of up to 38.4 kbps with a 1 MHz XTAL Runs on Any AVR Device Only Two Port Pins Required Does Not Use Any Timer
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised March 2002 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
74AC191 Up/Down Counter with Preset and Ripple Clock
74AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature
5485 DM5485 DM7485 4-Bit Magnitude Comparators
5485 DM5485 DM7485 4-Bit Magnitude Comparators General Description These 4-bit magnitude comparators perform comparison of straight binary or BCD codes Three fully-decoded decisions about two 4-bit words
PS323. Precision, Single-Supply SPST Analog Switch. Features. Description. Block Diagram, Pin Configuration, and Truth Table. Applications PS323 PS323
Features ÎÎLow On-Resistance (33-ohm typ.) Minimizes Distortion and Error Voltages ÎÎLow Glitching Reduces Step Errors in Sample-and-Holds. Charge Injection, 2pC typ. ÎÎSingle-Supply Operation (+2.5V to
AVR134: Real Time Clock (RTC) using the Asynchronous Timer. 8-bit Microcontrollers. Application Note. Features. 1 Introduction
AVR134: Real Time Clock (RTC) using the Asynchronous Timer Features Real Time Clock with Very Low Power Consumption (4 μa @ 3.3V) Very Low Cost Solution Adjustable Prescaler to Adjust Precision Counts
AVR319: Using the USI module for SPI communication. 8-bit Microcontrollers. Application Note. Features. Introduction
AVR319: Using the USI module for SPI communication Features C-code driver for SPI master and slave Uses the USI module Supports SPI Mode 0 and 1 Introduction The Serial Peripheral Interface (SPI) allows
XR-T5683A PCM Line Interface Chip
...the analog plus company TM XR-T5683A PCM Line Interface Chip FEATURES Single 5V Supply Receiver Input Can Be Either Balanced or Unbalanced Up To 8.448Mbps Operation In Both Tx and Rx Directions TTL
. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE
HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE. MEDIUM SPEED OPERATION - 8MHz (typ.) @ CL = 50pF AND DD-SS = 10. MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RES-
74HCU04. 1. General description. 2. Features and benefits. 3. Ordering information. Hex unbuffered inverter
Rev. 7 8 December 2015 Product data sheet 1. General description The is a hex unbuffered inverter. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to
X9C102/103/104/503. Terminal Voltages ±5V, 100 Taps. Digitally-Controlled (XDCP) Potentiometer
APPLICATION NOTE A V A I L A B L E AN20 AN42 53 AN71 AN73 AN88 AN91 92 AN115 Terminal Voltages ±5V, 100 Taps X9C102/103/104/503 Digitally-Controlled (XDCP) Potentiometer FEATURES Solid-State Potentiometer
IR2117(S)/IR2118(S) & (PbF)
Data Sheet No. PD14 Rev N IR2117(S)/IR211(S) & (PbF) Features Floating channel designed for bootstrap operation Fully operational to +V Tolerant to negative transient voltage dv/dt immune Gate drive supply
AVR106: C functions for reading and writing to Flash memory. 8-bit Microcontrollers. Application Note. Features. Introduction
AVR106: C functions for reading and writing to Flash memory Features C functions for accessing Flash memory - Byte read - Page read - Byte write - Page write Optional recovery on power failure Functions
SPREAD SPECTRUM CLOCK GENERATOR. Features
DATASHEET ICS7152 Description The ICS7152-01, -02, -11, and -12 are clock generators for EMI (Electro Magnetic Interference) reduction (see below for frequency ranges and multiplier ratios). Spectral peaks
CD4511BM CD4511BC BCD-to-7 Segment Latch Decoder Driver
CD4511BM CD4511BC BCD-to-7 Segment Latch Decoder Driver General Description The CD4511BM CD4511BC BCD-to-seven segment latch decoder driver is constructed with complementary MOS (CMOS) enhancement mode
