Two-wire Serial EEPROM AT24C01A (1) AT24C02 (2) AT24C04 AT24C08A AT24C16A (3)

Transcription

1 Faturs Low-voltag and Standard-voltag Opration 2.7 (V CC = 2.7V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Intrnally Organizd 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) Two-wir Srial Intrfac Schmitt Triggr, Filtrd Inputs for Nois Supprssion Bidirctional Data Transfr Protocol 100 khz (1.8V) and 400 khz (2.7V, 5V) Compatibility Writ Protct Pin for Hardwar Data Protction 8-byt Pag (1K, 2K), 16-byt Pag (4K, 8K, 16K) Writ Mods Partial Pag Writs Allowd Slf-timd Writ Cycl (5 ms max) High-rliability Enduranc: 1 Million Writ Cycls Data Rtntion: 100 Yars Automotiv Dvics Availabl 8-lad JEDEC PDIP, 8-lad JEDEC SOIC, 8-lad Ultra Thin Mini-MAP (MLP 2x3), 5-lad SOT23, 8-lad TSSOP and 8-ball dbga2 Packags Di Sals: Wafr Form, Waffl Pack and Bumpd Wafrs Dscription Th AT24C01A/02/04/08A/16A provids 1024/2048/4096/8192/16384 bits of srial lctrically rasabl and programmabl rad-only mmory (EEPROM) organizd as 128/256/512/1024/2048 words of 8 bits ach. Th dvic is optimizd for us in many industrial and commrcial applications whr low-powr and low-voltag opration ar ssntial. Th AT24C01A/02/04/08A/16A is availabl in spac-saving 8-lad PDIP, 8-lad JEDEC SOIC, 8-lad Ultra Thin Mini-MAP (MLP 2x3), 5-lad SOT23 (AT24C01A/AT24C02/AT24C04), 8-lad TSSOP, and 8-ball dbga2 packags and is accssd via a Two-wir srial intrfac. In addition, th ntir family is availabl in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) vrsions. 8-lad TSSOP 8-lad SOIC Tabl 1. Pin Configuration Pin Nam A0 - A2 SDA SCL WP NC GND VCC Function Addrss Inputs Srial Data Srial Clock Input Writ Protct No Connct Ground Powr Supply A0 A1 A2 GND VCC WP SCL SDA A0 A1 A2 GND ball dbga2 8-lad PDIP Bottom Viw VCC WP SCL SDA A0 A1 A2 GND VCC WP SCL SDA A0 A1 A2 GND lad Ultra Thin Mini-MAP (MLP 2x3) VCC WP SCL SDA SCL GND SDA Bottom Viw 5-lad SOT A0 A1 A2 GND WP VCC WP SCL SDA VCC Two-wir Srial EEPROM 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) 16K (2048 x 8) AT24C01A (1) AT24C02 (2) AT24C04 AT24C08A AT24C16A (3) Nots: 1. Not Rcommndd for nw dsign; Plas rfr to AT24C01B datasht. 2. Not Rcommndd for nw dsign; Plas rfr to AT24C02B datasht. 3. Not Rcommndd for nw dsign; Plas rfr to AT24C16B datasht 1

2 Absolut Maximum Ratings Oprating Tmpratur C to +125 C Storag Tmpratur C to +150 C Voltag on Any Pin with Rspct to Ground V to +7.0V Maximum Oprating Voltag V *NOTICE: Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. This is a strss rating only and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of this spcification is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct dvic rliability. DC Output Currnt ma Figur 1. Block Diagram 2 AT24C01A/02/04/08A/16A

3 AT24C01A/02/04/08A/16A Pin Dscription SERIAL CLOCK (SCL): Th SCL input is usd to positiv dg clock data into ach EEPROM dvic and ngativ dg clock data out of ach dvic. SERIAL DATA (SDA): Th SDA pin is bidirctional for srial data transfr. This pin is opn-drain drivn and may b wir-ord with any numbr of othr opn-drain or opncollctor dvics. DEVICE/PAGE ADDRESSES (A2, A1, A0): Th A2, A1 and A0 pins ar dvic addrss inputs that ar hard wird for th AT24C01A and th AT24C02. As many as ight 1K/2K dvics may b addrssd on a singl bus systm (dvic addrssing is discussd in dtail undr th Dvic Addrssing sction). Th AT24C04 uss th A2 and A1 inputs for hard wir addrssing and a total of four 4K dvics may b addrssd on a singl bus systm. Th A0 pin is a no connct and can b connctd to ground. Th AT24C08A only uss th A2 input for hardwir addrssing and a total of two 8K dvics may b addrssd on a singl bus systm. Th A0 and A1 pins ar no conncts and can b connctd to ground. Th AT24C16A dos not us th dvic addrss pins, which limits th numbr of dvics on a singl bus to on. Th A0, A1 and A2 pins ar no conncts and can b connctd to ground. WRITE PROTECT (WP): Th AT24C01A/02/04/08A/16A has a Writ Protct pin that provids hardwar data protction. Th Writ Protct pin allows normal Rad/Writ oprations whn connctd to ground (GND). Whn th Writ Protct pin is connctd to V CC, th writ protction fatur is nabld and oprats as shown in Tabl 2. Tabl 2. Writ Protct WP Pin Status Part of th Array Protctd 24C01A 24C02 24C04 24C08A 24C16A At V CC Full (1K) Array Full (2K) Array Full (4K) Array Full (8K) Array Full (16K) Array At GND Normal Rad/Writ Oprations Mmory Organization AT24C01A, 1K SERIAL EEPROM: Intrnally organizd with 16 pags of 8 byts ach, th 1K rquirs a 7-bit data word addrss for random word addrssing. AT24C02, 2K SERIAL EEPROM: Intrnally organizd with 32 pags of 8 byts ach, th 2K rquirs an 8-bit data word addrss for random word addrssing. AT24C04, 4K SERIAL EEPROM: Intrnally organizd with 32 pags of 16 byts ach, th 4K rquirs a 9-bit data word addrss for random word addrssing. AT24C08A, 8K SERIAL EEPROM: Intrnally organizd with 64 pags of 16 byts ach, th 8K rquirs a 10-bit data word addrss for random word addrssing. AT24C16A, 16K SERIAL EEPROM: Intrnally organizd with 128 pags of 16 byts ach, th 16K rquirs an 11-bit data word addrss for random word addrssing. 3

4 Tabl 3. Pin Capacitanc (1) Applicabl ovr rcommndd oprating rang from T A = 25 C, f = 1.0 MHz, V CC = +1.8V Symbol Tst Condition Max Units Conditions C I/O Input/Output Capacitanc (SDA) 8 pf V I/O = 0V C IN Input Capacitanc (A 0, A 1, A 2, SCL) 6 pf V IN = 0V Not: 1. This paramtr is charactrizd and is not 100% tstd. Tabl 4. DC Charactristics Applicabl ovr rcommndd oprating rang from: T AI = 40 C to +85 C, V CC = +1.8V to +5.5V, V CC = +1.8V to +5.5V (unlss othrwis notd) Symbol Paramtr Tst Condition Min Typ Max Units V CC1 Supply Voltag V V CC2 Supply Voltag V V CC3 Supply Voltag V I CC Supply Currnt V CC = 5.0V READ at 100 khz ma I CC Supply Currnt V CC = 5.0V WRITE at 100 khz ma I SB1 Standby Currnt V CC = 1.8V V IN = V CC or V SS µa I SB2 Standby Currnt V CC = 2.5V V IN = V CC or V SS µa I SB3 Standby Currnt V CC = 2.7V V IN = V CC or V SS µa I SB4 Standby Currnt V CC = 5.0V V IN = V CC or V SS µa I LI Input Lakag Currnt V IN = V CC or V SS µa I LO Output Lakag Currnt V OUT = V CC or V SS µa V IL Input Low Lvl (1) 0.6 V CC x 0.3 V V IH Input High Lvl (1) V CC x 0.7 V CC V V OL2 Output Low Lvl V CC = 3.0V I OL = 2.1 ma 0.4 V V OL1 Output Low Lvl V CC = 1.8V I OL = 0.15 ma 0.2 V Not: 1. V IL min and V IH max ar rfrnc only and ar not tstd. 4 AT24C01A/02/04/08A/16A

5 AT24C01A/02/04/08A/16A Tabl 5. AC Charactristics Applicabl ovr rcommndd oprating rang from T AI = 40 C to +85 C, V CC = +1.8V to +5.5V, V CC = +2.7V to +5.5V, CL = 1 TTL Gat and 100 pf (unlss othrwis notd) Symbol Paramtr Not: 1. This paramtr is charactrizd. 1.8-volt 2.7, 5.0-volt Min Max Min Max f SCL Clock Frquncy, SCL khz t LOW Clock Puls Width Low µs t HIGH Clock Puls Width High µs t I Nois Supprssion Tim (1) ns t AA Clock Low to Data Out Valid µs t BUF Tim th bus must b fr bfor a nw transmission can start (1) µs t HD.STA Start Hold Tim µs t SU.STA Start Stup Tim µs t HD.DAT Data In Hold Tim 0 0 µs t SU.DAT Data In Stup Tim ns t R Inputs Ris Tim (1) µs t F Inputs Fall Tim (1) ns t SU.STO Stop Stup Tim µs t DH Data Out Hold Tim ns t WR Writ Cycl Tim 5 5 ms Enduranc (1) 5.0V, 25 C, Byt Mod 1M 1M Units Writ Cycls 5

6 Dvic Opration CLOCK and DATA TRANSITIONS: Th SDA pin is normally pulld high with an xtrnal dvic. Data on th SDA pin may chang only during SCL low tim priods (s Figur 4 on pag 7). Data changs during SCL high priods will indicat a start or stop condition as dfind blow. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must prcd any othr command (s Figur 5 on pag 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. Aftr a rad squnc, th stop command will plac th EEPROM in a standby powr mod (s Figur 5 on pag 8). ACKNOWLEDGE: All addrsss and data words ar srially transmittd to and from th EEPROM in 8-bit words. Th EEPROM snds a zro to acknowldg that it has rcivd ach word. This happns during th ninth clock cycl. STANDBY MODE: Th AT24C01A/02/04/08A/16A faturs a low-powr standby mod which is nabld: (a) upon powr-up and (b) aftr th rcipt of th STOP bit and th compltion of any intrnal oprations. MEMORY RESET: Aftr an intrruption in protocol, powr loss or systm rst, any 2- wir part can b rst by following ths stps: 1. Clock up to 9 cycls. 2. Look for SDA high in ach cycl whil SCL is high. 3. Crat a start condition. 6 AT24C01A/02/04/08A/16A

7 AT24C01A/02/04/08A/16A Bus Timing Figur 2. SCL: Srial Clock, SDA: Srial Data I/O Writ Cycl Timing Figur 3. SCL: Srial Clock, SDA: Srial Data I/O SCL SDA 8th BIT ACK WORDn STOP CONDITION t wr (1) START CONDITION Not: 1. Th writ cycl tim t WR is th tim from a valid stop condition of a writ squnc to th nd of th intrnal clar/writ cycl. Figur 4. Data Validity 7

8 Figur 5. Start and Stop Dfinition Figur 6. Output Acknowldg 8 AT24C01A/02/04/08A/16A

9 AT24C01A/02/04/08A/16A Dvic Addrssing Writ Oprations Th 1K, 2K, 4K, 8K and 16K EEPROM dvics all rquir an 8-bit dvic addrss word following a start condition to nabl th chip for a rad or writ opration (rfr to Figur 7). Th dvic addrss word consists of a mandatory on, zro squnc for th first four most significant bits as shown. This is common to all th EEPROM dvics. Th nxt 3 bits ar th A2, A1 and A0 dvic addrss bits for th 1K/2K EEPROM. Ths 3 bits must compar to thir corrsponding hard-wird input pins. Th 4K EEPROM only uss th A2 and A1 dvic addrss bits with th third bit bing a mmory pag addrss bit. Th two dvic addrss bits must compar to thir corrsponding hard-wird input pins. Th A0 pin is no connct. Th 8K EEPROM only uss th A2 dvic addrss bit with th nxt 2 bits bing for mmory pag addrssing. Th A2 bit must compar to its corrsponding hard-wird input pin. Th A1 and A0 pins ar no connct. Th 16K dos not us any dvic addrss bits but instad th 3 bits ar usd for mmory pag addrssing. Ths pag addrssing bits on th 4K, 8K and 16K dvics should b considrd th most significant bits of th data word addrss which follows. Th A0, A1 and A2 pins ar no connct. Th ighth bit of th dvic addrss is th rad/writ opration slct bit. A rad opration is initiatd if this bit is high and a writ opration is initiatd if this bit is low. Upon a compar of th dvic addrss, th EEPROM will output a zro. If a compar is not mad, th chip will rturn to a standby stat. BYTE WRITE: A writ opration rquirs an 8-bit data word addrss following th dvic addrss word and acknowldgmnt. Upon rcipt of this addrss, th EEPROM will again rspond with a zro and thn clock in th first 8-bit data word. Following rcipt of th 8-bit data word, th EEPROM will output a zro and th addrssing dvic, such as a microcontrollr, must trminat th writ squnc with a stop condition. At this tim th EEPROM ntrs an intrnally timd writ cycl, t WR, to th nonvolatil mmory. All inputs ar disabld during this writ cycl and th EEPROM will not rspond until th writ is complt (s Figur 8 on pag 11). PAGE WRITE: Th 1K/2K EEPROM is capabl of an 8-byt pag writ, and th 4K, 8K and 16K dvics ar capabl of 16-byt pag writs. A pag writ is initiatd th sam as a byt writ, but th microcontrollr dos not snd a stop condition aftr th first data word is clockd in. Instad, aftr th EEPROM acknowldgs rcipt of th first data word, th microcontrollr can transmit up to svn (1K/2K) or fiftn (4K, 8K, 16K) mor data words. Th EEPROM will rspond with a zro aftr ach data word rcivd. Th microcontrollr must trminat th pag writ squnc with a stop condition (s Figur 9 on pag 11). Th data word addrss lowr thr (1K/2K) or four (4K, 8K, 16K) bits ar intrnally incrmntd following th rcipt of ach data word. Th highr data word addrss bits ar not incrmntd, rtaining th mmory pag row location. Whn th word addrss, intrnally gnratd, rachs th pag boundary, th following byt is placd at th bginning of th sam pag. If mor than ight (1K/2K) or sixtn (4K, 8K, 16K) data words ar transmittd to th EEPROM, th data word addrss will roll ovr and prvious data will b ovrwrittn. 9

10 ACKNOWLEDGE POLLING: Onc th intrnally timd writ cycl has startd and th EEPROM inputs ar disabld, acknowldg polling can b initiatd. This involvs snding a start condition followd by th dvic addrss word. Th rad/writ bit is rprsntativ of th opration dsird. Only if th intrnal writ cycl has compltd will th EEPROM rspond with a zro allowing th rad or writ squnc to continu. Rad Oprations Rad oprations ar initiatd th sam way as writ oprations with th xcption that th rad/writ slct bit in th dvic addrss word is st to on. Thr ar thr rad oprations: currnt addrss rad, random addrss rad and squntial rad. CURRENT ADDRESS READ: Th intrnal data word addrss countr maintains th last addrss accssd during th last rad or writ opration, incrmntd by on. This addrss stays valid btwn oprations as long as th chip powr is maintaind. Th addrss roll ovr during rad is from th last byt of th last mmory pag to th first byt of th first pag. Th addrss roll ovr during writ is from th last byt of th currnt pag to th first byt of th sam pag. Onc th dvic addrss with th rad/writ slct bit st to on is clockd in and acknowldgd by th EEPROM, th currnt addrss data word is srially clockd out. Th microcontrollr dos not rspond with an input zro but dos gnrat a following stop condition (s Figur 10 on pag 12). RANDOM READ: A random rad rquirs a dummy byt writ squnc to load in th data word addrss. Onc th dvic addrss word and data word addrss ar clockd in and acknowldgd by th EEPROM, th microcontrollr must gnrat anothr start condition. Th microcontrollr now initiats a currnt addrss rad by snding a dvic addrss with th rad/writ slct bit high. Th EEPROM acknowldgs th dvic addrss and srially clocks out th data word. Th microcontrollr dos not rspond with a zro but dos gnrat a following stop condition (s Figur 11 on pag 12). SEQUENTIAL READ: Squntial rads ar initiatd by ithr a currnt addrss rad or a random addrss rad. Aftr th microcontrollr rcivs a data word, it rsponds with an acknowldg. As long as th EEPROM rcivs an acknowldg, it will continu to incrmnt th data word addrss and srially clock out squntial data words. Whn th mmory addrss limit is rachd, th data word addrss will roll ovr and th squntial rad will continu. Th squntial rad opration is trminatd whn th microcontrollr dos not rspond with a zro but dos gnrat a following stop condition (s Figur 12 on pag 12). 10 AT24C01A/02/04/08A/16A

11 AT24C01A/02/04/08A/16A Figur 7. Dvic Addrss MSB 8K 16K Figur 8. Byt Writ Figur 9. Pag Writ (* = DON T CARE bit for 1K) 11

12 Figur 10. Currnt Addrss Rad Figur 11. Random Rad (* = DON T CARE bit for 1K) Figur 12. Squntial Rad 12 AT24C01A/02/04/08A/16A

13 AT24C01A/02/04/08A/16A AT24C01A Ordring Information (1) Ordring Cod Packag Opration Rang AT24C01A-10PU-2.7 (2) AT24C01A-10PU-1.8 (2) AT24C01A-10SU-2.7 (2) AT24C01A-10SU-1.8 (2) AT24C01A-10TU-2.7 (2) AT24C01A-10TU-1.8 (2) AT24C01A-10TSU-1.8 (2) AT24C01AU3-10UU-1.8 (2) AT24C01AY1-10YU-1.8 (2) (Not rcommndd for nw dsign) AT24C01AY6-10YH-1.8 (3) Nots: 1. This dvic is not rcommndd for nw dsign. Plas rfr to AT24C01B datasht. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabl. 2. U dsignats Grn Packag + RoHS compliant. 3. H dsignats Grn Packag + RoHS compliant, with NiPdAu Lad Finish. 4. Availabl in waffl pack and wafr form; ordr as SL788 for inklss wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM Markting. 5TS1 8U31 8Y1 8Y6 Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) AT24C01A-W (4) Di Sal Industrial Tmpratur ( 40 C to 85 C) Packag Typ 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.150" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) 8Y1 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 8Y6 8-lad, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lad Packag (DFN), (MLP 2x3 mm) 5TS1 5-lad, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outlin Packag (SOT23) 8U3-1 8-ball, di Ball Grid Away Packag (dbga2) Options 2.7 Low-voltag (2.7V to 5.5V) 1.8 Low-voltag (1.8V to 5.5V) 13

14 AT24C02 Ordring Information (1) Ordring Cod Packag Opration Rang AT24C02-10PU-2.7 (2) AT24C02-10PU-1.8 (2) AT24C02N-10SU-2.7 (2) AT24C02N-10SU-1.8 (2) AT24C02-10TU-2.7 (2) AT24C02-10TU-1.8 (2) AT24C02Y1-10YU-1.8 (2) AT24C02-10TSU-1.8 (2) AT24C02U3-10UU-1.8 (2) 8Y1 5TS1 8U3-1 Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) AT24C02-W (3) Di Sal Industrial Tmpratur ( 40 C to 85 C) Nots: 1. This dvic is not rcommndd for nw dsign. Plas rfr to AT24C02B datasht. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabl. 2. U dsignats Grn Packag + RoHS compliant. 3. Availabl in waffl pack and wafr form; ordr as SL719 for wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM Markting. Packag Typ 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.150" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) 8Y1 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 5TS1 5-lad, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outlin Packag (SOT23) 8U3-1 8-ball, di Ball Grid Away Packag (dbga2) Options 2.7 Low-voltag (2.7V to 5.5V) 1.8 Low-voltag (1.8V to 5.5V) 14 AT24C01A/02/04/08A/16A

15 AT24C01A/02/04/08A/16A AT24C04 Ordring Information (1) Ordring Cod Packag Opration Rang AT24C04-10PU-2.7 (2) AT24C04-10PU-1.8 (2) AT24C04N-10SU-2.7 (2) AT24C04N-10SU-1.8 (2) AT24C04-10TU-2.7 (2) AT24C04-10TU-1.8 (2) AT24C04Y1-10YU-1.8 (2) (Not rcommndd for nw dsign) AT24C04Y6-10YH-1.8 (3) AT24C04-10TSU-1.8 (2) AT24C04U3-10UU-1.8 (2) 8Y1 8Y6 5TS1 8U3-1 Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) AT24C04-W (4) Di Sal Industrial Tmpratur ( 40 C to 85 C) Nots: 1. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabl. 2. U dsignats Grn Packag + RoHS compliant. 3. H dsignats Grn Packag + RoHS compliant, with NiPdAu Lad Finish. 4. Availabl in waffl pack and wafr form; ordr as SL788 for inklss wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM Markting. Packag Typ 8-lad, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.150" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) 8Y1 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 8Y6 8-lad, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lad Packag (DFN), (MLP 2x3 mm) 5TS1 5-lad, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outlin Packag (SOT23) 8U3-1 8-ball, di Ball Grid Away Packag (dbga2) Options 2.7 Low-voltag (2.7V to 5.5V) 1.8 Low-voltag (1.8V to 5.5V) 15

16 AT24C08A Ordring Information (1) Ordring Cod Packag Opration Rang AT24C08A-10PU-2.7 (2) AT24C08A-10PU-1.8 (2) AT24C08AN-10SU-2.7 (2) AT24C08AN-10SU-1.8 (2) AT24C08A-10TU-2.7 (2) AT24C08A-10TU-1.8 (2) AT24C08AY1-10YU-1.8 (2) (Not rcommndd for nw dsign) 8Y1 AT24C08AY6-10YH-1.8 (3) 8Y6 AT24C08AU2-10UU-1.8 (2 8U2-1 Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) AT24C08A-W (4) Di Sal Industrial Tmpratur ( 40 C to 85 C) Nots: 1. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabl. 2. U dsignats Grn Packag + RoHS compliant. 3. H dsignats Grn Packag + RoHS compliant, with NiPdAu Lad Finish. 4. Availabl in waffl pack and wafr form; ordr as SL788 for inklss wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM Markting. Packag Typ 8-pin, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.150" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) 8Y1 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 8Y6 8-lad, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lad Packag (DFN), (MLP 2x3 mm) 8U2-1 8-ball, di Ball Grid Array Packag (dbga2) Options 2.7 Low Voltag (2.7V to 5.5V) 1.8 Low Voltag (1.8V to 5.5V) 16 AT24C01A/02/04/08A/16A

17 AT24C01A/02/04/08A/16A AT24C16A Ordring Information (1) Ordring Cod Packag Opration Rang AT24C16A-10PU-2.7 (2) AT24C16A-10PU-1.8 (2) AT24C16AN-10SU-2.7 (2) AT24C16AN-10SU-1.8 (2) AT24C16A-10TU-2.7 (2) AT24C16A-10TU-1.8 (2) AT24C16AY1-10YU-1.8 (2) (Not rcommndd for nw dsign) AT24C16AY6-10YH-1.8 (3) AT24C16AU2-10UU-1.8 (2) AT24C16A-W (3) 8Y1 8Y6 8U2-1 Di Sal Lad-fr/Halogn-fr/ Industrial Tmpratur ( 40 C to 85 C) Industrial Tmpratur ( 40 C to 85 C) Nots: 1. This dvic is not rcommndd for nw dsign. Plas rfr to AT24C16B datasht. For 2.7V dvics usd in th 4.5V to 5.5V rang, plas rfr to prformanc valus in th AC and DC charactristics tabl. 2. U dsignats Grn Packag + RoHS compliant. 3. H dsignats Grn Packag + RoHS compliant, with NiPdAu Lad Finish. 4. Availabl in waffl pack and wafr form; ordr as SL788 for inklss wafr form. Bumpd di availabl upon rqust. Plas contact Srial EEPROM Markting. Packag Typ 8-pin, 0.300" Wid, Plastic Dual Inlin Packag (PDIP) 8-lad, 0.150" Wid, Plastic Gull Wing Small Outlin (JEDEC SOIC) 8-lad, 0.170" Wid, Thin Shrink Small Outlin Packag (TSSOP) 8Y1 8-lad, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-ladd, Miniatur Array Packag (MAP) 8Y6 8-lad, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lad Packag (DFN), (MLP 2x3 mm) 8U2-1 8-ball, di Ball Grid Array Packag (dbga2) Options 2.7 Low Voltag (2.7V to 5.5V) 1.8 Low Voltag (1.8V to 5.5V) 17

18 Packaging Information PDIP 1 E E1 N Top Viw c A End Viw D1 D A2 A COMMON DIMENSIONS (Unit of Masur = inchs) SYMBOL MIN NOM MAX NOTE A A b b b c b3 4 PLCS b2 b L D D E E Sid Viw BSC A BSC 4 L Nots: R 1. This drawing is for gnral information only; rfr to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimnsions A and L ar masurd with th packag satd in JEDEC sating plan Gaug GS D, D1 and E1 dimnsions do not includ mold Flash or protrusions. Mold Flash or protrusions shall not xcd inch. 4. E and A masurd with th lads constraind to b prpndicular to datum. 5. Pointd or roundd lad tips ar prfrrd to as insrtion. 6. b2 and b3 maximum dimnsions do not includ Dambar protrusions. Dambar protrusions shall not xcd (0.25 mm) Orchard Parkway San Jos, CA TITLE, 8-lad, 0.300" Wid Body, Plastic Dual In-lin Packag (PDIP) DRAWING NO. 01/09/02 REV. B 18 AT24C01A/02/04/08A/16A

19 AT24C01A/02/04/08A/16A JEDEC SOIC C 1 E E1 N L Top Viw End Viw B A COMMON DIMENSIONS (Unit of Masur = mm) D Sid Viw A1 SYMBOL MIN NOM MAX NOTE A A b C D E E BSC L Not: Ths drawings ar for gnral information only. Rfr to JEDEC Drawing MS-012, Variation AA for propr dimnsions, tolrancs, datums, tc. 10/7/03 R 1150 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE, 8-lad (0.150" Wid Body), Plastic Gull Wing Small Outlin (JEDEC SOIC) DRAWING NO. REV. B 19

20 TSSOP Pin 1 indicator this cornr E1 E L1 N Top Viw L End Viw b D Sid Viw A2 A COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE D , 5 E 6.40 BSC E , 5 A 1.20 A b BSC L L REF Nots: 1. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-153, Variation AA, for propr dimnsions, tolrancs, datums, tc. 2. Dimnsion D dos not includ mold Flash, protrusions or gat burrs. Mold Flash, protrusions and gat burrs shall not xcd 0.15 mm (0.006 in) pr sid. 3. Dimnsion E1 dos not includ intr-lad Flash or protrusions. Intr-lad Flash and protrusions shall not xcd 0.25 mm (0.010 in) pr sid. 4. Dimnsion b dos not includ Dambar protrusion. Allowabl Dambar protrusion shall b 0.08 mm total in xcss of th b dimnsion at maximum matrial condition. Dambar cannot b locatd on th lowr radius of th foot. Minimum spac btwn protrusion and adjacnt lad is 0.07 mm. 5. Dimnsion D and E1 to b dtrmind at Datum Plan H. 5/30/02 R 2325 Orchard Parkway San Jos, CA TITLE, 8-lad, 4.4 mm Body, Plastic Thin Shrink Small Outlin Packag (TSSOP) DRAWING NO. REV. B 20 AT24C01A/02/04/08A/16A

21 AT24C01A/02/04/08A/16A 8Y1 MAP PIN 1 INDEX AREA A PIN 1 INDEX AREA E1 D D1 L E A1 b Top Viw End Viw Bottom Viw Sid Viw A COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 0.90 A D E D E b TYP L /28/03 R 2325 Orchard Parkway San Jos, CA TITLE 8Y1, 8-lad (4.90 x 3.00 mm Body) MSOP Array Packag (MAP) Y1 DRAWING NO. 8Y1 REV. C 21

22 8Y6 Mini-MAP (MLP 2x3 mm) A D2 b (8X) Pin 1 Indx Ara E E2 Pin 1 ID L (8X) D A2 A1 (6X) 1.50 REF. A3 COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE D 2.00 BSC E 3.00 BSC D E A A A A REF L BSC b Nots: 1. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-229, for propr dimnsions, tolrancs, datums, tc. 2. Dimnsion b applis to mtallizd trminal and is masurd btwn 0.15 mm and 0.30 mm from th trminal tip. If th trminal has th optional radius on th othr nd of th trminal, th dimnsion should not b masurd in that radius ara. 8/26/05 R 2325 Orchard Parkway San Jos, CA TITLE 8Y6, 8-lad 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lad Packag (DFN),(MLP 2x3) DRAWING NO. 8Y6 REV. C 22 AT24C01A/02/04/08A/16A

23 AT24C01A/02/04/08A/16A 5TS1 SOT C E1 E C L L1 1 2 Top Viw 3 End Viw b A2 A Sating Plan A1 NOTES: 1. This drawing is for gnral information only. Rfr to JEDEC Drawing MO-193, Variation AB, for additional information. 2. Dimnsion D dos not includ mold flash, protrusions, or gat burrs. Mold flash, protrusions, or gat burrs shall not xcd 0.15 mm pr nd. Dimnsion E1 dos not includ intrlad flash or protrusion. Intrlad flash or protrusion shall not xcd 0.15 mm pr sid. 3. Th packag top may b smallr than th packag bottom. Dimnsions D and E1 ar dtrmind at th outrmost xtrms of th plastic body xclusiv of mold flash, ti bar burrs, gat burrs, and intrlad flash, but including any mismatch btwn th top and bottom of th plastic body. 4. Ths dimnsions apply to th flat sction of th lad btwn 0.08 mm and 0.15 mm from th lad tip. 5. Dimnsion "b" dos not includ Dambar protrusion. Allowabl Dambar protrusion shall b 0.08 mm total in xcss of th "b" dimnsion at maximum matrial condition. Th Dambar cannot b locatd on th lowr radius of th foot. Minimum spac btwn protrusion and an adjacnt lad shall not b lss than 0.07 mm. D Sid Viw COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A 1.10 A A c D 2.90 BSC 2, 3 E 2.80 BSC 2, 3 E BSC 2, 3 L REF 0.95 BSC BSC b , 5 R 1150 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 5TS1, 5-lad, 1.60 mm Body, Plastic Thin Shrink Small Outlin Packag (SHRINK SOT) 6/25/03 DRAWING NO. REV. PO5TS1 A 23

24 8U2 dbga2 E D Pin 1 Mark this cornr Top Viw - Z d 5 4 D1 E1 Bottom Viw Øb M Z X Y M Z A2 A A1 # # # # Sid Viw COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE D 5.10 D TYP E 3.25 E TYP 0.75 TYP d 0.75 TYP A 0.90 REF A A Øb Nots: 1. Ths drawings ar for gnral information only. No JEDEC Drawing to rfr to for additional information. 2. Dimnsion is masurd at th maximum soldr ball diamtr, paralll to primary datum Z. 02/04/02 R 1150 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 8U2, 8-ball 0.75 pitch, Di Ball Grid Array Packag (dbga) AT24C512 (AT19870) DRAWING NO. 8U2 REV. A 24 AT24C01A/02/04/08A/16A

25 AT24C01A/02/04/08A/16A 8U3-1 dbga2 E D 1. b PIN 1 BALL PAD CORNER Top Viw A 2 A 1 A (d1) 1 PIN 1 BALL PAD CORNER Sid Viw d (1) 8 Bottom Viw 8 SOLDER BALLS 1. Dimnsion b is masurd at th maximum soldr ball diamtr. This drawing is for gnral information only COMMON DIMENSIONS (Unit of Masur = mm) SYMBOL MIN NOM MAX NOTE A A A b D 1.50 BSC E 2.00 BSC 0.50 BSC REF d 1.00 BSC d REF R 1150 E. Chynn Mtn. Blvd. Colorado Springs, CO TITLE 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Di Ball Grid Array Packag (dbga2) 6/24/03 DRAWING NO. REV. PO8U3-1 A 25

26 Rvision History Doc. No. Dat Commnts 0180Z1 5/2007 Implmntd rvision history. Changd formatting on pag AT24C01A/02/04/08A/16A

27 Atml Corporation 2325 Orchard Parkway San Jos, CA 95131, USA Tl: 1(408) Fax: 1(408) Rgional Hadquartrs Europ Atml Sarl Rout ds Arsnaux 41 Cas Postal 80 CH-1705 Fribourg Switzrland Tl: (41) Fax: (41) Asia Room 1219 Chinachm Goldn Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tl: (852) Fax: (852) Japan 9F, Tontsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan Tl: (81) Fax: (81) Atml Oprations Mmory 2325 Orchard Parkway San Jos, CA 95131, USA Tl: 1(408) Fax: 1(408) Microcontrollrs 2325 Orchard Parkway San Jos, CA 95131, USA Tl: 1(408) Fax: 1(408) La Chantrri BP Nants Cdx 3, Franc Tl: (33) Fax: (33) ASIC/ASSP/Smart Cards Zon Industrill Rousst Cdx, Franc Tl: (33) Fax: (33) East Chynn Mtn. Blvd. Colorado Springs, CO 80906, USA Tl: 1(719) Fax: 1(719) Scottish Entrpris Tchnology Park Maxwll Building East Kilbrid G75 0QR, Scotland Tl: (44) Fax: (44) RF/Automotiv Thrsinstrass 2 Postfach Hilbronn, Grmany Tl: (49) Fax: (49) East Chynn Mtn. Blvd. Colorado Springs, CO 80906, USA Tl: 1(719) Fax: 1(719) Biomtrics/Imaging/Hi-Rl MPU/ High Spd Convrtrs/RF Datacom Avnu d Rochplin BP Saint-Egrv Cdx, Franc Tl: (33) Fax: (33) Litratur Rqusts Disclaimr: Th information in this documnt is providd in connction with Atml products. No licns, xprss or implid, by stoppl or othrwis, to any intllctual proprty right is grantd by this documnt or in connction with th sal of Atml products. EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atml maks no rprsntations or warrantis with rspct to th accuracy or compltnss of th contnts of this documnt and rsrvs th right to mak changs to spcifications and product dscriptions at any tim without notic. Atml dos not mak any commitmnt to updat th information containd hrin. Unlss spcifically providd othrwis, Atml products ar not suitabl for, and shall not b usd in, automotiv applications. Atml s products ar not intndd, authorizd, or warrantd for us as componnts in applications intndd to support or sustain lif Atml Corporation. All rights rsrvd. Atml, logo and combinations throf and othrs, ar rgistrd tradmarks or tradmarks of Atml Corporation or its subsidiaris. Othr trms and product nams may b tradmarks of othrs. Printd on rcycld papr.