CAT24C kb I 2 C CMOS Serial EEPROM

Transcription

1 k I 2 MO rial PROM scription h is a 128 k rial MO PROM, intrnally organizd as 16,384 words of 8 its ach. It faturs a 64 yt pag writ uffr and supports oth th tandard (100 khz), Fast (400 khz) and Fast Plus (1 MHz) I 2 protocol. Writ oprations can inhiitd y taking th WP pin High (this protcts th ntir mmory). On hip (rror orrction od) maks th dvic suital for high rliaility applications.* Faturs upports tandard, Fast and Fast Plus I 2 Protocol 1.8 V to 5.5 V upply Voltag Rang 64 Byt Pag Writ Buffr Hardwar Writ Protction for ntir Mmory chmitt riggrs and Nois upprssion Filtrs on I 2 Bus Inputs (L and ) Low Powr MO chnology 1,000,000 Program/ras ycls 100 Yar ata Rtntion Industrial and xtndd mpratur Rang 8 lad PIP, OI, OP, MOP and UFN Packags his vic is P Fr, Halogn Fr/BFR Fr and RoH ompliant** L 2, 1, 0 WP V V Figur 1. Functional ymol *vailal for Nw Product (Rv. ) ** For additional information on our P Fr stratgy and soldring dtails, plas download th ON miconductor oldring and Mounting chniqus Rfrnc Manual, OLRRM/. PIP 8 L UFFIX 646 OI 8 W UFFIX 751B PIN ONFIGURION V V WP L PIP (L), OI (W), OP (Y), MOP (Z), UFN (HU3***), UFN (HU4) Pin Nam 0, 1, 2 L WP V V UFN 8 HU4 UFFIX 517Z MOP 8 Z UFFIX 846 vic ddrss Inputs rial ata Input/Output rial lock Input Writ Protct Input Powr upply Ground Function OP 8 Y UFFIX 948L UFN 8*** HU3 UFFIX 517X For th location of Pin 1, plas consult th corrsponding packag drawing. *** Not rcommndd for nw dsign. PIN FUNION h xposd pad for th FN/UFN packags can lft floating or connctd to Ground. ORRING INFORMION dtaild ordring and shipping information in th packag dimnsions sction on pag 16 of this data sht. miconductor omponnts Industris, LL, 2013 ugust, 2013 Rv Pulication Ordr Numr: 24128/

2 24128 al 1. BOLU MXIMUM RING Paramtr Rating Units torag mpratur 65 to +150 Voltag on ny Pin with Rspct to Ground (Not 1) 0.5 to +6.5 V trsss xcding Maximum Ratings may damag th dvic. Maximum Ratings ar strss ratings only. Functional opration aov th Rcommndd Oprating onditions is not implid. xtndd xposur to strsss aov th Rcommndd Oprating onditions may affct dvic rliaility. 1. h input voltag on any pin should not lowr than 0.5 V or highr than V V. uring transitions, th voltag on any pin may undrshoot to no lss than 1.5 V or ovrshoot to no mor than V V, for priods of lss than 20 ns. al 2. RLIBILIY HRRII (Not 2) ymol Paramtr Min Units N N (Nots 3, 4) nduranc 1,000,000 Program / ras ycls R ata Rtntion 100 Yars 2. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 3. Pag Mod, V = 5 V, h nw product rvision () uss (rror orrction od) logic with 6 its to corrct on it rror in 4 data yts. hrfor, whn a singl yt has to writtn, 4 yts (including th its) ar r programmd. It is rcommndd to writ y multipl of 4 yts in ordr to nfit from th maximum numr of writ cycls. al 3... OPRING HRRII Matur Product (Rv B) (V = 1.8 V to 5.5 V, = 40 to +125, unlss othrwis spcifid.) ymol Paramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400 khz 1 m I W Writ urrnt Writ, f L = 400 khz 3 m I B tandy urrnt ll I/O Pins at GN or V = 40 to = 40 to I L I/O Pin Lakag Pin at GN or V = 40 to = 40 to V IL Input Low Voltag 0.5 V x 0.3 V V IH Input High Voltag V x 0.7 V V V OL1 Output Low Voltag V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltag V < 2.5 V, I OL = 1.0 m 0.2 V al 4. PIN IMPN HRRII Matur Product (Rv B) (V = 1.8 V to 5.5 V, = 40 to +125, unlss othrwis spcifid.) ymol Paramtr onditions Max Units IN (Not 5) I/O Pin apacitanc V IN = 0 V 8 pf IN (Not 5) Input apacitanc (othr pins) V IN = 0 V 6 pf I WP (Not 6) WP Input urrnt V IN < V IH 200 V IN > V IH 1 5. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 6. Whn not drivn, th WP pin is pulld down to GN intrnally. For improvd nois immunity, th intrnal pull down is rlativly strong; thrfor th xtrnal drivr must al to supply th pull down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input uffr (~ 0.5 x V ), th strong pull down rvrts to a wak currnt sourc. 2

3 24128 al 5... OPRING HRRII Nw Product (Rv ) (Not 7) (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125, unlss othrwis spcifid.) ymol Paramtr st onditions Min Max Units I R Rad urrnt Rad, f L = 400 khz/1 MHz 1 m I W Writ urrnt 3 m I B tandy urrnt ll I/O Pins at GN or V = 40 to = 40 to I L I/O Pin Lakag Pin at GN or V = 40 to = 40 to V IL1 Input Low Voltag 2.5 V V 5.5 V V V V IL2 Input Low Voltag 1.8 V V < 2.5 V V V V IH1 Input High Voltag 2.5 V V 5.5 V 0.7 V V V V IH2 Input High Voltag 1.8 V V < 2.5 V 0.75 V V V V OL1 Output Low Voltag V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltag V < 2.5 V, I OL = 1.0 m 0.2 V al 6. PIN IMPN HRRII Nw Product (Rv ) (Not 7) (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125, unlss othrwis spcifid.) ymol Paramtr onditions Max Units IN (Not 8) I/O Pin apacitanc V IN = 0 V 8 pf IN (Not 8) Input apacitanc (othr pins) V IN = 0 V 6 pf I WP, I (Not 9) WP Input urrnt, ddrss Input V IN < V IH, V = 5.5 V 75 urrnt ( 0, 1, 2 ) V IN < V IH, V = 3.3 V 50 V IN < V IH, V = 1.8 V 25 V IN > V IH 2 7. h product Rv is idntifid y lttr or ddicatd marking cod on top of th packag. 8. hs paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat Q100 and J tst mthods. 9. Whn not drivn, th WP, 0, 1, 2 pins ar pulld down to GN intrnally. For improvd nois immunity, th intrnal pull down is rlativly strong; thrfor th xtrnal drivr must al to supply th pull down currnt whn attmpting to driv th input HIGH. o consrv powr, as th input lvl xcds th trip point of th MO input uffr (~ 0.5 x V ), th strong pull down rvrts to a wak currnt sourc. 3

4 24128 al 7... HRRII (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125 ) (Not 10) ymol Paramtr tandard V = 1.8 V 5.5 V Fast V = 1.8 V 5.5 V Fast Plus (Not 13) V = 2.5 V 5.5 V = 40 to +85 Min Max Min Max Min Max F L lock Frquncy ,000 khz t H: R ondition Hold im s t LOW Low Priod of L lock s t HIGH High Priod of L lock s t U: R ondition tup im s t H: ata In Hold im s t U: ata In tup im ns t R (Not 11) and L Ris im 1, ns t F (Not 11) and L Fall im ns t U:O OP ondition tup im s t BUF Bus Fr im Btwn OP and R Units s t L Low to ata Out Valid s t H ata Out Hold im ns i (Not 11) Nois Puls Filtrd at L and Inputs ns t U:WP WP tup im s t H:WP WP Hold im s t WR Writ ycl im ms t PU (Nots 11, 12) Powr-up to Rady Mod ms 10. st conditions according to.. st onditions tal. 11. std initially and aftr a dsign or procss chang that affcts this paramtr. 12.t PU is th dlay twn th tim V is stal and th dvic is rady to accpt commands. 13.Fast Plus (1 MHz) spd class availal for nw product rvision. h di rvision is idntifid y lttr or a ddicatd marking cod on top of th packag. al 8... ONIION Input Lvls 0.2 x V to 0.8 x V Input Ris and Fall ims 50 ns Input Rfrnc Lvls 0.3 x V, 0.7 x V Output Rfrnc Lvls 0.5 x V Output Load urrnt ourc: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 4

5 24128 Powr On Rst (POR) h incorporats Powr On Rst (POR) circuitry which protcts th dvic against powring up in th wrong stat. h will powr up into tandy mod aftr V xcds th POR triggr lvl and will powr down into Rst mod whn V drops low th POR triggr lvl. his i dirctional POR fatur protcts th dvic against rown out failur following a tmporary loss of powr. Pin scription L: h rial lock input pin accpts th rial lock gnratd y th Mastr. : h rial ata I/O pin rcivs input data and transmits data stord in PROM. In transmit mod, this pin is opn drain. ata is acquird on th positiv dg, and is dlivrd on th ngativ dg of L. 0, 1 and 2 : h ddrss pins accpt th dvic addrss. Whn not drivn, ths pins ar pulld LOW intrnally. WP: h Writ Protct input pin inhiits all writ oprations, whn pulld HIGH. Whn not drivn, this pin is pulld LOW intrnally. Functional scription h supports th Intr Intgratd ircuit (I 2 ) Bus data transmission protocol, which dfins a dvic that snds data to th us as a transmittr and a dvic rciving data as a rcivr. ata flow is controlld y a Mastr dvic, which gnrats th srial clock and all R and OP conditions. h acts as a lav dvic. Mastr and lav altrnat as ithr transmittr or rcivr. Up to 8 dvics may connctd to th us as dtrmind y th dvic addrss inputs 0, 1, and 2. I 2 Bus Protocol h I 2 us consists of two wirs, L and. h two wirs ar connctd to th V supply via pull up rsistors. Mastr and lav dvics connct to th 2 wir us via thir rspctiv L and pins. h transmitting dvic pulls down th lin to transmit a 0 and rlass it to transmit a 1. ata transfr may initiatd only whn th us is not usy (s.. haractristics). uring data transfr, th lin must rmain stal whil th L lin is HIGH. n transition whil L is HIGH will intrprtd as a R or OP condition (Figur 2). h R condition prcds all commands. It consists of a HIGH to LOW transition on whil L is HIGH. h R acts as a wak up call to all rcivrs. snt a R, a lav will not rspond to commands. h OP condition complts all commands. It consists of a LOW to HIGH transition on whil L is HIGH. vic ddrssing h Mastr initiats data transfr y crating a R condition on th us. h Mastr thn roadcasts an 8 it srial lav addrss. h first 4 its of th lav addrss ar st to 1010, for normal Rad/Writ oprations (Figur 3). h nxt 3 its, 2, 1 and 0, slct on of 8 possil lav dvics and must match th stat of th xtrnal addrss pins. h last it, R/W, spcifis whthr a Rad (1) or Writ (0) opration is to prformd. cknowldg ftr procssing th lav addrss, th lav rsponds with an acknowldg () y pulling down th lin during th 9 th clock cycl (Figur 4). h lav will also acknowldg all addrss yts and vry data yt prsntd in Writ mod. In Rad mod th lav shifts out a data yt, and thn rlass th lin during th 9 th clock cycl. s long as th Mastr acknowldgs th data, th lav will continu transmitting. h Mastr trminats th sssion y not acknowldging th last data yt (No) and y issuing a OP condition. Bus timing is illustratd in Figur 5. 5

6 24128 L R ONIION Figur 2. R/OP onditions OP ONIION VI R R/W Figur 3. lav ddrss Bits BU RL LY (RNMIR) BU RL LY (RIVR) L FROM MR OUPU FROM RNMIR OUPU FROM RIVR R LY ( t ) Figur 4. cknowldg iming UP ( t U: ) t F t HIGH t R tlow tlow L t U: t H: t H: t U: t U:O IN t t H t BUF OU Figur 5. Bus iming 6

7 24128 Writ Oprations Byt Writ Upon rciving a lav addrss with th R/W it st to 0, th will intrprt th nxt two yts as addrss yts. hs yts ar usd to initializ th intrnal addrss countr; th 2 most significant its ar don t car, th nxt 8 point to on of 256 availal pags and th last 6 point to a location within a 64 yt pag. yt following th addrss yts will intrprtd as data. h data will loadd into th Pag Writ Buffr and will vntually writtn to mmory at th addrss spcifid y th 14 activ addrss its providd arlir. h will acknowldg th lav addrss, addrss yts and data yt. h Mastr thn starts th intrnal Writ cycl y issuing a OP condition (Figur 6). uring th intrnal Writ cycl (t WR ), th output will tri statd and additional Rad or Writ rqusts will ignord (Figur 7). Pag Writ By continuing to load data into th Pag Writ Buffr aftr th 1 st data yt and for issuing th OP condition, up to 64 yts can writtn simultanously during on intrnal Writ cycl (Figur 8). If mor data yts ar loadd than locations availal to th nd of pag, thn loading will continu from th ginning of pag, i.. th pag addrss is latchd and th addrss count automatically incrmnts to and thn wraps around at th pag oundary. Prviously loadd data can thus ovrwrittn y nw data. What is vntually writtn to mmory rflcts th latst Pag Writ Buffr contnts. Only data loadd within th most rcnt Pag Writ squnc will writtn to mmory. cknowldg Polling h rady/usy status of th can ascrtaind y snding Rad or Writ rqusts immdiatly following th OP condition that initiatd th intrnal Writ cycl. s long as intrnal Writ is in progrss, th will not acknowldg th lav addrss. Hardwar Writ Protction With th WP pin hld HIGH, th ntir mmory is protctd against Writ oprations. If th WP pin is lft floating or is groundd, it has no impact on th opration of th h stat of th WP pin is strod on th last falling dg of L immdiatly prcding th first data yt (Figur 9). If th WP pin is HIGH during th stro intrval, th will not acknowldg th data yt and th Writ rqust will rjctd. livry tat h is shippd rasd, i.., all yts ar FFh. BU IVIY: MR R LV R R R a 13 a 8 a 7 a 0 O P * * P LV * = on t ar Bit Figur 6. Byt Writ qunc L 8th Bit Byt n t WR OP ONIION Figur 7. Writ ycl iming R ONIION R 7

8 24128 BU IVIY: MR R LV R R R a 13 a 8 a 7 a 0 n n+1 n+p O P * * P LV * = on t ar Bit P 63 Figur 8. Pag Writ qunc R L a 7 a 0 d 7 d 0 t U:WP WP t H:WP Figur 9. WP iming Rad Oprations Immdiat Rad Upon rciving a lav addrss with th R/W it st to 1, th will intrprt this as a rqust for data rsiding at th currnt yt addrss in mmory. h will acknowldg th lav addrss, will immdiatly shift out th data rsiding at th currnt addrss, and will thn wait for th Mastr to rspond. If th Mastr dos not acknowldg th data (No) and thn follows up with a OP condition (Figur 10), th rturns to tandy mod. lctiv Rad o rad data rsiding at a spcific location, th intrnal addrss countr must first initializd as dscrid undr Byt Writ. If rathr than following up th two addrss yts with data, th Mastr instad follows up with an Immdiat Rad squnc, thn th will us th 14 activ addrss its to initializ th intrnal addrss countr and will shift out data rsiding at th corrsponding location. If th Mastr dos not acknowldg th data (No) and thn follows up with a OP condition (Figur 11), th rturns to tandy mod. quntial Rad If during a Rad sssion th Mastr acknowldgs th 1 st data yt, thn th will continu transmitting data rsiding at susqunt locations until th Mastr rsponds with a No, followd y a OP (Figur 12). In contrast to Pag Writ, during quntial Rad th addrss count will automatically incrmnt to and thn wrap around at nd of mmory (rathr than nd of pag). 8

9 24128 BU IVIY: MR R LV R N O O P P LV L 8 9 8th Bit OU NO OP Figur 10. Immdiat Rad qunc and iming BU IVIY: MR R LV R R R a 13 a 8 a 7 a 0 R LV R N O OP * * P LV * = on t ar Bit Figur 11. lctiv Rad qunc BU IVIY: MR LV R N O O P P LV n n+1 n+2 n+x Figur 12. quntial Rad qunc 9

10 24128 PG IMNION PIP 8, 300 mils IU YMBOL MIN NOM MX PIN # 1 INIFIION c B B L OP VIW 2 1 L 2 c B I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. (2) omplis with J M

11 24128 PG IMNION OI 8, 150 mils 751B 01 IU O YMBOL MIN NOM MX c B h PIN # 1 INIFIION L θ 0º 8º OP VIW h 1 θ c L I VIW N VIW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J M

12 24128 PG IMNION OP8, 4.4x3 948L 01 IU O YMBOL MIN NOM MX c B L 1.00 RF L1 θ º 8º OP VIW 2 1 c I VIW 1 L1 N VIW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J MO

13 24128 PG IMNION UFN8, 2x3 517X 01 IU O IL P IZ 1.3 x PIN #1 INIFIION PIN #1 INX R 1 2 OP VIW I VIW BOOM VIW YMBOL MIN NOM MX RF IL L YP 0.10 RF L Nots: (1) ll dimnsions ar in millimtrs. (2) omplis with J MO FRON VIW 13

14 24128 PG IMNION MOP 8, 3x IU O YMBOL MIN NOM MX c B L L RF L2 θ 0.25 B 0º 6º OP VIW 2 IL 1 c I VIW N VIW L2 Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) omplis with J MO-187. IL L1 L 14

15 24128 PG IMNION UFN8, 2x3 XN P 517Z 01 IU O L P IZ 1.8 x PIN #1 INIFIION PIN #1 INX R 1 2 OP VIW I VIW BOOM VIW YMBOL MIN NOM MX RF RF IL FRON VIW RF L Nots: (1) ll dimnsions ar in millimtrs. (2) Rfr J MO-236/MO IL RF oppr xposd 15

16 24128 ORRING INFORMION (Nots 14 thru 19) vic Ordr Numr pcific vic Marking* 24128LI G PIP 8 I = Industrial ( 40 to +85 ) Packag yp mpratur Rang Lad Finish hipping NiPdu u, 50 Units / u 24128L G PIP 8 = xtndd ( 40 to +125 ) NiPdu u, 50 Units / u 24128WI G OI 8, J I = Industrial ( 40 to +85 ) NiPdu ap & Rl, 3,000 Units / Rl 24128W G OI 8, J = xtndd ( 40 to +125 ) NiPdu ap & Rl, 3,000 Units / Rl 24128YI G3 28 OP 8 I = Industrial ( 40 to +85 ) 24128Y G3 28 OP 8 = xtndd ( 40 to +125 ) NiPdu NiPdu ap & Rl, 3,000 Units / Rl ap & Rl, 3,000 Units / Rl 24128HU4IG3 (Not 19) 7U UFN 8 I = Industrial ( 40 to +85 ) NiPdu ap & Rl, 3,000 Units / Rl 24128HU4G3 (Not 19) 7U UFN 8 = xtndd ( 40 to +125 ) NiPdu ap & Rl, 3,000 Units / Rl 24128HU3IG3** BB UFN 8 I = Industrial ( 40 to +85 ) 24128ZI G3 7 MOP 8 I = Industrial ( 40 to +85 ) NiPdu NiPdu ap & Rl, 3,000 Units / Rl ap & Rl, 3,000 Units / Rl 24128Z G3 7 MOP 8 = xtndd ( 40 to +125 ) NiPdu ap & Rl, 3,000 Units / Rl 14. ll packags ar RoH compliant (Lad fr, Halogn fr). 15. h standard lad finish is NiPdu. 16. For additional packag and tmpratur options, plas contact your narst ON miconductor als offic. 17. For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our ap and Rl Packaging pcifications Brochur, BR8011/. 18. For dtaild information and a rakdown of dvic nomnclatur and numring systms, plas s th ON miconductor vic Nomnclatur documnt, N310/, availal at hr ar NO hyphns in th ordral part numrs. *Marking for Nw Product (Rv ). ** Not rcommndd for nw dsigns. ON miconductor is licnsd y Philips orporation to carry th I 2 Bus Protocol. ON miconductor and ar rgistrd tradmarks of miconductor omponnts Industris, LL (ILL). ILL owns th rights to a numr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of ILL s product/patnt covrag may accssd at Marking.pdf. ILL rsrvs th right to mak changs without furthr notic to any products hrin. ILL maks no warranty, rprsntation or guarant rgarding th suitaility of its products for any particular purpos, nor dos ILL assum any liaility arising out of th application or us of any product or circuit, and spcifically disclaims any and all liaility, including without limitation spcial, consquntial or incidntal damags. ypical paramtrs which may providd in ILL data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including ypicals must validatd for ach customr application y customr s tchnical xprts. ILL dos not convy any licns undr its patnt rights nor th rights of othrs. ILL products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th ody, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th ILL product could crat a situation whr prsonal injury or dath may occur. hould Buyr purchas or us ILL products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold ILL and its officrs, mploys, susidiaris, affiliats, and distriutors harmlss against all claims, costs, damags, and xpnss, and rasonal attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that ILL was nglignt rgarding th dsign or manufactur of th part. ILL is an qual Opportunity/ffirmativ ction mployr. his litratur is sujct to all applical copyright laws and is not for rsal in any mannr. PUBLIION ORRING INFORMION LIRUR FULFILLMN: Litratur istriution ntr for ON miconductor P.O. Box 5163, nvr, olorado U Phon: or oll Fr U/anada Fax: or oll Fr U/anada mail: [email protected] N. mrican chnical upport: oll Fr U/anada urop, Middl ast and frica chnical upport: Phon: Japan ustomr Focus ntr Phon: ON miconductor Wsit: Ordr Litratur: For additional information, plas contact your local als Rprsntativ 24128/