Chapter 10. Boundary Scan and Core-Based Testing

Chapter 10 Boundary Scan and Core-Based Testing VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 1 1

Outline Introduction Digital Boundary Scan (1149.1) Boundary Scan for Advanced Networks (1149.6) Embedded Core Test Standard (1500) Comparison between 1149.1 and 1500 VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 2 2

Boundary Scan Original objective: board-level digital testing Now also apply to: MCM and FPGA Analog circuits and high-speed networks Verification, debugging, clock control, power management, chip reconfiguration, etc. History: Mid-1980: JETAG 1988: JTAG 1990: First boundary scan standard 1149.1 VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 3 3

Boundary Scan Family No. 1149.1 1149.2 1149.3 1149.4 1149.5 1149.6 Main target Digital chips and interconnects among chips Extended digital serial interface Direct access testability interface Mixed-signal test bus Standard module test and maintenance (MTM) bus High-speed network interface Status Std. 1149.1-2001 Discontinue Discontinue Std. 1149.4-1999 Std. 1149.5-1995 (not endorsed by IEEE since 2003) Std. 1149.6-2003 VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 4 4

Core-Based SOC Design ADC RAM RAM ROM GLUE LOGIC PLL DAC BUS & INTERCONNECT ASIC 1 IP 1 DSP CPU ASIC 2 IP 2 RAM ROM ASIC DSP ALU ASIC VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 5 5

Digital Boundary Scan 1149.1 Basic concepts Overall test architecture & operations Hardware components Instruction register & instruction set Boundary scan description language On-chip test support Board/system-level control architectures VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 6 6

Basic Idea of Boundary Scan Boundary-scan cell Internal Logic VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 7 7

A Board Containing 4 IC s s with Boundary Scan Boundary-scan cell Boundary-scan chain Serial Data in Internal Logic Internal Logic Serial Data out Internal Logic Internal Logic System interconnect 8 VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 8

1149.1 Boundary-Scan Architecture Boundary-Scan Register (consists of boundary Scan cells) Test Data In (TDI) 1 1 Internal Logic Internal Registers Bypass Register Miscellaneous Register Instruction Register Test Data Out (TDO) Test Mode Select (TMS) Test Clock (TCK) TAP Controller Test Reset (TRST*) (optional) VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 9 1 9

Hardware Components of 1149.1 A test access port (TAP) consisting of : 4 mandatory pins: Test data in (TDI), Test data out (TDO), Test mode select (TMS), Test clock (TCK), and 1 optional pin: Test reset (TRST) A test access port controller (TAPC) An instruction register (IR) Several test data registers A boundary scan register (BSR) consisting of boundary scan cells (BSCs) A bypass register (BR) Some optional registers (Device-ID register, designspecified registers such as scan registers, LFSRs for BIST, etc.) VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 10 10

Basic Operations 1. Instruction sent (serially) through TDI into instruction register. 2. Selected test circuitry configured to respond to the instruction. 3. Test pattern shifted into selected data register and applied to logic to be tested 4. Test response captured into some data register 5. Captured response shifted out; new test pattern shifted in simultaneously 6. Steps 3-5 repeated until all test patterns are applied. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 11 11

Boundary-Scan Circuitry in A Chip Design-Spec. Reg. Data Register TDO TDI TRST* TMS TCK T A P T A P C Device-ID Reg. Boundary Scan Reg. Bypass Reg. (1-bit) 3 ClockDR, ShiftDR, UpdateDR Reset* ClockIR, ShiftIR, UpdateIR 3 Instruction Register M U X IR decode 0 1 Select M U X 1D TCK EN Enable VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 12 12

Data registers Boundary scan register: consists of boundary scan cells Bypass register: a one-bit register used to pass test signal from a chip when it is not involved in current test operation Device-ID register: for the loading of product information (manufacturer, part number, version number, etc.) Other user-specified data registers (scan chains, LFSR for BIST, etc.) VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 13 13

A Typical Boundary-Scan Cell (BSC) Operation modes Normal: IN OUT (Mode = 0) Shift: TDI... IN OUT... TDO (ShiftDR = 1, ClockDR) Capture: IN R1, OUT driven by IN or R2 (ShiftDR = 0, ClcokDR) Update: R1 OUT (Mode_Control = 1, UpdateDR) VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 14 14

TAP Controller A finite state machine with 16 states Input: TCK, TMS Output: 9 or 10 signals included ClockDR, UpdateDR, ShiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK and TRST* (optional). VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 15 15

State Diagram of TAP Controller VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 16 16

Main functions of TAP controller Providing control signals to Reset BS circuitry Load instructions into instruction register Perform test capture operation Perform test update operation Shift test data in and out VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 17 17

States of TAP Controller Test-Logic-Reset: normal mode Run-Test/Idle: wait for internal test such as BIST Select-DR-Scan: initiate a data-scan sequence Capture-DR: load test data in parallel Shift-DR: load test data in series Exit1-DR: finish phase-1 shifting of data Pause-DR: temporarily hold the scan operation (e.g., allow the bus master to reload data) Exit2-DR: finish phase-2 shifting of data Update-DR: parallel load from associated shift registers Note: Controls for IR are similar to those for DR. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 18 18

Instruction Set BYPASS Bypass data through a chip SAMPLE Sample (capture) test data into BSR PRELOAD Shift-in test data and update BSR EXTEST Test interconnection between chips of board Optional INTEST, RUNBIST, CLAMP, IDCODE, USERCODE, HIGH-Z, etc. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 19 19

Execution of BYPASS Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 20 20

Execution of SAMPLE Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 21 21

Execution of PRELOAD Instruction Input PRELOAD R1 R2 M U X Internal Logic R1 R2 M U X Output TDI TDO VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 22 22

Execution of EXTEST Instruction (1/3) Shift-DR (Chip1) Internal Logic Internal Logic TDI Registers TDO TDI Registers TDO TAP controller TAP controller VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 23 23

Execution of EXTEST Instruction (2/3) Update-DR (Chip1) Capture-DR (Chip2) VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 24 24

Execution of EXTEST Instruction (3/3) Shift-DR (Chip2) Internal Logic Internal Logic TDI Registers TDO TDI Registers TDO TAP controller TAP controller VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 25 25

Execution of INTEST Instruction (1/4) Shift-DR VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 26 26

Execution of INTEST Instruction (2/4) Update-DR VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 27 27

Execution of INTEST Instruction (3/4) Capture-DR Internal Logic TDI Registers TAP controller TDO VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 28 28

Execution of INTEST Instruction (4/4) Shift-DR Internal Logic TDI Registers TAP controller TDO VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 29 29

Boundary Scan Description Language (BSDL) Now a part of IEEE 1149.1-2001 Purposes: Provide standard description language for BS devices. Simplify design work for BS automated synthesis is possible. Promote consistency throughout ASIC designers, device manufacturers, foundries, test developers and ATE manufacturers. Make it easy to incorporation BS into software tools for test generation, analysis and failure diagnosis. Reduce possibility of human error when employing boundary scan in a design. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 30 30

Features of BSDL Describes the testability features of BS devices that are compatible with 1149.1. S subset of VHDL. System-logic and the 1149.1 elements that are absolutely mandatory need not be specified. Examples: BYPASS register, TAP controller, etc. Commercial tools to synthesize BSDL exist. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 31 31

Scan and BIST Support with Boundary Scan VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 32 32

Bus Master for Chips with Boundary Scan (1/5) Ring architecture with shared TMS Application chips TDI TCK TMS TDO #1 Bus master TDI TDO TMS TCK TDI TCK TMS TDO #2 VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 33 TDI TCK TMS TDO #N 33

Bus Master for Chips with Boundary Scan (2/5) Ring architecture with separate TMS Application chips Bus master TDI TDO TMS1 TMS2 TMSN TCK TDI TCK TMS TDO TDI TCK TMS TDO #1 #2 TDI TCK TMS TDO VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 34 #N 34

Bus Master for Chips with Boundary Scan (3/5) Star architecture VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 35 35

Bus Master for Chips with Boundary Scan (4/5) Multi-drop architecture Multi-Drop Device Multi-Drop Device Multi-Drop Device Bus master TDI TMS TCK TDO Test Bus VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 36 36

Bus Master for Chips with Boundary Scan (5/5) Hierarchical architecture VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 37 37

Boundary scan for advanced networks 1149.6 Rationale Analog test receiver Digital driver logic Digital receiver logic Test access port for 1149.6 VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 38 38

Rationale Advanced signaling techniques are required for multiple-mega-per-second I/O. Differential or AC-coupling networks Coupling capacitor in AC-coupled networks blocks DC signals. DC-level applied during EXTEST may decay to undefined logic level. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 39 39

Capturing AC-Coupled Coupled Signal with 1149.1 C U C U TX Update-DR V T RX TX V H V L RX V H V L Capture-DR VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 40 40

1149.1 Configuration for Differential Signaling C U C U TX RX VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 41 41

Analog Test Receiver Response to AC and DC-Coupled Coupled Signals VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 42 42

Digital Driver Logic Mission 0 Shift in ShiftDR 1 C U ClockDR Shift out UpdateDR Train/Pulse 0 1 AC Mode 1149.1 Bypass 1149.1 Extest Extest_Pulse 0 1 Mode Mode Data AC Test Signal Insertion, per driver AC Mode Train/Pulse 0 X X 1 0 X 1 1 0 RTI State TCK D Q AC Test Signal (distributed to all AC drivers) Extest_Train 1 1 1 AC Test Signal Generator (near TAP Controller) VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 43 43

Digital Receiver Logic Optional, Required for Observe-and-Control Capabilty on Single-Ended Inputs Only 0 Boundary Register Cell Shift In 1 0 ShiftDR Capture FF Shift Out Update FF 1 EXTEST: TCK TAP State Init_Memory Clock_DR Capture-DR Shift_DR Test Receiver Pad EXTEST_PULSE or EXTEST_TRAIN Selected R F AC DC C F V T V Hyst V Hyst ClockDR UpdateDR D Set Hyst Mem Clear Init_Memory (common to all test receivers) EXTEST_PULSE, EXTEST_TRAIN: Latch Q Init_Memory NOTE: The generated clock (Init_Memory) shown is suitable for rising edge-sensitive behavior only. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 44 TCK TAP State TMS May be located near TAP controller Q Q SET Q CLR D LG Exit*-DR Update_DR Capture-DR EXTEST EXTEST_TRAIN EXTEST_PULSE TMS Exit1-DR Exit2-DR TCK 44

Example of Modification on 1149.1 TAP Driver Behavior During EXTEST_PULSE Pulse Width TCK (TAP State) Test-Logic Reset Update-xR Run-Test/Idle Select-DR Capture-DR AC Test Signal Update Point Capture Point AC Pin Driver Data Inverted Data Data VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 45 45

Embedded Core Test Standard - 1500 SOC test problems Overall architecture Wrapper components and functions Instruction set Core test language Core test supporting and system test configurations Hierarchical test control and plug & play VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 46 46

SOC Test Problems/Requirements (1/2) Mixing technologies: logic, processor, memory, analog Need various DFT/BIST/other techniques Deeply embedded cores Need Test Access Mechanism Hierarchical core reuse Need hierarchical test management Different core providers and SOC test developers Need standard for test integration IP protection/test reuse Need core test standard/documentation VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 47 47

SOC Test Problems/Requirements (2/2) Higher-performance core pins than SOC pins Need on-chip, at-speed testing External ATE inefficiency Need on-chip ATE Long test application time Need parallel testing or test scheduling Test power must be considered Need lower power design or test scheduling Testable design automation Need new testable design tools and flow VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 48 48

A System Overview of IEEE 1500 Standard VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 49 49

Test Interface of A Core Wrapper Wrapper Parallel Input WPI Wrapper Parallel Control WPC Optional W rapper Parallel Port (W PP) Wrapper Parallel Output WPO Core WSI Wrapper Serial Input Required W rapper Serial Port (WSP) Wrapper WSC Wrapper Serial Control WSO Wrapper Serial Output VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 50 50

Serial Test Circuitry of 1500 for a Core VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 51 51

Wrapper Components Wrapper series port (WSP) Wrapper series input (WSI), Wrapper series output (WSO), Wrapper series control (WSC) Wrapper parallel port (WPP) (optional) Wrapper parallel input (WPI), Wrapper parallel output (WPO), wrapper parallel control (WPC) Wrapper instruction register (WIR) Wrapper bypass regiester (WBY) Wrapper data register (WBR) Consists of wrapper boundary cells (WBC s) Core data register (CDR) (optional) VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 52 52

Wrapper Series Control (WSC) signals WRCK: wrapper clock terminal AUXCKn: Optional auxiliary clocks, where n is the number of the clocks. WRSTN: wrapper reset SelectWIR: determine whether WIR is selected CaptureWR: enable Capture operation ShiftWR: enable Shift operation UpdateWR: enable Update operation TransferDR: enable Transfer operation VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 53 53

Wrapper Instruction Register VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 54 54

Wrapper Boundary Register (WBR) Consists of Wrapper boundary cells (WBC s) WBC Terminals: Cell functional input (CFI), cell functional output (CFO), cell test input (CTI), cell test output (CTO) Functional modes: Normal, inward facing, outward facing, nonhazardous (safe). Operation events: Shift, capture, update, transfer, apply. VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 55 55

Events of WBR (WBC) Shift: data advance one-bit forward on WBR s shift path Capture: data on CFI or CFO are captured and stored in WBC Update: data stored in WBC s shift path storage are loaded into an off-shift-path storage of the WBC Transfer: move data to the storage closest to CTI or one bit closer to CTO Apply: a derivative event inferred from other events to apply data to functional inputs of cores or functional outputs of WBR VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 56 56

Four Symbols Used in Bubble Diagrams for WBC s Storage element Data path Decision point Data paths from a source VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 57 57

Some Typical WBC s Represented by Bubble Diagrams VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 58 58

Example 10.1 - WIR Interface of WBY, WBR WDR(s) ) and CDR(s) SelectWIR {SelectWIR, WRCK, WRSTN, CaptureWR, ShiftWR, UpdateWR} WIR Circuitry Core_Cntrl WDR_Cntrl CDR_Cntrl DR_Select[n:0] WBR_Cntrl WBY_Cntrl WBR CDR k WDR k WIR_WSO DR_Select[n:0] DR_WSO WSO WSI WBY VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 59 59

Example 10.2 - Schematic Diagram of WBC WC_SD2_CIO CTI SHIFT XFER WRCK D1 MODE CFI CAPT CFO D2 CTO IO_FACE WRCK VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 60 60

WS_BYPASS Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 61 61

WS_EXTEST Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 62 62

WP_EXTEXT Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 63 63

WS_SAFE Instruction Disabled Safe States W B R FI FO Core FO FI W B R Safe States WSI Bypass WIR WSO WSC VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 64 64

WS_PRELOAD Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 65 65

WP_PRELOAD Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 66 66

WS_CLAMP Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 67 67

WS_INTEST Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 68 68

WS_INTEST_SCAN Instruction VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 69 69

General Parallel TAM Structure VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 70 70

Multiplexed TAM Architectures VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 71 71

Daisy chained TAM Architecture VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 72 72

Direct Access TAM Architectures VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 73 73

Local Controller TAM Architectures VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 74 74

Core Access Switch (CAS) Architecture VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 75 75

Different Functional Modes of CAS VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 76 76

Various Types of Test Supporting Using CAS Structure VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 77 77

A Hierarchical Test Architecture Supporting Plug & Play Feature VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 78 78

Detailed I/O and CTC of The Hierarchical Test Architecture VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 79 79

A Hierarchical Test Architecture with I/Os Compatible to 1149.1 VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 80 80

Comparison between 1149.1 and 1500 Purpose Parallel Mode Extra Data/Control I/Os FSM Transfer Mode Latency between operations Mandatory Instructions 1149.1 Board-level No Mandatory: TDI, TDO, TMS, TCK Optional: TRST Yes No Yes EXTEST, BYPASS, SAMPLE, PRELOAD 1500 Core-based VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 81 Yes Mandatory: WSI, WSO, 6 WSC Optional: TransferDR, WPP, AUXCKn(s) No Yes No WS_EXTEST, WS_BYPASS, one Wx_INTEST, WS_PRELOAD (cond. required) 81