Boundary Scan. Boundary Scan.1
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1 Boundary Scan! Objectives! History! Family of 49! Architecture! Bus Protocol! Boundary scan cell! TAP controller! Instruction set! Boundary Scan Description Language Boundary Scan.
2 Objectives! Standards for board level testing; can be used to test. chips 2. chip interconnections 3. modules 4. module interconnections 5. subsystems 6. systems 7. ulti-chip odules Boundary Scan.2
3 History! 985: Joint European Test Action Group (JETAG, Philips)! 986 VHSIC Element-Test & aintenance (ET) bus standard (IB et al.) VHSIC Test & aintenance (T) Bus structure (IB et al.)! 988: Joint Test Action Group (JTAG) proposed Boundary Scan Standard! 99 Boundary Scan approved as IEEE Std Boundary Scan Description Language (BSDL) proposed by HP! 993: 49.a-993 approved to replace ! 994: 49.b BSDL approved! 995: 49.5 approved! 999: 49.4 approved Boundary Scan.3
4 Overview of P49 Family Number Title Status 49. Testing of digital chips and interconnections between chips 49.2 Extended Digital Serial Interface 49.3 Direct Access Testability interface Std Std. 49.a-993 Std. 49.b-994 (BSDL) Near completion Discontinue 49.4 ixed-signal Test Bus Std Standard odule Test and Std aintenance (T) Bus Protocal 49 nification Not yet started Boundary Scan.4
5 49.-99, 49.a-993! Testing of chips and interconnections on board! For digital circuits! ost successful among 49 family! Widely used in industry, e.g., in advanced CP, HDTV, satellite system, etc. Boundary Scan.5
6 Basic Chip Architecture for 49. Boundary Scan Cell Boundary Scan Path I/O Pins I/O Pins Sin Sout TRST* iscellaneous Registers Instruction Register Bypass Register TS TAP Controller TCK Boundary Scan.6
7 Boundary Scan Circuitry in a Chip Design-Spec. Reg. Data Registers TRST* TS TCK T A P T A P C 3 3 Device-ID Reg. BS Register Bypass Reg.( bit) ClockDR ShiftDR pdatedr ClockIR ShiftIR pdateir Reset* IR decode Instruction Register Select TCK D C Enable EN Boundary Scan.7
8 Hardware Components of 49.! TAP (Test Access Port) : TS, TCK,,, TRST* (optional)! TAP Controller : A finite state machine with 6 states Input : TCK, TS Output : 9 or signals included ClockDR, pdatedr, ShiftDR, ClockIR, pdateir, ShiftIR, Select, Enable, TCK and the optional TRST*.! IR (Instruction Register)! TDR (Test Data Registers) : andatory: Boundary scan register and Bypass register Optional: Device-ID register, Design-Specific registers, etc. Boundary Scan.8
9 Bus Protocol! Signals : Test Data In : Test Data Out TS: Test ode Selection TCK: Test Clock TRST* (optional): Test Reset! Basic operations Instruction sent (serially) over into instruction register. Selected test circuitry configured to respond to instruction. Test instruction executed. Test results shifted out through ; new test data on may be shifted in at the same time. Boundary Scan.9
10 A Typical Boundary Scan Cell IN SOT OT SIN shiftdrclockdr Operation modes: ID Q Q A ID pdatedr. Normal: ode_control=; IN->OT 2. Scan: ShiftDR=,ClockDR; ->...->SIN->SOT->... Q Q B 3. Capture: ShiftDR=, ClcokDR; IN->, OT driven by IN or 4. pdate: ode_control=, pdatedr; ->OT ode_control Boundary Scan.
11 State Diagram of TAP Controller Test--Reset Run-test/idle Control of data registers Select-DR-Scan Capture-DR Shift-DR Exit-DR Pause-DR Exit2-DR Control of instruction registers Select-IR-Scan Capture-IR Shift-IR Exit-IR Pause-IR Exit2-IR pdate-dr pdate-ir Boundary Scan.
12 States of TAP Controller! Test--Reset: normal mode! Run-Test/Idle: wait for internal test such as BIST! Select-DR-Scan: initiate a data-scan sequence! Capture-DR: load test data in parallel! Shift-DR: load test data in series! Exit-DR: finish phase- shifting of data! Pause-DR: temporarily hold the scan operation (allow the bus master to reload data)! Exit2-DR: finish phase-2 shifting of data! pdate-dr: parallel load from associated shift registers Boundary Scan.2
13 Timing of instruction scan TCK TS Control State Test-- Reset Run-test/ Idle Select-DR- Scan Select-IR- Scan Capture-IR Shift-IR Exit -IR Pause-IR Exit 2 -IR Shift-IR Exit -IR pdate-ir Run-Test/Idle Data input to IR IR shift-register Parallel output of IR IDCODE New instruction Data input to TDR TDR shift-register Parallel output of TDR Old data Register selected enable Instruction register Inactive Active Inactive Active Inactive = Don't care or undefined Boundary Scan.3
14 Timing of data scan TCK TS Control State Run-Test/Idle SelectDR-Scan Capture-DR Shift-DR Exit -DR Pause-DR Exit 2 -DR Shift-DR Exit -DR pdate-dr Run-Test/Idle SelectDR-Scan SelectIR-Scan Test-- Reset Data input to IR IR shift-register Parallel output of IR Instruction IDCODE Data input to TDR TDR shift-register Parallel output of TDR Instruction Register Old data Test data register New data enable Inactive Active Inactive Active Inactive = Don't care or undefined Boundary Scan.4
15 Instruction Set! ETEST: Test interconnection between chips of board! SAPLE/PRELOAD: Sample and shift out data or shift in data only! BYPASS: Bypass data through a chip! Optional : INTEST, RNBIST, CLAP, IDCODE, SERCODE, HIGH-Z, etc. Boundary Scan.5
16 ETEST Chip Chip2. Shift-DR (Chip) Registers TAP Controller Registers TAP Controller 2. pdate-dr (Chip) 3. Capture-DR (Chip2) Registers TAP Controller Registers TAP Controller 4. Shift-DR (Chip2) Registers TAP Controller Registers TAP Controller Boundary Scan.6
17 ETEST. Shift-DR (Chip) Input Output 2. pdate-dr (Chip) Input Output to Chip2 Input from Chip 3. Capture-DR (Chip2) Output 4. Shift-DR Input (Chip2) Output Boundary Scan.7
18 SAPLE/PRELOAD Input SAPLE Output Input PRELOAD Output Sample/Preload is one instruction that allows. Sample and shift (out) or 2. Shift (in) only Boundary Scan.8
19 BYPASS Bypass Register ( bit) TAP Controller Boundary Scan.9
20 INTEST.Shift-DR 2.pdate-DR Registers TAP Controller Registers TAP Controller 3.Capture-DR 4. Shift-DR Registers TAP Controller Registers TAP Controller Boundary Scan.2
21 Boundary Scan.2 INTEST Output Input Input 2. pdate-dr Output Input 3. Capture-DR Output Output Input 4. Shift-DR. Shift-DR
22 Test Bus Configuration Application chips Application chips Bus master TD TS TCK TCK TS TCK TS # #2 Bus master TD TS TS2 TSN TCK TCK TS TCK TS # #2 TCK TS #N TCK TS #N Ring configuration Star configuration Boundary Scan.22
23 A Printed Circuit Board with 49. (Ring configuration, test controller on board) Chip Chip2 Registers Registers TAP Controller TAP Controller TAP Controller Registers ASTER Controller TS TCK Chip3 Boundary Scan.23
24 Boundary Scan Description Language (BSDL)! Now the IEEE 49.b standard! Purposes: To provide a standard description language for boundary scan devices. To simplify the design work for boundary scan---automated synthesis is possible. To promote consistency throughout ASIC designers, device manufacturers, foundries, test developers and ATE manufacturers. For easy incorporation into software tools for test generation, analysis and failure diagnosis. To reduce possibility of human error when employing boundary scan in a design. Boundary Scan.24
25 Features of BSDL! BSDL describes the testability features of boundary scan devices which are compatible with 49..! It's a subset of VHDL.! Elements of a design which are absolutely mandatory for the 49. and system-logic are not included in the language. Examples: BYPASS register, TAP controller, etc.! BSDL may be used in a full or in a partial VHDL environment. Boundary Scan.25
26 Boundary Scan.26 A Complete Example TS CLK C O R E L O G I C TAP Controller D D2 D3 D4 D5 Q5 Q4 Q3 Q2 Q Q6 D6 C O R E L O G I C D D2 D3 D4 D5 Q5 Q4 Q3 Q2 Q Q6 D6 CLK TCK
27 Entity entity demo is generic(physical_pin_ap:string:="ndefined"); port(clk:in,bit;q:out,bit_vector( to 6);D:in,bit_vector( to 6); GND,VCC:linkage,bit;:out,bit;TS,TCK,:in,bit); use STD_49 99.all; attribute PIN_AP of demo:entity is PHYSICAL_PIN_AP; constant DW_PACKAGE:PIN_AP_STRING:="CLK:," & "Q(6,7,8,9,,),D(2,3,4,5,6,7),GND:8,VCC:9," & ":5,TS:4,TCK:3,:2"; attribute TAP_SCAN_IN of :signal is true; attribute TAP_SCAN_ODE of TS:signal is true; attribute TAP_SCAN_OT of :signal is true; attribute TAP_SCAN_CLOCK of TCK:signal is (2e6,BOTH); attribute INSTRCTION_LENGTH of demo:entity is 4; attribute INSTRCTION_OPCODE of demo:entity is "BYPASS (),"& "ETEST()," & "SAPLE(,)," & "INTEST()"; Boundary Scan.27
28 Entity (Cont.) attribute INSTRCTION_CAPTRE of demo:entity is ""; attribute BONDARY_CELLS of demo:entity is "BC_"; attribute BONDARY_LENGTH of demo:entity is 2; attribute BONDARY_REGISTER of demo:entity is -- num cell port function safe [ccell disval rslt] "2 (BC_,CLK,input,)," & " (BC_,D(),input,)," & " (BC_,D(2),input,)," & "9 (BC_,D(3),input,)," & "8 (BC_,D(4),input,)," & "7 (BC_,D(5),input,)," & "6 (BC_,D(6),input,)," & "5 (BC_,Q(),output3,,,,Z)," & "4 (BC_,Q(2),output3,,,,Z)," & "3 (BC_,Q(3),output3,,,,Z)," & "2 (BC_,Q(4),output3,,5,,Z)," & " (BC_,Q(5),output3,,5,,Z)," & " (BC_,Q(6),output3,,5,,Z)"; end demo; Boundary Scan.28
29 Package package STD_49 99 is attribute PIN_AP:string; subtype PIN_AP_STRING is string; type CLOCK_LEVEL is (LOW, BOTH); type CLOCK_INFO is record FREQ:real; LEVEL:CLOCK_LEVEL; end record; attribute TAP_SCAN_IN: boolean; attribute TAP_SCAN_OT:boolean; attribute TAP_SCAN_CLOCK:CLOCK_INFO; attribute TAP_SCAN_ODE:boolean; attribute TAP_SCAN_RESET:boolean; attribute INSTRCTION_LENGTH:integer; attribute INSTRCTION_OPCODE:string; attribute INSTRCTION_CAPTRE:string; Boundary Scan.29
30 Package (Cont.) type ID_BITS is ('', '', ''); type ID_STRING is array (3 downto ) of ID_BIT attribute REGISTER_ACCESS:string type BSCAN_INST is (ETEST, SAPLE, INTEST,RNBIST); type CELL_TYPE is (INPT, INTERNAL, CLOCK, CONTROL, OTPT2, OTPT3, BIDIR_IN, BIDIR_OT); type CAP_DATA is (PI, PO, PD, CAP,, ZRRO, ONE); type CELL_DATA is record CT:CELL_TYPE; I:BSCAN_INST; CD:CAP_DATA; end record; type CELL_INFO is array(positive range<>) of CELL_DATA; constant BC_:CELL_INFO; attribute BONDARY_CELLS:string; attribute BONDARY_LENGTH:integer; attribute BONDARY_REGISTER:string; attribute DESIGN_WARING:string; end STD_49 99; Boundary Scan.3
31 Package Body constant BC_:CELL_INFO:=( (INPT,ETEST,PI), (OTPT2,ETEST,PI), (INPT,SAPLE,PI), (OTPT2,SAPLE,PI), (INPT,INTEST,PI). (OTPT2,INTEST,PI), (OTPT3,ETEST,PI), (INTERNAL,ETEST,PI), (OTPT3, SAPLE,PI), (INTERNAL,SAPLE,PI), (OTPT3, INTEST,PI), (INTERNAL,INTEST,PI), (CONTROL,ETEST,PI),(CONTROL,ETEST,PI), (CONTROL,SAPLE,PI),(CONTROL,SAPLE,PI), (CONTROL,INTEST,PI),(CONTROL,INTEST,PI) ); Boundary Scan.3
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