Testing and Programming PCBA s during Design and in Production
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1 Testing and Programming PCBA s during Design and in Production Hogeschool van Arnhem en Nijmegen 6 June 23 Rob Staals JTAG Technologies [email protected] Copyright 23, JTAG Technologies juni 3
2 The importance of Testing Don t ship bad boards to your customers, find problems before your customers do. DOA s (Death On Arrival) lead to huge costs (rule of ten) The "rule of ten" specifies that it costs times more to find and repair a defect at the next stage of assembly. the part itself at sub-assembly at final assembly at the dealer/distributor. at the customer. Important to find defects in an early stage. 2 Copyright 23, JTAG Technologies juni 3
3 What are you testing Simplified statement: If all components are correctly soldered - the board should work Assuming: Design is right Components are OK (ppm -.ppm) Conclusion: Testing the interconnections should be sufficient to detect a great deal of bad boards. 3 Copyright 23, JTAG Technologies juni 3
4 Error analysis based on real PCBA production data Tombstoning Others 3% 6% 26% Shorts incl. SA/SA Component defect 7% Careless placement % Upside down 9% 2% Not placed 7% Opens 4 Copyright 23, JTAG Technologies juni 3
5 Commonly used Testmethods AOI Automated Optical Inspection 5 Copyright 23, JTAG Technologies juni 3
6 Commonly used Testmethods AXI Automated X-ray Inspection 6 Copyright 23, JTAG Technologies juni 3
7 Commonly used Testmethods FP Flying Probe 7 Copyright 23, JTAG Technologies juni 3
8 Commonly used Testmethods ICT In Circuit Test 8 Copyright 23, JTAG Technologies juni 3
9 Commonly used Testmethods FT Functional Test 9 Copyright 23, JTAG Technologies juni 3
10 Functional vs Structural Test Functional Test Checks every function of the board (interconnects are implicitly tested) - Manual creation of the tests - Very difficult to diagnose, doesn t pinpoint to the exact location of the problem - Requires highly skilled engineers - Time consuming - Expensive test, very good as final test to check specifications Structural Test (AOI, AXI, FP and ICT) Checks the structure of the board (interconnects, device orientation, device values etc.) - test + Automatic generation based on the Netlist + Low cost + Pinpoints to the exact location of the problem if sufficient testpoints are available Copyright 23, JTAG Technologies juni 3
11 FP and ICT interconnection test The probes of a Flying Prober and In Circuit Tester are connected to a measurement system. Compare this with the probes of a multimeter. Moving around with the probes will pinpoint to the exact location of the interconnection problem. Copyright 23, JTAG Technologies juni 3
12 How to perform a Structural Test on a board containing Hi-density devices like BGA s The probes of a Flying Prober or In Circuit Tester require a minimum clearance and have no access to the BGA pins How to solve this problem? 2 Copyright 23, JTAG Technologies juni 3
13 How to solve the access problem 3 Copyright 23, JTAG Technologies juni 3
14 Boundary-scan is the solution to the access problem What is Boundary-scan and how does it work Official standard: IEEE Std Copyright 23, JTAG Technologies juni 3
15 Boundary-scan architecture The Boundary-scan architecture is a standard implementation in many devices, such as µs, DSPs, FPGAs etc.. I/ I/ I/ I/ I/ I/ I/ I/ I/
16 Boundary-scan architecture Additional Testlogic and pins have been added I/ I/ I/ I/ I/ Boundary-Scan Register BSR I/ I/ I/ I/ Bypass TMS TCK TRST Optional Instruction register TMS TCK TRST Test Data In Test Data Out Test Mode Select Test Clock Test Reset
17 Via a Testvectors is shifted into the BSR Testvector Bypass TMS Instruction register TCK TRST Optional
18 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
19 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
20 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
21 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
22 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
23 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
24 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
25 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
26 Shift-in Testvector via Bypass Shift TMS Instruction register TCK TRST Optional
27 UPDATE drives the BSR data onto all pins simultaneously Bypass Update TMS TCK TRST Optional Instruction register
28 UPDATE command The UPDATE command can be compared with one probe of the multimeter, but than for all Bscan I/O pins simultaneously (hundreds thousands pins). However for a proper interconnection measurement a second probe is required. This is established with the CAPTURE command. 28 Copyright 23, JTAG Technologies juni 3
29 CAPTURE simultaneously senses the values on the pins and stores it in the BSR The nets are at a certain logic level. Bypass TMS TCK TRST Optional Instruction register
30 CAPTURE simultaneously senses the values on the pins and stores it in the BSR Bypass Capture TMS TCK TRST Optional Instruction register
31 CAPTURE command The Capture command can be compared with the second probe of the multimeter, but than for all Bscan I/O pins simultaneously. The UPDATE and CAPTURE commands provides direct access to hundreds or thousands I/O pins. Each Bscan I/O pin can be seen as a build-in TESTPROBE. 3 Copyright 23, JTAG Technologies juni 3
32 Shift-out captured data After the values on the pins have been captured into the BSR the result is shifted out via. The result can be compared with the expected data. Any difference pin-points to the error location. 32 Copyright 23, JTAG Technologies juni 3
33 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
34 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
35 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
36 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
37 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
38 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
39 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
40 Shift-out Captured data via Result Bypass Shift TMS TCK TRST Optional Instruction register
41 Compare Captured data with expected result Expected Result Bypass TMS Instruction register Mismatch TCK TRST Optional
42 Example Test the interconnections between Boundary-scan devices 42 Copyright 23, JTAG Technologies juni 3
43 Test interconnections between Bscan devices IC IC2 BP IR BP IR TMS TCK Goal: Test the interconnections between IC and IC2 Both - chains are cascaded 43 Copyright 23, JTAG Technologies juni 3
44 Calculate the required Testvector IC IC2 Testvector xxxx BP IR BP IR TMS TCK. Calculate Testvector for testing the interconnects 44 Copyright 23, JTAG Technologies juni 3
45 Shift-in testvector via IC IC2 Testvector xxxx BP IR BP IR SHIFT TMS TCK 2. Repeat Shift operation until testvector is in the corresponding cells 45 Copyright 23, JTAG Technologies juni 3
46 UPDATE IC IC2 Testvector xxxx BP IR BP IR UPDATE TMS TCK 3. The UPDATE command drives the testvector onto the pins of IC and thus on the corresponding nets. 46 Copyright 23, JTAG Technologies juni 3
47 CAPTURE IC IC2 Testvector xxxx BP IR BP IR CAPTURE TMS TCK 4. The CAPTURE command senses the values on the pins and puts them into the BSR 47 Copyright 23, JTAG Technologies juni 3
48 Shift-out result and compare with expected IC Testvector xxxx BP IR IC2 Result BP IR xxxx SHIFT TMS TCK 5. The Captured result is shifted-out on and compared with the expected value. Any mismatch pin-points to the location of the failure. Mismatch Caused by an open underneath this pin 48 Copyright 23, JTAG Technologies juni 3
49 Compare Result with Expected and Diagnose The diagnostics pin-points to the exact error location Errors are shown in inverse video. In this case the result was a however a was expected.. and are for Input H, L and Z are for output 49 Copyright 23, JTAG Technologies juni 3
50 Faultdetection With the aid of Intelligent testvectors Opens Shorts SA and SA problems are easily detected The Intelligent testvectors are based on an Enhanced Binary Search principle. (Minimum set of Testvectors with a Maximum Testcoverage) 5 Copyright 23, JTAG Technologies juni 3
51 Testing connectivity of Non-Bscan components Bscan Non-Bscan Bscan Boundary-scan chain 5 Copyright 23, JTAG Technologies juni 3
52 Testing connectivity NAND Gate A B & Y Bscan Bscan A B Y Boundary-scan chain Use Truthtable to stimulate the inputs and sense the outputs of the NAND using the Bscan cells. A model contains information about the Truthtable. 52 Copyright 23, JTAG Technologies juni 3
53 Testing connectivity MEMORY ADD Bscan RAM DATA Bscan Ctrl Boundary-scan chain Stimulate the Add/Data/Ctrl pins to write and read data from the RAM. The information on how to read/write to the memory is described in a model. 53 Copyright 23, JTAG Technologies juni 3
54 Testing connectivity FLASH ADD Bscan FLASH DATA Bscan Ctrl Boundary-scan chain A model contains all the information on how to get access to the FLASH. 54 Copyright 23, JTAG Technologies juni 3
55 I/O Connector LoopBack Connector Testing connectivity I/O plus Connector () Bscan Bscan Boundary-scan chain Use loopback connector to test the connectivity of the I/O block and Connector 55 Copyright 23, JTAG Technologies juni 3
56 I/O Connector External Bscan board Testing connectivity I/O plus Connector (2) Bscan Bscan Boundary-scan chain Use an external Bscan board with required # of I/O pins to get full access. 56 Copyright 23, JTAG Technologies juni 3
57 Testing connectivity serial devices like I2C, SPI etc. SDA SLC Bscan I2C Bscan Boundary-scan chain Simulating the I2C protocol givess access to the I2C device The information on how to simulate the serial protocol is defined in a model. 57 Copyright 23, JTAG Technologies juni 3
58 Using the JTAG interface for Programming Besides Testing, the JTAG interface can also be used for Programming. 58 Copyright 23, JTAG Technologies juni 3
59 Programming CPLD and FPGA Logic cells Interconnections JTAG Interface 59 Copyright 23, JTAG Technologies juni 3
60 Programming CPLD and FPGA JTAG Interface CPLDs and FPGAs use the JTAG interface to directly download the configuration file into the device. 6 Copyright 23, JTAG Technologies juni 3
61 Programming CPLD and FPGA JTAG Interface Fortunately, these chips also have a Boundary-scan chain that gives direct access to surrounding devices 6 Copyright 23, JTAG Technologies juni 3
62 Programming external FLASH ADD Bscan FLASH DATA Bscan Ctrl Boundary-scan chain The Image file gets integrated in the Bscan Addr-Data-Ctrl patterns to program the FLASH. 62 Copyright 23, JTAG Technologies juni 3
63 Programming Embedded Flash Internal FLASH µ JTAG Interface Some µs have internal flash that gets directly programmed via de JTAG interface 63 Copyright 23, JTAG Technologies juni 3
64 Demonstration 64 Copyright 23, JTAG Technologies juni 3
65 Blockdiagram 65 Copyright 23, JTAG Technologies juni 3
66 Full access through the TAP TAP 66 Copyright 23, JTAG Technologies juni 3
67 Software tools JTAG Live Buzz Free Download 67 Copyright 23, JTAG Technologies juni 3
68 Supported controllers 68 Copyright 23, JTAG Technologies juni 3
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