FPGA Synthesis Example: Counter Peter Marwedel Informatik XII, U. Dortmund
Gliederung Einführung SystemC Vorlesungen und Programmierung FPGAs - Vorlesungen - VHDL-basierte Konfiguration von FPGAs mit dem XUP VII Pro Entwicklungssystem Algorithmen - Mikroarchitektur-Synthese - Automatensynthese - Logiksynthese - Layoutsynthese Zeitplan 3,5 W ochen 3,5 W ochen 6 Wochen - 2-
http://www.xilinx.com/support/ sw_manuals/xilinx8/download/qst.zip ISE design flow - 3-
tutorial Some slides use patched project name Starting a more complex design example Set simulator to ISE for installations without separate Modelsim simulator. - 4-
Generated design header tutorial tutorial - 5-
Using language templates to define architectural body tutorial Open edit menu - 6-
Select simple counter tutorial Select simple counter template and copy tutorial - 7-
Copy template to current design tutorial Adapt template as required tutorial - 8-
Adding testbench tutorial Add new source to counter tutorial - 9-
Set waveform for clock tutorial tutorial - 10 -
Define waveform for other signals tutorial tutorial Click on direction signal to define transitions - 11 -
View generated testbench q - 12 -
Automatically generate expected waveform (1) tutorial Select testbench and check process view q tutorial - 13 -
Automatically generate expected waveform (2) Requires ISE to be specified as the simulator for the project (and simulator must be available). - 14 -
Replacing the original testbench Overwriting initial testbench - 15 -
Automatic or manual comparison? Click on yes/ja in order to compare automatically. Initially unknown. - 16 -
Automatic comparison Added when responding 'yes' for the 1st time - 17 -
Behavioral simulation - 18 -
Adding timing constraints (1) Double click on timing constraints - 19 -
Adding timing constraints (2) q - 20 -
Adding timing constraints (3) - 21 -
Add pin constraints Use table from slides fga-01-22 -
Synthesis - 23 -
Viewing synthesis results (1) Double click on view RTL - 24 -
Viewing synthesis results (2) Initially, top level module is visible. - 25 -
Enter lower level of the hierarchy (1) Right click on module - 26 -
Enter lower level of the hierarchy (2) Oops: no counter register, but separate add/sub component; Additional buffers generated - 27 -
After placement & routing After zooming After double click on place & route; now: check result - 28 -
View result of placement and routing (1) After zooming - 29 -
View result of placement and routing (2) After zooming even more - 30 -
List of used components After enlarging left window - 31 -
Viewing the design summary - 32 -
Estimated power consumption - 33 -
Generate Post-Place & Route Static Timing - 34 -
Checking Timing constraints (1) - 35 -
Checking Timing constraints (2) - 36 -
View routed design (1) - 37 -
View routed design (2) - 38 -
View routed design (3) 4 slices in 1 CLB used - 39 -
Simulate Post-Place & Route HDL Model (1) - 40 -
Simulate Post-Place & Route HDL Model (2) Propagation delays are visible at this level - 41 -
Simulate Post-Place & Route HDL Model (3) Using the measure marker - 42 -
Generation of configuration file - 43 -
Generation of configuration file - 44 -
Summary Fast path through design flow with Xilinx ISE - 45 -