Introduction to Flash Memory

Transcription

1 Introduction to Flash Memory ROBERTO BEZ, EMILIO CAMERLENGHI, ALBERTO MODELLI, AND ANGELO VISCONTI Invited Paper The most relevant phenomenon of this past decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipment (palm top, mobile PC, mp3 audio player, digital camera, and so on). Moreover, in the coming years, portable systems will demand even more nonvolatile memories, either with high density and very high writing throughput for data storage application or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility, and the cost make the Flash memory a largely utilized, well-consolidated, and mature technology for most of the nonvolatile memory applications. Today, Flash sales represent a considerable amount of the overall semiconductor market. Although in the past different types of Flash cells and architectures have been proposed, today two of them can be considered as industry standard: the common ground NOR Flash, that due to its versatility is addressing both the code and data storage segments, and the NAND Flash, optimized for the data storage market. This paper will mainly focus on the development of the NOR Flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler Nordheim tunneling. The main reliability issues, such as charge retention and endurance, will be discussed, together with the understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, will be presented. In fact, the exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range, and reducing the cost per bit. Finally, the NOR Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore s law down to the 130-nm technology generations. The technology development and the consolidated know-how is expected to sustain the scaling trend down to the 90- and 65-nm technology nodes as forecasted by the International Technology Roadmap of Semiconductors. One of the crucial issues to be solved Manuscript received July 1, 2002; revised January 5, The authors are with the Central Research and Development Department, Non-Volatile Memory Process Development, STMicroelectronics, Agrate Brianza, Italy ( [email protected]). Digital Object Identifier /JPROC to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms. Keywords Flash evolution, Flash memory, Flash technology, floating-gate MOSFET, multilevel, nonvolatile memory, NOR cell, scaling. I. INTRODUCTION The semiconductor market, for the long term, has been continuously increasing, even if with some valleys and peaks, and this growing trend is expected to continue in the coming years (see Fig. 1). A large amount of this market, about 20%, is given by the semiconductor memories, which are divided into the following two branches, both based on the complementary metal oxide semiconductor (CMOS) technology (see Fig. 2). The volatile memories, like SRAM or DRAM, that although very fast in writing and reading (SRAM) or very dense (DRAM), lose the data contents when the power supply is turned off. The nonvolatile memories, like EPROM, EEPROM, or Flash, that are able to balance the less-aggressive (with respect to SRAM and DRAM) programming and reading performances with nonvolatility, i.e., with the capability to keep the data content even without power supply. Thanks to this characteristic, the nonvolatile memories offer the system a different opportunity and cover a wide range of applications, from consumer and automotive to computer and communication (see Fig. 3). The different nonvolatile memory families can be qualitatively compared in terms of flexibility and cost (see Fig. 4). Flexibility means the possibility to be programmed and erased many times on the system with minimum granularity (whole chip, page, byte, bit); cost means process complexity and in particular silicon occupancy, i.e., density or, in simpler words, cell size. Considering the flexibility-cost plane, it turns out that Flash offers the best compromise between these two parameters, since they have the smallest cell size /03$ IEEE PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL

2 Fig. 1. Semiconductor market: revenues versus year. The bottom wave refers to the semiconductor memory amount. Fig. 4. Nonvolatile memory (NVM) qualitative comparison in the flexibility cost plane. A common feature of NVMs is to retain the data even without power supply. Fig. 2. MOS memory tree. Based on these market needs, a well-known way to classify Flash products and the relative technologies is that of defining two major application segments: code storage, where the program or the operating system is stored and is executed by the microprocessor or microcontroller; data (or mass) storage, where data files for image, music, and voice are recorded and read sequentially. Different type of Flash cells and architectures have been proposed in the past (see Fig. 5). They can be divided in terms of access type, parallel or serial, and in terms of the utilized programming and erasing mechanism, Fowler Nordheim tunneling (FN), channel hot electron (CHE), hot-holes (HH), and source-side hot electron (SSHE). Among all of these architectures, today two can be considered as industry standard: the common ground NOR Flash [1] [3], that due to its versatility is addressing both the code and data storage segments, and the NAND Flash, optimized for the data storage market [4], [5]. In the following, the basic concepts, the reliability issues, the evolution, and scaling trends will be presented only for the NOR Flash cell, but most of these considerations are also valid for the NAND since both of them are based on the concept of floating-gate MOS transistor. Fig. 3. Main nonvolatile memory applications. (one transistor cell) with a very good flexibility (they can be electrically written on field more than times, with byte programming and sectors erasing). The most relevant phenomenon of this past decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipment (palm top, mobile PC, mp3 audio player, digital camera, and so on). Moreover, in the coming years, portable systems will demand even more nonvolatile memories, either with high density and very high writing throughput for data storage application or with fast random access for code execution in place. II. NOR FLASH CELL In 1971, Frohman-Bentchkowsky presented a floating gate transistor in which hot electrons were injected and stored [6], [7]. From this original work, the erasable programmable read only memory (EPROM) cell, programmed by CHE and erased by ultraviolet (UV) photoemission, has been developed. The EPROM technology became the most important nonvolatile memory in the 1980s. In the same period, the Flash EEPROM was proposed, basically an EPROM cell, with the possibility to be electrically erased [8]. The name Flash was given to represent the fact that the whole memory array could be erased in the same (fast) time. The first Flash product was presented in 1988 [9]. In terms of applications, initially Flash products were mainly used as an EPROM replacement, offering the possibility to be erased on system, avoiding the cumbersome UV erase oper- 490 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

3 Fig. 5. The family tree of Flash memory cell architecture. The actual industry standard are: 1) The NOR for code and data storage application and 2) NAND only for data storage. Fig. 6. Semiconductor memory market for the main memory, i.e., DRAM, Flash, and SRAM. ation. But the Flash market did not take off until this technology was proven to be reliable and manufacturable. In the late 1990s, the Flash technology exploded as the right nonvolatile memory for code and data storage, mainly for mobile applications. Starting from 2000, the Flash memory can be considered a really mature technology: more than 800 million units of 16-Mb equivalent NOR Flash devices were sold in that year. In Fig. 6, the Flash market is reported and compared with the DRAM and SRAM one [10]. It can be seen that the Flash market became and has stayed bigger than the SRAM one since Moreover, the Flash market is forecasted to be above $20 billion in three or four years from now, reaching the DRAM market amount, and only smoothly following the DRAM oscillating trend, driven by the personal computer market. In fact, portable systems for communications and consumer markets, which are the drivers of the Flash market, are forecasted to continuously grow in the coming years. In the following, we briefly describe the basics of the Flash cell functionality. Fig. 7. Schematic cross section of a Flash cell. The floating-gate structure is common to all the nonvolatile memory cells based on the floating-gate MOS transistor. A. Basic Concept A Flash cell is basically a floating-gate MOS transistor (see Fig. 7), i.e., a transistor with a gate completely surrounded by dielectrics, the floating gate (FG), and electrically governed by a capacitively coupled control gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device; charge injected in the FG is maintained there, allowing modulation of the apparent threshold voltage (i.e., seen from the CG) of the cell transistor. Obviously the quality of the dielectrics guarantees the nonvolatility, while the thickness allows the possibility to program or erase the cell by electrical pulses. Usually the gate dielectric, i.e., the one between the transistor channel and the FG, is an oxide in the range of 9 10 nm and is called tunnel oxide since FN electron tunneling occurs through it. The dielectric that separates the FG from the CG is formed by a triple layer of oxide nitride oxide (ONO). The ONO thickness is in the range of nm of equivalent oxide thickness. The ONO layer as interpoly dielectric has been introduced in order to improve the tunnel oxide quality. In fact, the BEZ et al.: INTRODUCTION TO FLASH MEMORY 491

4 Fig. 8. Schematic energy band diagram (lower part) as referred to a floating gate MOSFET structure (upper part). The left side of the figure is related to a neutral cell, while the right side to a negatively charged cell. Fig. 9. (a) NOR Flash array equivalent circuit. (b) Flash memory cell cross section. use of thermal oxide over polysilicon implies growth temperature higher than 1100 C, impacting the underneath tunnel oxide. High-temperature postannealing is known to damage the thin oxide quality. If the tunnel oxide and the ONO behave as ideal dielectrics, then it is possible to schematically represent the energy band diagram of the FG MOS transistor as reported in Fig. 8. It can be seen that the FG acts as a potential well for the charge. Once the charge is in the FG, the tunnel and ONO dielectrics form potential barriers. The neutral (or positively charged) state is associated with the logical state 1 and the negatively charged state, corresponding to electrons stored in the FG, is associated with the logical 0. The NOR Flash name is related to the way the cells are arranged in an array, through rows and columns in a NOR-like structure. Flash cells sharing the same gate constitute the so-called wordline (WL), while those sharing the same drain electrode (one contact common to two cells) constitute the bitline (BL). In this array organization, the source electrode is common to all of the cells [Fig. 9(a)]. A scanning electron microscope (SEM) cross section along a bitline of a Flash array is reported in Fig. 9(b), where three cells can be observed, sharing two by two the drain contact and the sourceline. This picture can be better understood considering the layout of a cell (see Fig. 10) and the two schematic cross sections, along the direction (bitline) and the direction (wordline). The cell area is given by the pitch times the pitch. The pitch is given by the active area width and space, considering also that the FG must overlap the oxide field. The pitch is constituted by the cell gate length, the contact-to-gate distance, half contact, and half sourceline. It is evident, as reported in Fig. 9(b), that both contact and sourceline are shared between two adjacent cells. B. Reading Operation The data stored in a Flash cell can be determined measuring the threshold voltage of the FG MOS transistor. The best and fastest way to do that is by reading the current driven by the cell at a fixed gate bias. In fact, as schematically reported in Fig. 11, in the current voltage plane two cells, respectively, logic 1 and 0 exhibit the same transconductance curve but are shifted by a quantity the threshold voltage shift ( ) that is proportional to the stored electron charge. Hence, once a proper charge amount and a corresponding is defined, it is possible to fix a reading voltage in such 492 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

5 Fig. 12. Writing mechanism in floating-gate devices. Fig. 10. The NOR Flash cell. (a) Basic layout. (b) Updated Flash product (64-Mb, 1.8-V Dual bank). (c) and (d) are, respectively, the schematic cross section along bitline (y pitch) and wordline (x pitch). Fig. 13. NOR Flash writing mechanism. Fig. 11. Floating-gate MOSFET reading operation. a way that the current of the 1 cell is very high (in the range of tens of microamperes), while the current of the 0 cell is zero, in the microampere scale. In this way, it is possible to define the logical state 1 from a microscopic point of view as no electron charge (or positive charge) stored in the FG and from a macroscopic point of view as large reading current. Vice versa, the logical state 0 is defined, respectively, by electron charge stored in the FG and zero reading current. C. Writing Operation Considering Fig. 8, the problem of writing an FG cell corresponds to the physical problem of forcing an electron above or across an energy barrier. The problem can be solved exploiting different physical effects [11]. In Fig. 12, the three main physical mechanisms used to write an FG memory cell are sketched. The CHE mechanism, where electrons gain enough energy to pass the oxide silicon energy barrier, thanks to the electric field in the transistor channel between source and drain. In fact, the electron energy distribution presents a tail in the high energy side that can be modulated by the longitudinal electric field. The photoelectric effect, where electrons gain enough energy to surmount the barrier thanks to the interaction with a photon with energy larger than the barrier itself. For silicon dioxide, this corresponds to UV radiation. This mechanism is the one originally used in EPROM s products to erase the entire device. The Fowler Nordheim electron tunneling mechanism is a quantum-mechanical tunnel induced by an electric field. Applying a strong electric field (in the range of 8 10 MV/cm) across a thin oxide, it is possible to force a large electron tunneling current through it without destroying its dielectric properties. A NOR Flash memory cell is programmed by CHE injection in the FG at the drain side and it is erased by means of the FN electron tunneling through the tunnel oxide from the FG to the silicon surface (see Fig. 13). III. RELIABILITY Many issues have to be addressed when, from the theoretical model of a single cell, a Flash product has to be realized, integrating millions of cells in an array. Nonvolatility implies at least ten years of charge retention, and the data must be stored in a cell after many read/program/erase cycles. The confidence in Flash memory reliability has grown together with the understanding of the single memory cell failure mechanisms. BEZ et al.: INTRODUCTION TO FLASH MEMORY 493

6 Fig. 14. Threshold voltage distribution of a 1-Mb Flash array after UV erasure, after CHE programming, and after FN erasure. The high degree of testability [12] allows the detection at wafer level of latent defects which may cause single-cell failures related to programming disturbs, data retention, and oxide defects [13], thus making Flash one of the most reliable nonvolatile memories. A. Threshold Voltage Distribution When dealing with a large array of cells, e.g., from tens of thousands to one million, it is very important to understand the type of dispersion given by the large set of cells. The best way to do it is to compare the threshold voltage distribution of the whole array, considering it after UV erasure that can be considered as the reference state after CHE programming and after FN erasing. Fig. 14 shows typical distributions of cell threshold voltages in a large memory array. The UV-erased distribution is pretty narrow and symmetrical. A more accurate analysis would reveal a Gaussian distribution due to random variations of critical dimensions, thickness, and doping which contribute to cause a dispersion of threshold voltages, either directly or through coupling ratios. The programmed distribution is wider than the UV-erased one, but it is still symmetrical. The enlargement occurs because most of the parameters that cause dispersion of UV-erased cells also impact the threshold shift of programmed cells. The distribution of threshold voltages after electrical erase is much wider and heavily asymmetrical. A more detailed analysis would show that the bulk of the distribution is again a Gaussian with a standard deviation larger than the one of programmed cells. Cells in this part of the distribution are referred to as normal cells. But there is also an exponential tail at low, composed of cells that erase faster than the average, also called tail cells. The dispersion of threshold voltages of normal cells is due to coupling ratio variations, and it has been accurately modeled [14]. Instead, the understanding of the tail cells, although of key importance, is more difficult. In fact, as these cells erase faster than normal cells with the same applied voltage, one should assume that they are somehow defective. However, they are just too numerous for being associated with extrinsic defects. Fig. 15. Schematic of a Flash array, showing row and column disturbs occurring when the cycled cell is programmed. Different models have been presented with the aim to explain the tail cells. For example, a distribution in the polycrystalline structure of the FG, with a barrier height variation at the grain boundaries, would give rise to a local enhancement of the tunnel barrier [15]. Another model explains the tail cells as due to randomly distributed positive charges in the tunnel oxide [16]. This model is solidly based on the well-known existence of donor-like bulk oxide traps and on calculations that show the huge increase of the tunnel current density caused by the presence of an elementary positive charge closed to injecting electrode. Independently from a consolidated model, it can be stated that the exponential tail of the erased distribution is mostly related to structural imperfections, i.e., intrinsic defects, and it can be minimized by process optimization (for example, working on silicon surface preparation, tunnel oxidation, FG polysilicon optimization) but not eliminated. Flash products must be designed taking into account the existence of such a tail. B. Program Disturb The failure mechanisms referred to as program disturbs concern data corruption of written cells caused by the electrical stress applied to these cells while programming other cells in the memory array. Two types of program disturbs must be taken into account: row and column disturbs, also referred as gate and drain stress, as schematically reported in Fig. 15, representing a portion of a cell array. Row disturbs are due to gate stress applied to a cell while programming other cells on the same wordline. If a high voltage is applied to the selected row, all the other cells of that row must withstand the gate stress without losing their data. Depending on the data stored in the cells, data can be lost either by a leakage in the gate oxide or by a leakage in the interpoly dielectric. Column disturbs are due to drain stress applied to a cell while programming other cells on the same bitline. Under this condition, programmed cells can lose charge by FN tunneling from the FG to the drain (soft erasing). The program disturb depends on the number of cells along bitline and wordline and then depends strongly on the sector organization. The most effective way to prevent disturb propagation is to use block select transistor in a divided bitline and wordline 494 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

7 organization to completely isolate each sector. Program disturb really could be a critical issue in Flash memory, and cells and circuits must be designed with safety margins versus the stress sensitivity. C. Data Retention As in any nonvolatile memory technology, Flash memories are specified to retain data for over ten years. This means the loss of charge stored in the FG must be as minimal as possible. In updated Flash technology, due to the small cell size, the capacitance is very small and at an operative programmed threshold shift about 2 V corresponds a number of electrons in the order of 10 to 10. A loss of 20% in this number (around 2 20 electrons lost per month) can lead to a wrong read of the cell and then to a data loss. Possible causes of charge loss are: 1) defects in the tunnel oxide; 2) defects in the interpoly dielectric; 3) mobile ion contamination; and 4) detrapping of charge from insulating layers surrounding the FG. The generation of defects in the tunnel oxide can be divided into an extrinsic and an intrinsic one. The former is due to defects in the device structure; the latter to the physical mechanisms that are used to program and erase the cell. The tunnel oxidation technology as well as the Flash cell architecture is a key factor for mastering a reliable Flash technology. The best interpoly dielectric considering both intrinsic properties and process integration issues has been demonstrated to be a triple layer composed of ONO. For several generations, all Flash technologies have used ONO as their interpoly dielectric. The problem of mobile ion contamination has been already solved on the EPROM technology, taking particular care with the process control, but in particular using high phosphorus content in intermediate dielectric as a gettering element. [17], [18]. The process control and the intermediate dielectric technology have also been implemented in the Flash process, obtaining the same good results. Electrons can be trapped in the insulating layers surrounding the floating gate during wafer processing, as a result of the so-called plasma damage, or even during the UV exposure normally used to bring the cell in a well-defined state at the end of the process. The electrons can subsequently detrap with time, especially at high temperature. The charge variation results in a variation of the floating gate potential and thus in cell decrease, even if no leakage has actually occurred. This apparent charge loss disappears if the process ends with a thermal treatment able to remove the trapped charge. The retention capability of Flash memories has to be checked by using accelerated tests that usually adopt screening electric fields and hostile environments at high temperature. D. Programming/Erasing Endurance Flash products are specified for 10 erase/program cycles. Cycling is known to cause a fairly uniform wear-out of the cell performance, mainly due to tunnel oxide degradation, which eventually limits the endurance characteristics [19]. A Fig. 16. Threshold voltage window closure as a function of program/erase cycles on a single cell. Fig. 17. number. Program and erase time as a function of the cycles Fig. 18. Anomalous SILC modeling. The leakage is caused by a cluster of positive charge generated in the oxide during erase (left-hand side). The multitrap assisted tunneling is used to model SILC: trap parameters are energy and position. typical result of an endurance test on a single cell is shown in Fig. 16. As the experiment was performed applying constant pulses, the variations of program and erase threshold voltage levels are described as program/erase threshold voltage window closure and give a measure of the tunnel oxide aging. In real Flash devices, where intelligent algorithms are used to prevent window closing, this effect corresponds to a program and erase times increase (see Fig. 17). In particular, the reduction of the programmed threshold with cycling is due to trap generation in the oxide and to interface state generation at the drain side of the channel, which are mechanisms specific to hot-electron degradation. BEZ et al.: INTRODUCTION TO FLASH MEMORY 495

8 Fig. 19. Data retention tests at room temperature. The evolution of the erase threshold voltage reflects the dynamics of net fixed charge in the tunnel oxide as a function of the injected charge. The initial lowering of the erase is due to a pile-up of positive charge which enhances tunneling efficiency, while the long-term increase of the erase is due to a generation of negative traps. Cycling wear-out can be reduced by proper device engineering and by optimization of the tunnel oxide process. However, once process and product are qualified for a given endurance specification, no major problems should come from lot-to-lot variation. Actually, endurance problems are mostly given by single-cell failures, which present themselves like a retention problem after program/erase cycles. In fact, a high field stress on thin oxide is known to increase the current density at low electric field. The excess current component, which causes a significant deviation from the current voltage curves from the theoretical FN characteristics at low field, is known as stress-induced leakage current (SILC). SILC is clearly attributed to stress-induced oxide defects and, as far as a conduction mechanism, it is attributed to a trap assisted tunneling (see Fig. 18). The main parameters controlling SILC are the stress field, the amount of charge injected during the stress, and the oxide thickness. For fixed stress conditions, the leakage current increases strongly with decreasing oxide thickness [20] [22]. The effect of cycling on data retention cannot be referred to in the typical cell, but must be studied considering a wide array of cells, looking in particular to the tail distribution. In Fig. 19, we report the results of retention test on a 1-Mb array of cells with 8-nm tunnel oxide in order to enhance the SILC defects in single cells. Retention tests have been performed on arrays cycled 10 and 10 times [23]. As can be seen, the amount of cells that lose charge after three years are much more in the case of longer endurance. Data retention after cycling is the issue that definitely limits the tunnel oxide thickness scaling. For very thin oxide, below 8 9 nm, the number of leaky cells becomes so large that even error-correction techniques cannot fix the problem. IV. MULTILEVEL CONCEPT An attractive way to speed up the scaling of Flash memory is offered by the multilevel (ML) concept [24]. The idea is Fig. 20. DV as a function of the pulse number for three different channel lengths (the upper axis also shows the gate voltage at each programming step). based on the ability to precisely control the amount of charge stored into the floating gate in order to set the threshold voltage of a memory cell within any of a number of different voltage ranges, corresponding to different logical levels. A cell operated with 2 different levels is capable of storing bits, the case being the conventional single-bit cell. Three main issues must be afforded when going from conventional to ML Flash [25]. A high programming accuracy is required to obtain narrow distributions; reading operation implies multiple, either serial or parallel, comparison with suitable references to determine the cell status, requiring accurate and fast current sensing; window and read voltage are larger while read margins are smaller than the single-bit case, this for allocating all levels, requiring improved reliability and/or error-correction circuitry. These key points will be discussed with reference to a common-ground NOR architecture. A. Multilevel Flash Programming CHE programming has been shown to give, under proper conditions, a linear relationship with unit slope between programming gate voltage and variation [26], independently of cell parameters (see Fig. 20). Very tight distri- 496 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

9 Fig. 21. Schematic of the control-gate voltage pulses. Fig. 23. Threshold voltage distribution for 2 b/cell compared with the standard 1 b/cell. Fig. 22. Parallel multilevel sensing architecture. MSB = most significant bit; LSB = less significant bit. butions can be obtained by combining a program-and-verify technique with a staircase ramp (see Fig. 21). In fact, this method should theoretically lead to a distribution width for any state not larger than. Indeed, neglecting any error due to sense amplifier inaccuracy or voltage fluctuations, the last programming pulse applied to a cell will cause its threshold voltage to be shifted above the program verify decision level by an amount at most as large as. It follows that by decreasing, it is possible to increase the programming accuracy. Obviously, this is paid in terms of a larger number of programming pulses together with verify phases and, therefore, with a longer programming time. Hence, the best accuracy/time tradeoff must be chosen for each case considering the application specification. However, high programming throughput, equal to 1-b/cell devices, is normally achieved via a large internal program parallelism, which is possible because cells need a low programming current in ML staircase programming. To do that, ML devices operate with a program write buffer, whose typical length is bytes, i.e., cell data length. Also, evolution to 3 4 b/cell will not have an impact on programming throughput. In fact, program pulses and verify phases increase proportionally with the number of bits per cell, thus keeping roughly constant the effective byte programming time. Despite a not-negligible programming current, another advantage in using CHE programming for multilevel devices is to avoid the appearance of erratic bits that instead can be a potential failure mode affecting FN programming. In fact, erratic bit behavior was observed in the FN erase of standard NOR memories [27] but, for its nature, it should be present in every tunneling process [28]. B. Reading Operation In order to have a fast reading operation in the NOR cell, a parallel sensing approach can be used [29]. The cell current, obtained in reading conditions, is simultaneously compared with three currents provided by suitable reference cells (see Fig. 22). The comparison results are then converted to a binary code, whose content can be 11, 01, 10, or 00, due to the multilevel nature. In Fig. 23, we report the threshold voltage distribution of a 2-b/cell memory. The 11, 10, and 01 cell distribution will give rise to a different current distribution, measured at fixed, while the 00 cell distribution does not drain current as well as the programmed level of a standard 1-b/cell device. High read data rate, via page or burst mode, is normally supported by large internal read parallelism. A parallel sensing approach does not seem transferable to 3- or 4-b/cell generations because of the exponential increase, 2 1, in comparators number, respectively 7 or 15 per cell, that means exponential increase in sensing area and current consumption. At this moment, a serial sensing approach, e.g., dichotomic, or a mixed serial-parallel is considered the more suitable approach. Serial sensing is also useful for a 2-b/cell device when high-speed random access is not necessary, e.g., in Flash Cards applications. C. Data Retention One of the main concerns about multilevel is the reduced margin toward the charge loss, compared with the 1-b/cell approach. We can basically divide the problem of data retention into two different issues. The first is related to the extrinsic charge loss, i.e., to a single bit that randomly can have different behaviors with respect to the average and that usually form a tail in a standard distribution. It is well known that extrinsic charge loss strongly depends on tunnel oxide retention electric field and that this issue can become more critical if an enhanced cell threshold range has to be used to allocate the 2 levels [30]. This problem is usually solved with the introduction of the error correction code (ECC), whose correction power must be chosen as a function of the technology and of the specification required to the memory products. The second one is related to the intrinsic charge loss, i.e., to the behaviors of the Gaussian part of a cell distribution, BEZ et al.: INTRODUCTION TO FLASH MEMORY 497

10 Fig. 24. Shift in the threshold voltage distribution after 500 h bake at 250 C. Fig. 25. DRAM and Flash cell size reduction versus year. The scaling has been of about a factor 30 in ten years. that must be characterized and defined as a function of the different level distributions. In order to study the data retention on multilevel memories, usually tests at high-temperature bake on programmed cells are performed. A result of data retention after bake (500 h, 250 C) is shown in Fig. 24, on one million cells [31]. The maximum shift, which occurs for the uppermost level, is about 0.1 V. This means the spacing between levels is reduced by a very small amount. It is interesting to note that the three programmed levels are shifted by an amount proportional to their respective programmed, so that the spacing between adjacent levels is reduced by only a fraction of the observed maximum shift. V. EVOLUTION AND SCALING TREND The Flash memories were commercially introduced in the early 1990s and since that time they have been able to follow the Moore law or, better, the scaling rules imposed by the market. Fig. 25 reports in a logarithmic scale the Flash cell size as a function of time, from 1992 to It turns out that the reduction of the cell size has been about a factor 30 in those ten years, closely following the scaling of the DRAM, today still considered as the reference memory technology that sets the pace to the technology node evolution. More specifically, the NOR Flash cell has scaled from 4.2 m for the 0,6- m technology node to the present cell size of 0.16 m at the m node. Moreover, considering the multilevel approach for the Flash cell with the capability to store two bits in the same cell, as presented in Section IV, not only the scaling trend but even the bit size itself is well aligned with the DRAM one. Together with the Flash cell scaling, there has also been an evolution of the Flash product specification and application. Three main generations can be considered, well differentiated as a technology node, process complexity, and specification. First generation ( ). The Flash applications were mainly EPROM replacement. The products were characterized by a single array (bulk), with memory density from 256 kb to 2 Mb. The program and erase algorithms were controlled externally and all the product were dual voltage: 12 V for the write operations and 5 V for the power supply. Cycling specification was limited to 10. Second generation ( ). The Flash memory has become the right nonvolatile memory technology for code storage application, where software updates must be performed on the field. In particular, portable systems, mainly cellular phones, were strongly interested in this feature. The cellular phone applications brought a lot of innovations: The density was increased from 1 to 16 Mb and sectors were introduced, instead of a single (bulk) array, in order to allow different use of the memory (some sectors can be used to store code while others to store data, with different requirements in terms of cycling). Sector density was from 10 to 256 kb. A single voltage supply pin (5 or 3 V according to the system specification) substituted the two high-voltage and low-voltage pins previously used. The need to be programmed on field, without the possibility to have the high voltage from an external pin, has developed the technology to internally generate the writing voltages using charge-pump techniques. A high-voltage supply is sometimes still used, but limited to the first programming operation in the system manufacturing line, to improve the throughput. Algorithms to perform all the operation on the array reading programming and erasing were embedded into the device in order to avoid the need for an external microcontroller. 10 writing cycles were introduced as a specification. More than effectively needed by the system, this high endurance is the result of a highly reliable technology. Third generation (from 1998 on). The portable system specifications push toward Flash memory products that look more and more like an application-specific memory. Obviously, the density is one of the most important parameters, and devices well 498 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

11 Fig. 26. NOR Flash technology and architecture evolution. Fig. 27. Triple well structure cross section: schematic (left side) and SEM (right side). beyond 64 Mb will be realized entering the Flash in the gigabit era. The sectorization is becoming more complex, and dual or multiple bank devices have already been presented. In these devices, different groups of sectors ( banks) can be differently managed: at the same time one sector belonging to a bank can be read while another one, inside a different bank, can be programmed or erased. Also, following the general trend of reducing the power supply, the device supply is scaling to 1.8 V (with the consequent difficulties of internally generating high voltages starting from this low supply voltage value) and will go down to 1.2 V. Another issue, becoming more and more important, is the high data throughput, in particular considering the density increase. Burst mode is often used in order to speed up the reading operation and quickly download the software content, reaching up to 50 MB/s. The introduction of the different generation as well as the reduction of the cell size has been made possible by the developments of Flash technology and process, and of cell architecture. For what concerns the process architecture, all the main technology steps that have allowed the evolution of the CMOS technology have also been used for Flash. In Fig. 26, the different cell cross sections as a function of the different technology node are reported. For every generation, the main innovative introduced steps are pointed out. It turns out that the evolution of the different generations has been sustained by an increased process complexity, from the one gate oxide and one metal process with standard local oxidation of silicon isolation at the 0.8- m technology node, to the two gate oxides, three metals, and shallow trench isolation at the m node. In between is the introduction of tungsten plug, of self-aligned silicided junctions and gates, and the wide use of chemical mechanical polishing steps. But one of the most crucial technologies for Flash evolution was the high-energy implantation development that has allowed the introduction of the triple well architecture (see Fig. 27). With this process module, further development of the single-voltage products has been possible, allowing the easy management of the negative voltage required to erase the cell and, furthermore, the possibility to completely change the erasing scheme of the cell. In fact, as reported in Fig. 28, the cell programming and erasing applied voltages have been changed as a function of the different generation, always staying inside the CHE programming and the FN erasing. The first generation of cells BEZ et al.: INTRODUCTION TO FLASH MEMORY 499

12 Fig. 28. NOR Flash cell evolution. Fig. 29. NOR cell scaling. The basic layout has remained unchanged through different generations. was erased, applying the high voltage to the source junction and then extracting electrons from the FG-source overlap region (source erase scheme). This way was too expensive in terms of parasitic current, as the working conditions were very close to the junction breakdown. Moving to the second generation with the single-voltage devices, the voltage drop between the source and the FG was divided, applying a negative voltage to the control gate and lowering the source bias to the external supply voltage (negative gate source erase scheme). Finally, with the exploitation of the triple well also for the array, the erasing potential is now divided between the negative CG and the positive bulk (the isolated p-well) of the array, moving the tunneling region from the source to the whole cell channel (channel erase scheme). In this way, electrons are extracted from the FG all along the channel without any further parasitic current contribution from the source junction, consequently reducing the erase current amount of about three orders of magnitude; the latter being a clear benefit for battery saving in portable low-voltage applications. The NOR Flash cell is forecasted to scale again following the International Technology Roadmap of Semiconductors (ITRS) [32]. The introduction of the 130-nm technology node has occurred in with a cell size of 0.16 m [33], following the 10- golden rule for the cell area scaling, where is the technology node. The representation of the memory cell size in terms of number of is a usual way to compare different technology with the same metric; for example, the DRAM cell size is today quoted to stay in the range of 6 8. Fig. 30. NOR Flash cell scaling trends for cell area (right y axis) and cell aspect ratio (left y axis). Both values are normalized to the 130-nm technology node. The next technology step for the NOR Flash will be the 90-nm technology node in The cell size is expected to stay in the range of 10 12, translating to a cell area of m. As reported again in Fig. 29, the cell basic layout and structure has remained unchanged through the different generations. The area scales through the scaling of both the and pitch. Basically, this must be done contemporarily reducing the active device dimensions, effective length ( ) and width ( ), and the passive elements, such as contact dimension, contact to gate distance, and so on. For future generation technology nodes, i.e., the 65 nm in 2007 and the 45 nm in 2010, as forecasted by ITRS, the Flash cell reduction will face challenging issues. In fact, while the passive elements will follow the standard CMOS evolution, benefiting from all the technology steps and process modules proposed for the CMOS logic (like advanced lithography for contact size, cupper for metallization in very tight pitch), the active elements will be limited in the scaling. In particular, the effective channel length will be limited by the possibility to further scale the active dielectric, i.e., the tunnel oxide and the interpoly ONO. As already presented in Section III, the tunnel oxide thickness scaling is limited by intrinsic issues related to the Flash cell reliability, in particular the charge retention one, especially after many writing cycles. Although the direct tunneling, preventing the ten-year retention time, occurs at 6 7 nm, SILC considerations push the tunnel thickness limit to no less than 8 9 nm. Moreover, the effective 500 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

13 width reduction could be limited by the read current reduction, strongly proportional to the, then impacting the access time. Scaling the technology node, while the cell pitch will more and more approach the 2, the -pitch scaling will be limited by the cell gate scaling. Hence, for the 65- and 45-nm technology nodes, it is expected to have smaller cell size but with an increased number of, from 10 to 14. In particular, the cell aspect ratio, i.e., the pitch over the pitch, will continue to rise, due to the slowdown of the reduction. Fig. 30 reports the cell area and the cell-aspect ratio versus the technology node, both normalized at 130 nm. As can be observed, the cell area will be roughly one half at 90 nm (same number of ) and will decrease, but with slower trend at 65 and 45 nm. The cell-aspect ratio will continue to increase, almost doubling the one at 130 nm when the technology node will reach 45 nm. VI. SUMMARY With more than ten years of consolidated know-how and thanks to its flexibility and cost characteristics, Flash memory is today a largely utilized, well-consolidated, and mature technology for nonvolatile memory application. Flash sales represent a considerable amount of the overall semiconductor market. In particular, the NOR Flash is today the most diffused architecture, being able to serve both the code and the data storage market. The cell is basically a floating-gate MOS transistor, programmed by CHE and erased by Fowler Nordheim tunneling. The main reliability issues, like charge retention and endurance, have been extensively studied and the physical mechanism well understood in such a way to guarantee the present specification requirements. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore s law down to the 130-nm technology generations. The technology development and the consolidated know-how will sustain the scaling trend down to the 90- and 65-nm technology nodes as forecasted by the ITRS. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic (direct tunneling) and extrinsic (SILC) mechanisms. At each technology node, the multilevel approach will increase the memory efficiency, almost doubling the density at the same chip size, enlarging the application range, and reducing the cost per bit. REFERENCES [1] S. Lai, Flash memories: Where we were and where we are going, in IEDM Tech. Dig., 1998, pp [2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Flash memory cells An overview, Proc. IEEE, vol. 85, pp , Aug [3] P. Pavan and R. Bez, The industry standard Flash memory cell, in Flash Memories, P. Cappelletti et al., Ed. Norwell, MA: Kluwer, [4] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, New ultra high density EPROM and Flash with NAND structure cell, in IEDM Tech. Dig., 1987, pp [5] S. Aritome, Advance Flash memory technology and trends for file storage application, in IEDM Tech Dig., 2000, pp [6] D. Frohman-Bentchkowsky, Memory behavior in a floating-gate avalanche-injection MOS (FAMOS) structure, Appl. Phys. Lett., vol. 18, pp , [7], FAMOS A new semiconductor charge storage device, Solid State Electron., vol. 17, pp , [8] S. Mukherjee, T. Chang, R. Pang, M. Knecht, and D. Hu, A single transistor EEPROM cell and its implementation in a 512 K CMOS EEPROM, in IEDM Tech. Dig., 1985, pp [9] V. N. Kynett, A. Baker, M. Fandrich, G. Hoekstra, O. Jungroth, J. Kreifels, and S. Wells, An in-system reprogrammable 256 K CMOS Flash memory2, in ISSCC Conf. Proc., 1988, pp [10] Webfeet Inc., Semiconductor industry outlook, presented at the 2002 Non-Volatile Memory Conference, Santa Clara, CA. [11] L. Selmi and C. Fiegna, Physical aspects of cell operation and reliability, in Flash Memories, P. Cappelletti et al., Ed. Norwell, MA: Kluwer, [12] G. Casagrande, Flash memory testing, in Flash Memories, P. Cappelletti et al., Ed. Norwell, MA: Kluwer, [13] P. Cappelletti and A. Modelli, Flash memory reliability, in Flash Memories, P. Cappelletti et al., Ed. Norwell, MA: Kluwer, [14] K. Yoshikawa, S. Yamada, J. Miyamoto, T. Suzuki, M. Oshikiri, E. Obi, Y. Hiura, K. Yamada, Y. Ohshima, and S. Atsumi, Comparison of current Flash EEPROM erasing methods: Stability and how to control, in IEDM Tech. Dig., 1992, pp [15] S. Maramatsu, T. Kubota, N. Nishio, H. Shirai, M. Matsuo, N. Kodama, M. Horikawa, S. Saito, K. Arai, and T. Okazawa, The solution of over-erase problem controlling poly-si grain size Modified scaling principles for Flash memory, in IEDM Tech. Dig., 1994, pp [16] C. Dunn, C. Kay, T. Lewis, T. Strauss, J. Screck, P. Hefley, M. Middendorf, and T. San, Flash EEPROM disturb mechanism, in Proc. Int. Rel. Phys. Symp., 1994, pp [17] G. Crisenza, G. Ghidini, S. Manzini, A. Modelli, and M. Tosi, Charge loss in EPROM due to ion generation and transport in interlevel dielectrics, in IEDM Tech. Dig., 1990, pp [18] G. Crisenza, C. Clementi, G. Ghidini, and M. Tosi, Floating gate memories, Qual. Reliab. Eng. Int., vol. 8, pp , [19] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, Failure mechanisms of Flash cell in program/erase cycling, in IEDM Tech. Dig., 1994, pp [20] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, Statistical model of reliability and scaling projections for Flash memories, in IEDM Tech. Dig., 2001, pp [21] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti, New technique for fast characterization of SILC distribution in Flash arrays, in Proc. IRPS, 2001, pp [22] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, Localization of SILC in Flash memories after program/erase cycling, in Proc. IRPS, 2002, pp [23] A. Modelli, Reliability of thin dielectrics for nonvolatile applications, Microelectron. Eng., vol. 48, pp , [24] B. Riccò, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanari, and A. Modelli, Nonvolatile multilevel memories for digital applications, Proc. IEEE, vol. 86, pp , Dec [25] A. Modelli, R. Bez, and A. Visconti, Multi-level Flash memory technology, in 2001 Int. Conf. Solid State Devices and Materials (SSDM), Tokyo, Japan, 2001, pp [26] C. Calligaro, A. Manstretta, A. Modelli, and G. Torelli, Technological and design constraints for multilevel Flash memories, in Proc. 3rd IEEE Int. Conf. Electronics, Circuits, and Systems, 1996, pp [27] T. C. Ong et al., Erratic erase in ETOXTM Flash memory array, in Tech. Dig. VLSI Symp. Technology, vol. 7A-2, 1993, pp [28] A. Chimenton, P. Pellati, and P. Olivo, Analysis of erratic bits in FLASH memories, in Proc. IRPS, 2001, pp [29] G. Campardo et al., 40-mm 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory, IEEE J. Solid-State Circuits, vol. 35, pp , Nov [30] H. P. Belgal et al., A new reliability model for post-cycling charge retention of Flash memories, in Proc. IRPS, 2002, pp [31] A. Modelli, A. Manstretta, and G. Torelli, Basic feasibility constraints for multilevel CHE-programmed Flash memories, IEEE Trans. Electron Devices, vol. 48, pp , Sept [32] International Technology Roadmap for Semiconductors, 2001 ed. [33] S. Keeney, A 130 nm generation high-density ETOX Flash memory technology, in IEDM Tech. Dig., 2001, pp BEZ et al.: INTRODUCTION TO FLASH MEMORY 501

14 Roberto Bez was born in Milan, Italy, in He received the Ph.D. degree in physics from the University of Milan in In 1986, he joined the VLSI Process Development Group of STMicroelectronics, Agrate Brianza, Italy, where he worked on nonvolatile memory process architectures. Until 1989, he was engaged in the electrical characterization and modeling of nonvolatile memory cells, contributing to the development of original device models. From 1989 to 1993 his work focused on the development of Flash memory, studying the device physics related to the programming/erasing mechanisms and participating to the process architecture definition. Then he was Project Leader of the Flash memory device process development for single power supply application from 1994 to 1997, and for multilevel products since Currently, he is Section Manager in the Non-Volatile Memory Process Development Group of the Central Research and Development Department of STMicroelectronics. He has authored many papers, conference contributions, and patents on topics related to nonvolatile memories. He was lecturer in Electron Device Physics at the University of Milan and in Non-Volatile Memory Devices at the University of Padova and Polytechnic of Milan. He is a member of the Symposium on VLSI Technology Technical Program Committee. Alberto Modelli was born in Milan, Italy, in He received the Ph.D. degree in physics from the University of Milan in In 1978, he joined the Device Physics Laboratory of the Research and Development Department, STMicroelectronics, Agrate Brianza, Italy, where he initially worked on the development of silicon solar cells and later on the physics and electrical characterization of the Si/SiO2 system. In 1994, he joined the Non-Volatile Memory Process Development Group of STMicroelectronics, where he has been working on the reliability of flash memories. Since 1996, he has been in charge of multilevel flash development. He is author or coauthor of over 40 publications, one book, and five patents on the above-mentioned topics. Emilio Camerlenghi was born in Bergamo, Italy, in He received the Ph.D. degree in physics (curriculum in solid state physics) from the University of Milan, Milan, Italy, in In 1985, he joined the Central Research and Development Department, VLSI Process Development Group of STMicroelectronics, Agrate Brianza, Italy, working on nonvolatile memories process architectures. Until 1989, he was engaged in development of the 1.2-m EPROM technology, with the main objective of studying the memory cell hot-electron programming physics and developing the memory cell device. From 1990 to 1992, he became responsible of the development of the new generation 0.6-m EPROM process architecture. In 1992, he joined the Flash development team, where he was Project Leader of the 0.6-m Flash technology, designed to realize both double (5 12 V) and single (5 V only) power supply devices. In 1995, he was in charge of leading the ST part of an advanced project (a codevelopment between STM and a U.S. company) whose target was to demonstrate the functionality of an innovative Flash memory virtual-ground architectural concept. In the years, he was appointed to lead the development of the 0.25-m Flash process architecture for low-voltage power supply applications. Since 1998, he has been Section Manager of High Performance Flash Memory in the Non-Volatile Memory Process Development Group of the Central Research and Development Department, STMicroelectronics; under his responsibility, the 0.18-m, 0.15-m generations were developed and qualified, while the 0.13-m technology is at present in the qualification phase. He has authored many conference papers and patents on nonvolatile memory related topics. He is currently a member of the IEDM conference subcommittee on Integrated Circuits and Manufacturing. Angelo Visconti was born in Como, Italy, in He received the Ph.D. degree in physics, cum laude, from the University of Milan, Como, in His thesis was on the feasibility of optical temporal solitons in quadratic nonlinear materials. Beginning in 1987, he worked for ten years as a hardware and software designer and project leader for industrial automation systems. In 1997, he joined the Central Research and Development Department of STMicroelectronics, Agrate Brianza, Italy, in the Non-Volatile Memory Process Development Group. His first activities were about the study and characterization of channel erase and programming currents in Flash cells. Afterward, he was involved in the development of a 0.18-m CMOS high-density Flash memory process. His interests are the characterization, reliability, and multilevel applications of Flash cells. He is author or coauthor of several publications and patents in the nonvolatile memory field and nonlinear optical field. He is currently a Lecturer of Non-Volatile Memory Devices at the University of Padova, Padova, Italy. 502 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

15 Program Schemes for Multilevel Flash Memories MARCO GROSSI, MASSIMO LANZONI, AND BRUNO RICCÒ, FELLOW, IEEE Invited Paper This paper presents a synthetic overview of multilevel (ML) Flash memory program methods. The problem of increasing program time with the number of bits stored in each cell is discussed and methods based on both channel hot electrons (CHE) and Fowler Nordheim tunneling (FNT) will be discussed. In the case of CHE, the use of an increasing voltage rather than a constant one on the control gate (CG) leads to narrower threshold voltage distributions and smaller current absortion, with positive effects on degree of parallelism and program throughput. As for FNT, much faster programming than those commonly used today can be done using high CG voltages without producing intolerable degradation of cell reliability. Keywords Flash, memories, multilevel, programming. I. INTRODUCTION Emerging new applications for Flash memories (e.g., audio and video storage) have highly increased the demand for high-density, low-cost memories. In this context, multilevel (ML) storage [1] allows to memorize more than one bit in each cell, thus offering significant cost per bit reduction for the same cell dimension. ML storage, however, implies more critical constraints in terms of program and sensing accuracy, charge retention, read and write disturbs. In particular, accurate programming requires the placement of the right amount of charge on the cell floating gate (FG) to produce tight threshold voltage ( ) distributions. If denotes the number of bits per cell, 2 such distributions, adequately separated from each other, must cover a total voltage window (TVW) (in pratice the difference between the highest and the lowest value of ) that tends to shrink with new technologies aimed at low-voltage operations. Accurate charge placement is normally obtained by means of program and verify (P&V) algorithms featuring a sequence of small steps, each followed by a read operation Manuscript received July 1, 2002; revised January 5, The authors are with the Department of Electronics, Computer Science, and Systems, University of Bologna, Bologna, Italy ( [email protected]). Digital Object Identifier /JPROC to determine whether or not further programming is to be made. This approach obviously leads to the required accuracy, provided that the individual program steps are small enough. On the other hand, precision is heavily paid for in terms of program throughput (PT), i.e., number of bits that can be programmed per second, since the number of P&V steps increases with decreasing distribution widths. This, of course is particularly true for increasing values of (3,4, ), since the width of the distribution decreases essentially as 2 (for the same TVW). In spite of these problems, ML programming with 2 b/cell in both NOR [2], [3] and NAND [4], [5] technology is already a reality, while a substantial research effort is dedicated at the cases with 3 and 4. As for architectures, the NOR solution has been so far the mainstream Flash technology since: 1) it allows one to program cells by both channel hot electrons (CHE) and Fowler Nordheim tunneling (FNT); and 2) the absence of serial connected cells allows faster programming and reading and avoids write disturbs (seriously affecting the NAND case). On the other hand, the NAND solution is gaining increasing interest due to: 1) its more compact layout (leading to higher memory density and lower cost per bit); and 2) the possibility to use very low (or even negative) values, thus effectively eliminating the problem of overerased cells and the consequent need of erase and verify algorithm. A symmetrical problem exists in NAND memories for overprogramming. Since unselected cells become pass transistors, if a cell is too high, this can prevent it from turning on. The problem is, however, less important than overerase in ML memories, since high accuracy in programming must be guaranteed either in NOR or NAND architecture to allow many levels to be stored in the same TVW. In the case of a NOR Flash memory, Fig. 1 illustrates the distributions required for 4, 8, and 16 levels, respectively. The needs to avoid read disturbs due to excessively low values as well as undesired programming of low cells during reading impose a minimum and maximum value, thus effectively determining the TVW /03$ IEEE 594 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

16 (a) (b) Fig. 1. V distributions for ML programming of NOR Flash memory in a TVW of 4.5 V. (a) Four-level programming. (b) Eight-level programming. (c) 16-level programming. (c) In the case of Fig. 1, where a TVW of 4.5 V is considered, the maximum gate voltage ( ) applied during reading is 5.25, 5.4, and 5.85 V for 4, 8, and 16 levels, respectively. In the NAND architecture, Fig. 2 illustrates the distributions for the eight-level NAND memory discussed in [5]: the distributions are well separated (0.4 V), and, although the maximum applied to nonselected word-lines in reading is 6 V (a trade-off between fast reading and device reliability), a reliable and efficient device is achieved. 2) FNT: electrons are injected into the FG by tunneling due to the high vertical electric field. Compared with FNT, CHE requires lower voltages, with benefits for the driving circuitry and device reliability, but is also characterized by large current absortion that limits the degree of parallelism (DOP) and is problematic for lowpower applications. In the following sections, program methods for both CHE and FNT are synthetically discussed. II. MULTILEVEL PROGRAM METHODS Flash memory programming is achieved by injecting electrons into the FG. This can be obtained by means of two different physical mechanisms. 1) CHE: electrons in the channel of the cell MOSFET gain enough energy by the driving electric field to be injected into the FG (helped by the vertical electric field, essentially due to ). III. CHANNEL HOT ELECTRONS NOR Flash memories can be programmed by CHE using two different techniques: 1) conventional box programming; and 2) ramped voltage programming. In the former method, a constant voltage is applied on the CG during the whole operation, while in the latter is raised linearly during programming. GROSSI et al.: PROGRAM SCHEMES FOR MULTILEVEL FLASH MEMORIES 595

17 Fig. 2. Target V distributions for eight-level NAND Flash memory. The picture is taken from [5]. The FG voltage ( ) and the injection current into the FG ( ) are linked by the following equation [6]: (1) where is the FG to CG capacitance; is the FG to drain capacitance; and is the total capacitance between FG and the other MOSFET regions. In conventional box programming,, thus. Since decreases with decreasing, both the programming speed ( ) and are high at the beginning of programming, but decrease with program time and reach a low value at the end of the operation, as schematically illustrated in Fig. 3(a) [6]. This behavior represents a problem because high values of (hence of ) limit the DOP, thus the PT. Moreover, strong nonuniformities of produce high dispersion in programmed, hence (relatively) wide distributions. With ramped voltage programming instead, is constant (hereafter, is the slope of the gate bias waveform) and ; thus,. If the initial value of the ramp applied to CG is set so that, the write operation takes place under equilibrium conditions ( ), where both and are constant, as schematically illustrated in Fig. 3(b) [6]. Qualitative waveforms of and for ramped voltage programming are sketched in Fig. 4(a) [6], while Fig. 4(b) [6] shows the expected transient behavior of and (here, denotes the time necessary to reach the equilibrium condition ). In Fig. 4(c) [6], the expected waveforms for and are schematically described. As already mentioned, constant helps to maximize DOP, hence PT. Furthermore, the linear relationship between programmed and program time produces a better accuracy in programming, hence, tighter distributions. distribution widths obtained with ramped voltage programming depend on programming conditions, i.e., drain and substrate bias ( and, respectively) as well as on. Fig. 5 shows the standard deviation ( ) of the programmed distribution measured on 10 K cells as a function of, for different values of and. For all considered bias configurations, the minimum is obtained at low program speeds (low ) and increases with. Thus, a tradeoff is in order between high program speeds and good accuracy in achieving the final value. From this point of view, the ramped voltage programming technique has been shown to be able to program a Flash memory array on four levels (2 b/cell) without the need of P&V algorithms [7], with substantial benefits of PT. In particular, assuming the same DOP (256), the method of [7] results in a 0.8 MB s, instead of 0.17 MB/s achieved in [2]. The obtained distributions are well separated, and the minimum read margin (i.e., the difference between the cell and the gate bias used in reading) is 0.4 V. Also, after 20 K program/erase (P/E) cycles, the read margin does not degrade much; thus, the reliability constraints for the memory are guaranteed. However, programming the memory on eight or more levels without P&V algorithms requires a significant increase in TVW that is not compatible with desirable circuit specification. On the other hand, the use of ramped voltage programming in conjunction with P&V is problematic, because before each program step the exact value of cell must be determined in order to set the correct initial value of. Since determination is a time-consuming operation, 596 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

18 Fig. 3. Conceptual plots of V _ as a function of the FG voltage V and corresponding typical behavior of V during programming operation where the CG has (a) a box waveform or (b) a ramp waveform. ramped voltage programming with P&V is more convenient than conventional box programming only if a minimum number of verifications is used. A new programming method that combines ramped voltage programming with verify operations is described in [8]. With this algorithm, programming is performed using only two steps, each precedeed by a determination. In detail, and with reference to Fig. 6, the program algorithm consists of the following steps. First, the initial value ( ) of the cell is determined. Second, the cell is programmed from to an intermediate target value ( ) using a ramped CG voltage with slope and the same overdrive ( ) for all cells. Third, the obtained value ( )of after this program step is determined. Fourth, the cell is programmed from to the final value with a CG voltage of slope and overdrive, where. The determination of guarantees quasi-equilibrium conditions during the first program operation, thus avoiding initial high current absortion and loss of accuracy. The determination of, instead, allows one to adjust the program overdrive to account for the characteristics of each individual cell, and represents the essential element to obtain adequate program accuracy. The algorithm is capable of achieving distribution widths and displacement of the distribution mean value from the targets smaller than 150 and 20 mv, respectively. This method is adequate for 3 b/cell ML schemes while, for the case of 4 b/cell, the separation between distribution is probably insufficient for direct use in real memories, although the adoption of error correcting codes makes it possible to use it also for 16-level schemes. The achieved program time is six times lower than that obtained with the algorithm of [2] for 4 b/cell at cell level (70.75 instead of 400 s) that, with a cell matrix scheme featuring DOP 256 and parallel analog determination of cells, results in a PT about three times larger (0.9 instead of 0.32 MB/s). IV. FOWLER NORDHEIM TUNNELING Compared with CHE, this programming method has the advantage of small current absortion, particularly interesting for low-power applications. Moreover, it allows very high GROSSI et al.: PROGRAM SCHEMES FOR MULTILEVEL FLASH MEMORIES 597

19 Fig. 4. (a) Qualitative waveforms of the CG and drain voltages for ramped voltage programming scheme as well as corresponding behavior of (b) V, I and (c) V, I. Fig. 5. Dependence of on V for 10 K cells at different V and V. BWP indicates the for box programming. DOP, thus leading to a strong increase in PT. In this regard, the NAND state of the art (based on FNT programming) produces a PT as high as 10 MB/s [9]. However, as described in [10], FNT has several drawbacks that make it less effective than CHE for ML applications. In particular, programming by tunneling is more sensitive than CHE to process parameters, and this produces wider distributions. Furthermore, the applied voltages are higher than with CHE, and this produces high stress in the oxide, resulting in worse device reliability. In this regard, Fig. 7 shows read disturb time, i.e., the time to produce a 0.5-V shift due to drain stress, as a function of number of P/E cycles [11]. Thus, since the applied voltages cannot be too high, programming currents ( ) are low; this leads to high programming times (in the range of 10 ms as opposite to the few s for CHE programming). To maintain competitive PT, high parallel programming is required, and this leads to high circuit complexity and die-size overhead, although parallel programming for FNT is simpler to implement than for CHE. Compared to CHE, FNT tends to produce wider distributions and higher programming time; thus, efficient P&V algorithms are needed in ML programming to guarantee good program accuracy and PT. In [12], three different P&V algorithms (schematically shown in Fig. 8) are presented for a NAND Flash memory. Fig. 8(a) illustrates the conventional P&V technique where pulses of variable width are applied on the CG, while a verify operation is carried out between two write pulses. The first write pulses are sufficiently short so as to ensure that fast cells will not overprogrammed, then the pulse width is increased to minimize the number of verify steps for slow cells. Fig. 8(b) shows the trapezoidal pulse algorithm that achieves much better results than in Fig. 8(a). Higher programming speed can be obtained, while the oxide electric field ( ) can be reduced. Moreover, programming time increase with distribution width reduction is much weaker than for the previous case. Fig. 8(c) instead shows the staircase pulse algorithm that uses the same approach as in Fig. 8(b) but it is much easier to generate on-chip. In Fig. 9, the main characteristics of both FNT and CHE are compared. Since the advantage of less disturbs and lower electric fields are more important than the large DOP allowed by FNT, CHE seems to be more suitable for ML applications, at least when low power consumption is not the main constraint. Of course, with FNT it is possible to reduce program time ( ) by increasing, thus trading off and device reliability. In this regard, stress-induced leakage current (SILC), degrading data retention time, is the main phenomenon, and it has conventionally been considered to increase with, thus with the decrease of [13] (for the same charge fluence, i.e., total charge injected through the oxide). However, recent studies [14] have shown that, for the same charge fluence, initially SILC increases with decreasing, but it tends to decrease with as the stress time becomes comparable to the characteristic time required for permanent oxide degradation. Fig. 10 shows SILC characteristics of Flash memory cells as a function of and for different program conditions. Fig. 10(a) shows that SILC after a 10 K P/E cycling with 20 ns is not much larger than the one obtained 598 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

20 Fig. 6. Representation of the novel algorithm that combines ramped voltage programming with verify operations. Inside the boxes, the CG voltage during the two program steps is shown. Fig. 7. A comparison between the read disturb due to CHE and FNT programming, as a function of P/E cycles. The picture is taken from [11]. with 30 s. Instead, Fig. 10(b) shows that SILC stops increasing for 1 s and (slightly) decreases with below such a value. This shows that FNT programming of Flash memory with as low as 20 ns is feasible, with good results in term of data retention, provided that sufficiently low during reading is applied. In this regard, in Fig. 11 the maximum read disturb voltage ( ) compatible with a data retention time of ten years after 10 K P/E cycles is shown as a function of.for as low as 20 ns, this maximum value is about 2.5 V. However, a significant problem for FNT is due to the high voltages needed for fast programming [in the case of Fig. 10(a), for 20 ns, it is 26.5 V], since this leads to challenging constraints for the high-voltage programming circuit. Scaling the oxide thickness has favorable effects because it decreases the values of for the same oxide field, but also produces a drastic decrease in data retention time. In [15], measurements performed on 6.5-nm oxide Flash memories have shown a data retention time of 13 hours after 10 K P/E cycles with a maximum of 2.5 V during reading. Such a retention time is small compared to the ten-year retention of conventional nonvolatile memories, but it is more than three orders of magnitude greater than typical DRAM refresh time, thus making fast FNT potentially interesting for DRAM-like applications. GROSSI et al.: PROGRAM SCHEMES FOR MULTILEVEL FLASH MEMORIES 599

21 Fig. 8. Conventional (a), trapezoidal (b), and staircase (c) programming pulses. A verify step is carried out after each pulse. The picture is taken from [12]. Fig. 10. SILC characteristics of the Flash memory cells after 10 K P/E cycling (a) as a function of F for different program conditions and (b) as a function of T. Fig. 9. Comparison of FNT and CHE programming mechanisms for ML applications. The picture is taken from[11]. V. CONCLUSION This paper has presented a synthetic review of different program techniques for ML Flash memories based both on CHE injection and FNT. In the case of CHE, ramped voltage programming has been shown able to achieve tighter distributions and higher program throughput than the conventional box techniques. In fact, programming on four levels is feasible without the use of P&V algorithms. Instead, with 8 or 16 levels, P&V is mandatory and problems are in order because of the difficulty of conjugating ramped voltage programming and verify operations. In the case of FNT, instead, fast programming with pulse duration of 20 ns seems able to produce very high PT (comparable with DRAMs). However, problems occur because of need to use high-voltage circuitry and/or the reduction of data retention time due to decreased tunnel oxide thickness. For these reasons, fast FNT seems more suitable for DRAM-like applications than conventional nonvolatile memories. Fig. 11. Maximum read disturb voltage V which still guarantees a data retention time of 10 years versus T after 10 K P/E cycles. REFERENCES [1] B. Riccò, G. Torelli, M. Lanzoni, A. Manstretta, H. Maes, D. Montanari, and A. Modelli, Nonvolatile multilevel memories for digital applications, Proc. IEEE, vol. 86, pp , Dec [2] A. Silvagni, S. Zanardi, A. Manstretta, and M. Scotti, Modular architecture for a family of multilevel 256/192/128/64 mbit 2-bit/cell 3 v only NOR Flash memory devices, IEEE Trans. Electron Devices, vol. 48, pp , Jan [3] M. Bauer, A multilevel-cell 32 Mb Flash memory, in IEEE ISSCC Tech. Dig., 1995, pp [4] T.-S. Jung, Y.-J. Choi, and K.-D. Suh, A 117 mm 3.3 v only 128 mb multilevel NAND Flash memory for mass storage applications, IEEE J. Solid-State Circuits, vol. 31, pp , Nov PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

22 [5] H. Nobukata, S. Takagi, and K. Hiraga, A 144-Mb, eight-level NAND Flash memory with optimized pulsewidth programming, IEEE J. Solid-State Circuits, vol. 35, pp , May [6] D. Esseni, A. D. Strada, P. Cappelletti, and B. Riccò, A new and flexible scheme for hot-electron programming of nonvolatile memory cells, IEEE Trans. Electron Devices, vol. 46, pp , Jan [7] R. Versari, D. Esseni, G. Falavigna, M. Lanzoni, and B. Riccò, Optimized programming of multilevel Flash EEPROMs, IEEE Trans. Electron Devices, vol. 48, pp , Aug [8] M. Grossi, M. Lanzoni, and B. Riccò, A novel algorithm for high throughput programming of multi-level Flash memories, IEEE Trans. Electron Devices., submitted for publication. [9] H. Nakamura, K. Imamiya, and T. Himeno, A 125 mm 1Gb NAND Flash memory with lomb/s program throughput, in IEEE ISSCC Tech. Dig., vol. 1, 2002, pp [10] B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, and A. Modelli, Multilevel Flash cells and their trade-offs, in IEEE IEDM Tech. Dig., 1996, pp [11] B. Eitan and A. Roy, Binary and multilevel Flash cells, in Flash Memories, P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Eds. Boston, MA: Kluwer, 1999, pp [12] G. Hemink, T. Tanaka, and T. Endoh, Fast and accurate programming method for multi-level NAND EEPROM s, in Symp. VLSI Technology Dig. Tech. Papers, 1995, pp [13] R. Moazzami and C. Hu, Stress-induced current in thin silicon dioxide film, in IEEE IEDM Tech. Dig., 1992, pp [14] R. Versari, A. Pieracci, D. Morigi, and B. Riccò, Fast tunneling programming of nonvolatile memories, IEEE Trans. Electron Devices, pp , June [15] R. Versari, A. Pieracci, and B. Riccò, Fast programming/erasing of thin-oxide EEPROMs, IEEE Trans. Electron Devices, pp , Apr gate technique. Marco Grossi was born in Bologna, Italy, in He received the Laurea degree in electronic engineering from the University of Bolognain He is currently working toward the Ph.D. degree at the Department of Electronics, Computer Science, and Systems Laboratory, University of Bologna. His research interest is characterization of nonvolatile memories. He is currently working in the field of Flash memories and the multilevel programming of these memories using the ramped Massimo Lanzoni was born in Bologna, Italy, in He received the Laurea degree in electronic engineering from the University of Bologna, Bologna, Italy, in He is with the Microelectronics Research Group, Department of Electronics, Computer Science, and Systems, University of Bologna, working on research projects in the fields of nonvolatile memories, MOS devices, virtual instrumentation, and testing. His research interests include the characterization of thin dielectrics reliability, nonvolatile memory cell characteristics and reliability, MOS transistors experimental characterization and new techniques for IC testing as nonvolatile memories endurance testing and CMOS IC latch-up testing. He is now involved in projects concerning analog applications of nonvolatile memories and multilevel programming. Bruno Riccò (Fellow, IEEE) was born in Parma, Italy, in He received the Laurea degree in electrical engineering from the University of Bologna, Bologna, Italy, in 1971 and the Ph.D. degree from the University of Cambridge, Cambridge, U.K., in 1976, where he worked at the Cavendish Laboratory. In 1980, he was a Full Professor of Electronics at the University of Padova, Padova, Italy. In 1983, he was a Full Professor of Electronics at the University of Bologna. In 1983 and 1986, he was Visiting Professor at the University of Stanford, Stanford, CA; at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY; and at the University of Washington, Seattle. He is currently with the Department of Electronics, Computer Science, and Systems, University of Bologna. He has also been a Consultant for major companies and for the Commission of the European Union in the definition, evaluation, and review of research projects in microelectronics. He is author or coauthor of more than 300 publications (more than half of which have been published in major international journals), three books, and six patents in the field of nonvolatile memories. His research interests include solid-state devices and ICs. He is currently also working in the field of IC design, evaluation, and testing. Prof. Riccò has been President of the Group of Electron Devices, Technologies, and Circuits of the Italian Association of Electrical and Electronics Engineers (AEI) since 1996, and was President of the Italian Group of Electronics Engineers from 1998 to In 1996, he recieved the G. Marconi Award from the AEI. He was European Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES from 1986 to 1996, European Cochair at the International Electron Device Meeting (IEDM) from 1992 to 2001, and Vice- Chairman of the North Italy Section of IEEE from 1999 to He has been Chairman of the IEEE North Italy since GROSSI et al.: PROGRAM SCHEMES FOR MULTILEVEL FLASH MEMORIES 601

23 Status and Outlook of Emerging Nonvolatile Memory Technologies Gerhard Muller, Thomas Happ, Michael Kund, Gill Yong Lee, Nicolas Nagel, and Recai Sezi Infineon Technologies AG MP TD NMP, PO Box 80949,81609 Munich, Germany Abstract This paper reviews the concept, status and challenges of emerging nonvolatile memory technologies. The technologies that are discussed and compared to state of the art Flash technology are the Conductive Bridging RAM (CBRAM), the Ferro-electric RAM (FeRAM), the Magneto-resistive RAM (MRAM), the Organic RAM (ORAM) and the Phase Change RAM (PCRAM). CBRAM data retention has been measured at elevated temperatures (Fig. 2). A slight increase of the low resistance state could be observed, whereas the ROFF values remain constant resulting in a resistance ratio >IO' even after 10 years. CBRAM The CBRAM memory effect is based on a polarity-dependent, resistive switching at a low write threshold voltage Vth of 250mV with typically 2pA write current and an erase voltage threshold of -8OmV. The ON-state (low resistance) of a CBRAM memory cell is achieved after a redox reaction driving metal ions in the chalcogenide glass forming metal-rich clusters that lead to a conductive bridge between the electrodes. The memory element can be switched back to the OFF-state by applying a reverse bias voltage. In this case metal ions are removed and due to that size and number of metal-rich clusters are reduced resulting in an erased conductive bridge (resistance increase). Scalability of the CBRAM technology from 5pm down to l0onm has been demonstrated [l]. As a result the threshold voltage Vth and the ON-state resistance Ron were observed to be feature size independent, whereas the OFF-state resistance ROFF shows the expected dependency up to the resolution limit of 10"Ohm (Fig. I). U) T - 25% ilarea storage material [i~pm'] Fig.1 CBRAM cell resistance and threshold voltage as a function of storage material area. 0.5 IE+O dl, It 7 ' 1oy 1E41 1E+01 1E+03 1E+05 1E+07 1E+09 Time [SI Fig.2 CBRAM data retention measured at elevatedtemperatures. FeRAM FeRAM stores data as remnant polarization in a ferroelectric capacitor. Fig. 3 shows an SEM cross section of a state of the art planar FeRAM cell, used in a 32Mb FeRAM with a cell size of l.9pm2. [2]. Key technology ingredients are the chain FeRAM concept and the COP structure (capacitor on plug). Fig.3 32Mb Chain FeRAM cell with COP (capacitor over plug). Planar FeRAM cell concepts are limited to cell sizes around 10F2 (F: minimum feature size) (Fig. 4) and have a limited shrinkability potential. In order to address this, a novel chain FeRAM cell concept using a new 3 dimensional vertical capacitor was developed [2]. This concept is highly scalable and enables structurally small cells down to 4F2. The 3d vertical capacitor cell saves the space of the VO contact and the cell size is not defined mainly by the capacitor area. A hysteresis loop of a vertical capacitor is shown in Fig /04/$ IEEE IEDM

24 ~ Fig.4 Tap: Advanced planar FeRAM cell: &c.li=!9.75f' Bottom: Advanced vertical capacitor cell: A,a=4F' without corrosion. This customized full stack etch process provides magnetic tunnel junction (MTJ) patterning with a local cell resistance spread of -2%. The magnetoresistance (MR), the important figure of merit for the READ operation, has been limited to - 70%. Higher MR would increase the read operation margin and enable very small MTJs that are essential for scalability. Within our MRAM Alliance with IBM, we pioneered the development of tunnel junctions with 100 bcc textured MgO tunnel barriers and achieved MRs as high as 220% [3]. Fig. 7 shows a resistance versus field characteristic for a tunnel junction of this type, with this example showing a MR of 165% 4% 0 4w OFCmcaI nsld Wlml Fig.5 Hysteresis loop from a vertical capacitor with Ir02 electrodes. MRAM In MRAMs the data is stored in the orientation of the magnetization of the storage layer. As for many other BEOL memory technologies 2 cell flavours are possible, a cross point cell and the FET cell, which has an access transistor connected in series with the tunnel junction. The highest published MUM chip density of 16Mb was accomplished with the FET cell [3] with a 1.4pm' cell size. Since the XPC does not require an access device the cell size can he smaller especially because one can stack storage layers on top of each other. However, in order to control parasitic currents and the write operating margin, higher tunnel resistances are required than for the FET cell, resulting in slower random access times. Field (Oe) Fig. 7 Tunnelling magnetoresistance of MgO MTJ stack, TaN lrmn 1 CoSFej6 I Co,,Felo i MgO I CoslFela i Mg, annealed at three different temperawes (left). Cross-sectional TEM image illustrating the highly texhmd nanre of the MgO tunnel barrier (right). ORAM The data in the ORAM is stored in an organic storage material that exhibits reversible resistive switching (Fig. 8). Via tilled wf,/ storage mat 8-1 Fig.8 Schematic view of ORAM cell and IV c we. Reversible wle operation by voltage application, read operation by determination of the highilow conductance state. With cell structures > 1x2pm2 size a retention of >400 days@25" C, extrapolated retention of 10 years@90" C and an endurance of les w/e cycles was demonstrated [4]. Fig. 9 and Fig. IO address the scalability prospects ofthis technology. 1, Fig. 6 M UM cross point cell realization In XPC MRAM (Fig. 6), the magnetic stack is deposited directly on Cu wires, and then pattemed using a single step reactive ion etching process, requiring stopping on Cu and ILD io2 10 i " Area of storage material [pm21 Fig.9 Effect of storage material area on resistance values at T=25T. Extrapolation indicates a resistance ratio of >IO at an area of20x20nm IEDM

25 ~~.. ~ ~..._._. ~ Area of storage material &m2] Fig. 10 Effect of storage material area on switching voltages (quasi static experiment at 25-C). Extrapolation indicates a sufficient large resistance ratio ROFF/RON down to a storage material area of 20x20nm2. The switching voltages are independent of the diameter of the storage material. Very first promising distribution functions for Vth are displayed in Fig. 11. Main challenges for this technology will he the uniformity on large areas and the thermal budget. maintaining sufficient Write operating margin and themal cross talk for dense PCRAM arrays. In order to address these concems, the reset operation was modelled using a finite element approach. Fig. 13 compares the currents required to melt the GST for different geometries and bottom electrode contact sizes. For all cell designs, the current scales down with decreasing feature size. However, the heater cell exhibits significantly higher reset currents due to lateral current spreading. rmo I Bonom electlode contad size (nm) Fig. 13 Simulated PCRAM reset current dependence an contact size. Vth (VI Fig.] 1 Switching threshold voltage (Vth) distribution functions determined for 50 cells with a via size of 240nm. via diameterd: 140 nm PCRAM The PCRAM is based on a thermally induced reversible phase change between the amorphous and the crystalline phase of a chalcogenide glass (Ge,Sh,Te,) which is initiated by ohmic hea :with an electric current pulse (Fig. 12) [51 E P 5m 4m Normal=& 40nm rads1 distance (OF1 Fig.14 Simulated radial temperature distribution normalized to the via diameter in active-in-via PCRAM cells after 20"s hcating. The vertical line indicates the closest position of the next cell in a denre 4F' array. The horizontal. line indicates the IOa retention criterion for GST material. The simulation also shows that the heat plume scales down with the via diameter (Fig. 14). The highest published PCRAM chip density is 64Mb with a cell size of 0.5 pm2 cell size [5]. Conclusions Fig.12 Schematics of different PCRAM resistor geometries with GeSbTe (CST) phase change material: heater cell, active-in-via cell and V-cell (top dawn). In a set-read-reset-read cycle, the set pulse crystallizes the GST while reset melts and transforms it into the high resistance amorphous state. Potential concerns for this technology are reducing the reset current in order to obtain structurally small cell sizes while Tab. 1 compares the discussed emerging memory technologies to Flash technology [6]. All technologies are non-volatile. All of the emerging memory technologies exhibit a better READ performance than NAND Flash. Flash requires for writing the first bit into the memory many orders of magnitudes longer than the emerging technologies. For FeRAM, MRAM and PCRAM, which are the most widely pursued non-volatile emerging memory technologies, a substantially better WRITE IEDM

26 endurance was demonstrated. With the exception of ORAM all other discussed emerging memory technologies do not require a boosted voltage for the WRITE operation as Flash does. In case of the FeRAM technology the READ operation is destructive, meaning that after every READ operation the information has to be written back into the cell. The more mature emerging memory technologies, FeRAM, MRAM and PCRAM have comparable properties, with MRAM having a performance advantage, FeRAM having a maturity advantage and PCRAM having a cell size advantage. They all could he used as universal memories, based on their non-volatility, READiWrite performance and high endurance. In order to not just occupy a niche market but to gain a substantial share of the overall memory market, the challenge for all of them is closing the cell size gap to the established memory technologies, Flash and DRAM. Acknowledgements References (1) R. Symanczyk et al., "Electrical Characterization of Solid Slate Ionic Memory Elements", NVMTS Tech. Dig., 2003, p (2) N. Nagel et al., "New Highly Scalable 3 Dimensional Chain FeFL4M Cell with Vertical Capacitor", VLSI Tech. Dig., 2004, p. 146, H. Kanaya et al., "A 0.602pm' Nestled Chain Cell SfNChlR Formed by One Mask Etching Process for 64Mbit FeRAM, VLSl Tech. Dig., 2004, p (3) A.R. Sitaram et al., "A 0.18pm Logic-based MUM Technology for High Performance Nonvolatile Memory Applications", VLSl Tech. Dig., 2003, p. 15, J. DeBrosse et al., "A 16Mb MRAM Featuring Bootstrapped Write Drivers", VLSl Circ. Dig., 2004, p. 454, S.S.P. Parkin et al., "Giant Tunneling Magnetoresistance at Room Temperature with MgO (100) Tunnel Barriers", Nature Materials, 2004, in press. (4) R. Sezi et al., "Organic Materials for High-Density Non-Valatile Memory Applications", IEDM Tech. Dig., 2003, p (5) S. Lai, "Current Status of Phase Change Memory and its Fuhue'', IEDM Tech. Dig., 2003, p. 256, S. H. Lee et al., "Full Integration and Cell Characteristics for 64Mb Nonvolatile PRAM", VLSI Tech. Dig., 2004, p. 20. (6) D. Elmhurst et al., "A 1.8V 128Mb Mulilevel Cell Flash Memory with Flexible Read While Write", IEEE Journal of Solid-State Cire., Vol. 38, Noll, 2003, p The authors would like to thank the members of the IBM- Infineon MRAM development alliance, the Infineon-Toshiba FeRAM development alliance and the team members of the CBRAM, ORAM and PCRAM projects for their respective contributions. Tab.1 Comparison of the emerging memory technologies to Flash technology. Flash CBRAM FeRAM MRAM I I I - Maturity I Higdlz!:r I Single Cells I Niche Products IProduct Samples Densi W I 4Gb I I 32!Mb I 16Mb cd sir. rllm'l I n~n2r. I I np. I l A Embeddability I Yes I Yes I Yes I Yes Nonvolatile I Yes Yes Yes Yes I 80ns/Iops I <200ns 5011s 30ns I <200ns I 75ns I 30ns Access Random Write I, era~~~oms, I Access Destructive READ Write Endurance No 106 No >io5 Yes >lo- No 10'5 ORAM I PCRAM I Write Voltage Vdd+-1OV Vdd Vdd Vdd Actrans Systems, ememov-tech., Agilent, Fujitsu, IBM Fujitsu, HaloLSI, Hynix, lnfineon lnfineon Companies Infineon, Intel, Matsushita, Oki Motorola Criteria: IEDM, Macronix, Ramtron NEC sscc, VLSl Motorola, Samsung Renesas oublication during Powerchip, Sanyo Samsung ast 3 years) Renesas I Hitachi, Toshiba Sony Samsung, TI Sandisk, Sony, SST. ST. Toshiba lnfineon Hitachi Intel Macronix Ovonyx Samsung 570-IEDM

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39 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER Scaling of Flash NVRAM to 10 s of nm by Decoupling of Storage From Read/Sense Using Back-Floating Gates Arvind Kumar, Student Member, IEEE, and Sandip Tiwari, Fellow, IEEE Abstract Conventional floating-gate Flash memory structures have limited scalability due to nonscaling of insulators for charge retention and reliability, inefficiency of hot-electron injection processes at nanometer dimensions due to off-equilibrium overshoot effects, poor short-channels effects due to poor electrostatics and large voltages needed at the control/read gate as a result of voltage leveraging. We present and analyze a new nonvolatile memory structure based on back-floating gate, which decouples the read/sensing from storage/programming and thus allows a design with efficient storage and improved injection and short-channel characteristics. This structure can be scaled to dimensions similar to that of high performance transistors, i.e., 10 s of nanometers, without compromising the requirements of insulator thickness. Characteristics of the structure are analyzed using coupled simulation and modeling that employs Monte Carlo simulation for hot carrier analysis and quasistatic calculation for evaluating charge injection and storage. We compare the characteristics of the new structure with conventional structures and their use as memory cell. Index Terms EEPROM, flash memory, hot carriers, nonvolatile memory, semiconductor memories, tunnel devices/effects. I. INTRODUCTION CONVENTIONAL floating-gate Flash memory structures [1], where storage of electrons screens the channel from the control gate, are limited in dimensional scaling for power and speed by: 1) limitations to gate-stack insulator thickness to ensure charge retention; 2) inefficiencies of hot-electron injection processes as dimensions approach many 10 s of nanometers (nm); 3) poor electrostatic control due to nonscaling of insulators; and 4) constraints placed on cell size by processes for isolation and floating gate definition. The injection oxides are conventionally in the 6 12-nm range and the control oxides are typically 15 nm and higher as a compromise between programming, erasure and reliability effects of defect-mediated leakage. This results in programming voltages that are typically 10 V and higher and tunneling times in many 10 s of s when aided by hot carrier injection with 3 5 V of drain voltage. The thick gate stack results in poor electrostatic control that has a strong effect on the subthreshold slope. As device gate lengths scale to smal- Manuscript received June 8, 2002; revisedoctober 18, This work was supported in part by the Semiconductor Research Corporation under Task by the National Science Foundation (NSF) through the Center of Nanoscale Systems, and also by a Shared Research University Equipment Grant from IBM. The authors are with the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY USA ( [email protected]). Digital Object Identifier /TNANO Fig. 1. Electron energy distribution near the drain end for a 100-nm conventional floating gate Flash cell. ler dimensions, the consequences of the poor electrostatic control are egregious. An even stronger effect arises from the overshoot in the hot-carrier region, which leads to poorer injection efficiency into the floating gate region. Together, these limitations lead to limits in scalability of front-floating gate structures in the NOR architecture that is commonly preferred. The issue of carrier injection in a front floating gate memory structure is clarified through Fig. 1, which shows the electron energy distribution near the drain junction for conventional front floatinggatecellforagatelengthof100nmin bulkcmos.these simulations employ the program DAMOCLES [2], which provides a full band self consistent Monte Carlo (MC) solution of the Boltzmann transport equation (BTE) and Poisson equation in two-dimensional geometries. The applied bias voltage for the simulation is 10 V at the gate and 5 V at the drain with source grounded. High hot electron injection efficiency requires hot carriers to have sufficient incident flux in order to transmit efficiently into the floating gate region. However, even with careful field design of the drain junction, a large fraction of the high energy region occurs in the doped drain region. As is evident from Fig. 1, there is a poor injection region overlap between the hot carriers in the channel and the floating gate that will worsen as dimensions shrink. The consequence of this is poor injection efficiency and increasingly longer charging/writing time as dimensions are scaled for the NOR-type front-floatinggate nonvolatile random access memory (NVRAM). This manuscript analyzes a structure where the floating gate is provided on the back of a thin silicon-on-insulator channel. The advantage of this approach is that the floating back-gate X/02$ IEEE

40 248 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002 Fig. 2. Cross-section of a back-floating gate Flash memory cell. can be oversized to increase the overlap in the drain extensions and hence provides efficient injection for NOR-type nonvolatile memory cell. Simultaneously, good electrostatic control of the transistor through scaling of read-gate oxide, etc., occurs and hence good low voltage operation is achieved for read process as well as for charge transport during writing. The difference between the use of charge screening through the floating gate in the two approaches is that the front-floating gate charge screens the induced mobile charge in the channel, while the back-floating gate charge affects the field and the barrier on the back of the channel and thus influences the net effective depletion charge. The ability to make such a structure will also allow fabrication of a transistor with controllable threshold voltage when the back-gate potential is directly controlled, thus simplifying the technology for standalone and embedded memories. (a) II. DEVICE STRUCTURE AND DISCUSSION Fig. 2 shows a cross section of the back-floating gate memory cell. In geometry, it is similar to the various back-plane and double-gate structures [3] [5]. The floating gate, with its limitations on tunneling and control oxide thickness is placed on the back of the thin silicon-on-insulator (SOI) layer. An inversion layer is formed in the thin silicon channel through the doped substrate a control gate. Injection into the floating gate occurs through biasing which raises the energy in the channel w.r.t. that of the floating gate and of the carriers within the channel w.r.t. the lattice, leading to hot-carrier injection similar to that of front-floating gate structures. While our simulations are performed using a positive bias applied to the back substrate with source grounded, a translation in voltage can establish the substrate to be the reference ground. A higher control-gate voltage w.r.t. the source forms the channel and the lower substrate energy causes the injection to take place in the back-floating gate region. One important consequence of choosing such a geometry is that the front gate oxide can now be substantially reduced, appropriate to transistor scaling and the transistor operates at low bias voltage with good short-channel characteristics allowing for efficient read operation. The storage can still be maintained reliable together with improved injection efficiency at smaller length. The placement also alleviates isolation constraints of the front-floating gate structures leading to a smaller memory cell footprint. And, this paper will show that the ability to provide a larger overlap allows good injection efficiency at small length scales. So, this new design allows the gate lengths to be scaled to 10 s of nm dimensions. (b) Fig. 3. (a) V roll-off and (b) subthreshold swing characteristics of an example front-floating gate Flash designed for 100 nm. In accord with the current knowledge of practical limits of reproducibility and processing, for the simulations that we discuss, we have chosen the front gate oxide to be 2 nm, the silicon channel to be 15 nm thick, the back injection oxide to be 6 nm, the back floating gate to be 20 nm thick and the back control oxide to be 10 nm, together with a heavily doped substrate which provides the control gate. Techniques such as that of Yang et al. [4] and Xue et al. [6] can be employed to fabricate these geometries. To emphasize the consequences for electrostatic control, Fig. 3 (front-floating gate) and Fig. 4 (back-floating gate) show threshold voltage roll-off and subthreshold characteristics obtained using drift-diffusion analysis for a variety of gate lengths. The threshold voltage roll-off in front floating gate structures is substantial at 100 nm, while the back floating gate structure maintains good threshold voltage control down to sub 70 nm for this design. The subthreshold swing is a much stronger measure of the electrostatic control and a comparison of the figures shows nearly a factor of 2 5 difference between the two approaches, with strong implications for power and mixed logic-memory applications. Thus, the transistor-oriented attributes, i.e., read and sense-related characteristics of the device show significant improvement at the small scale through the use of a back floating gate.

41 KUMAR AND TIWARI: SCALING OF FLASH NVRAM TO 10 s OF nm 249 Fig. 5. Circuit schematic of an array using the back-floating gate memory in the NOR configuration. (b) Fig. 4. (a) V roll-off and (b) subthreshold swing characteristics of an example back-floating gate Flash designed for 100 nm. (a) A variety of programming mechanisms are employed in floating gate memory structures. These include: Fowler Nordheim (FN) tunneling, i.e., tunneling of cold electrons through a triangular barrier using high electric fields; and a variety of hot carrier processes through drain, source, or substrate-side injection, secondary impact ionization [7], etc. The goal of utilizing the hot-carrier processes is to improve on the charging time by reducing the effective barrier height for injection of energetic carriers. The length scale over which hot carriers lose their energy (9 40 nm from our simulations) affects the charging time because smaller gate lengths and poorer electrostatics both reduce the incident flux and transmission probability. This is the major limitation in the scaling of front-floating gate structures. Secondary impact ionization approaches are difficult to implement in silicon-on-insulator structures because of the limited vertical extent. So, improving hot-carrier injection together with improving electrostatics is critical to continuing scaling of floating-gate memory structures. The constraints arising from energy loss and maintaining adequate current injection are balanced well in the back-floating gate structure. In this device, the charge is placed on the back and affects the threshold voltage through the change in electric field. Thus, it uses depleted SOI structures. Charge from the channel screens the high programming biases of the back-gate/substrate, which helps maintain reliability of the top read oxide, but the reliability of the back-oxide is affected by similar constraints as that of the front-floating gate structures although it sees smaller process-induced damage. The endurance and retention are a function of the quality and thickness of the oxide as well as process-induced effects. Since nonvolatility requires a specific minimum oxide thickness to prevent charge leakage, the fundamental constraints for endurance and retention in this structure are not likely to be any different from that of the front-floating gate structures. The charge stored on the back-floating gate modulates the threshold voltage. Unlike the front floating gate structures, where the read voltage and programmed threshold voltage are levered by the injection and control insulator thickness and larger voltages are needed, a back-floating gate device does not need the boosting of the voltages for similar signal strength and hence is lower in power with a programmable threshold voltage shift of approximately the band-gap of silicon. Since the read operation is decoupled from storage function, the device structure is also more immune to read-disturb and maintain large improvements in subthreshold slope in the programmed state; this potentially has strong implications for multilevel storage. The erase operation in the back floating structures can be accomplished using FN tunneling mechanism similar to that used in conventional NVRAMs. Fig. 5 shows a circuit schematic for 2 2 memory array in NOR configuration [8] with a shared source line between adjacent rows. The NOR memory architecture provides random access capability where any cell can be directly addressed through the appropriate bit and word lines. Erase operation can be achieved as a block by changing the channel and doped region potentials w.r.t. that of the substrate. A positive source (bit-line source, BLs) and drain (bit-line drain, BLd) erases the entire row with suitably high voltages. Selective writing to a cell is accomplished by turning on the channel of a transistor while providing aiding fields for injection into the back-floating gate. So, to program the cell for bit 00, with substrate grounded, a negative source bias (on BL0s), a smaller negative drain bias (on BL0d) and a gate bias (on WL0) are applied to turn on the channel of bit 00. Cells that are addressed by the same word line (WL0), but that should not be written (e.g., bit 10) are biased to equal source and drain potentials to prevent any hot carrier formation in the channel.

42 250 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002 Fig. 6. Flowchart for quasi-static simulation of back-floating gate charging using MC simulation together with determination of transmission coefficient. Also, when bit 00 is being programmed, the read gate of cell bit 01, which shares the same bit lines (BL0s and BL0d) as that of cell bit 00, is biased negatively using WL1 to turn off the channel and hence avoid programming disturb. III. SIMULATIONS AND RESULTS In this section, the discussion is based on a device structure with 15-nm Si channel, 6-nm injection oxide between the back floating gate and channel, 9-nm control gate oxide and a 20-nm thick floating gate. The device is designed for a 45-nm gate length with 2-nm gate oxide and its transport is simulated using DAMO- CLES [2], which does not model tunneling effects but accurately models carrier energetics. All major scattering processes (electron electron, diffuse scattering at oxide/silicon interface, ionized impurity, phonons, etc.) are included in the simulation, but two-dimensional quantization effects are not, in order to keep the simulation time acceptable. The consequence of this assumption on comments derived is insignificant because much of the phenomena of interest occur at the drain end. The time constants of MC simulation (time steps of 20 fs for scattering evaluation) and the time-constant for charging of floating gate (ns to ms) are quite disparate. So, we approach the simulation of floating gate charging as a quasi-static phenomenon evaluated using the data from the MC calculation. MC simulation is used to extract the hot carrier distribution in the channel and WKB approximation is used to calculate the transmission coefficient of electrons across the injection oxide. Electron current density from Si to SiO at any cross section along the channel can then be obtained by integrating over the electrons with velocity component perpendicular to the interface and directed toward it. So, our procedure for the calculation is outlined in Fig. 6. We determine the carrier energy and velocity distribution using a large number of MC particles and collect data over a large time period ( 6 ps) after steady-state has been achieved for the bias conditions applied. This solution of BTE does not include tunneling, but provides us with the information about energy and velocity of each particle. The injected current density from the silicon channel as function of position ( ), is then given by the equation (b) Fig. 7. Carrier distribution in the vertical cross-section between the back floating gate and the silicon channel near the drain end at (a) 2 and (b) 4-V drain bias. (a) is the hemi-distribution of electrons incident at the interface, is the density of available electron states and is the transmission coefficient. In our Monte Carlo simulation, this integrand reduces to a summation over each and every simulated particle together with a normalization charge factor ( )., the transmission coefficent, is given by (2) for a trapezoidal barrier, and where is the elementary charge, is the energy, is the electron velocity component incident at the interface, (1) (3)

43 KUMAR AND TIWARI: SCALING OF FLASH NVRAM TO 10 s OF nm 251 (a) Fig. 8. Distribution function of electrons in the hot carrier region of the drain as a function of energy. The different plots are for different drain bias conditions. (b) Fig. 9. Electron energy along the channel for carriers at different drain bias conditions. The electron energy loss occurs over different length scales depending on the energy of the carriers. Note also that at the highest bias field, penetration occurs into the source region. for triangular barrier. In these equations, is the electric field, is the spatial position in the direction of tunneling, is the tunneling effective mass and is the reduced Planck s constant. The net flux can now be calculated using the potential distribution provided by the solution. Fig. 7 shows an example of this for the distribution of electrons at two different bias voltages 2 and 4 V on the drain with the sampling in a narrow cross-section with the injection overlap running between floating gate and the silicon channel. The normalization factor, in (1), accounts for the carrier density to particle relationship in the MC simulation. So, the BTE solution provides us with a distribution function and we calculate injected charge through the quasistatic relation between the injected charge density and the current density. The solution, thus proceeds according the flow chart of Fig. 6. We start with the steady-state condition with no net charge on the floating gate. By solving the particle distribution function we (c) Fig. 10. Energy distribution during programming in a 45-nm gate length back-floating gate Flash cell for (a) 0, (b) 20, and (c) 40 nm overlap showing increasing hot electron coupling to the floating gate. can now calculate the time for injecting a charge, whose magnitude is a function of the accuracy desired. The injection of this charge changes the electrostatic potential of the floating gate and the rest of the structure and we can now determine the

44 252 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002 Fig. 11. Injection current density for different overlap lengths referenced to front reading gate edge. (a) carrier distribution function for this updated potential again. The process can be continued until one has obtained the desired accuracy and information related to the charging. Note that in these calculations, the largest transmission probability occurs for electrons that tunnel through a small barrier or surmount the barrier (, with no quantum-mechanical reflections included). So, most of the charging occurs through carriers that have energy larger than the oxide/silicon barrier height or are close to the top within a fraction of an electron volts (ev). Fig. 8 shows examples at four different drain bias conditions. The results are similar to those described by Fischetti et al. [9] in their study of the subband-gap impact ionization effects in MOSFETs: the carriers show a behavior that closely follows two tempertures for the charge cloud. What is specifically interesting in this figure is the behavior at 4 V and higher, the typical conditions for aiding hot carrier effects for injection. We now see specific band-structure related scattering and energy loss effects at the and L symmetry points. Clearly, use of a higher drain bias aids in the injection efficiency by providing a larger electron distribution. The second crucial consideration is the energy loss mechanism as the carriers scatter in the highly doped drain regions. Fig. 9 shows, for multiple bias conditions the position-dependent electron tailing of average energy. And, the high energy carriers lose their energy at length scales between 8 and 40 nm (the length scale for drop in energy). Further down as the electron traverses the drain high field region it loses energy at length scales of nm and once it encounters the high doping region of the drain and no accelerating field, the loss length scale expands to higher values. This loss in energy, coupled to its transmission coefficient effect, has a significant contribution to the net flux of electrons that are available for injection into the floating gate. Since the average field in the injection direction is small by design for good electrostatic control, the ability to inject is strongly dependent on this hot carrier behavior together with the capture in the floating gate region. Fig. 10 shows the hot-electron distribution near the drain junction for various overlap dimensions of the back-floating gate with respect to front/read gate edge. Simulations show that (b) (c) Fig. 12. (a) Average electron kinetic energy distribution (b) electron density and (c) injection current density along the channel for different read/front gate bias conditions. The memory cell is being programmed by applying 8 V to the back gate and 4 V to the drain. for hot carrier processes, an overlap of nm is sufficient to couple 90 of the hot carriers in the channel region.

45 KUMAR AND TIWARI: SCALING OF FLASH NVRAM TO 10 s OF nm 253 the front-floating gate structure using similar design rules for injection and control oxides. The back floating gate structure in these calculations is charged using 3 V and 4 V drain bias and 8 V at the control gate. Charging times of the order of s are required to change the threshold voltage of the device by 1 V. The charging transient of a conventional floating flash cell designed for the same gate length dimensions and oxide-floating-gate-oxide stack thickness has a charging time that is one to two orders of magnitude slower. Thus, the ability to decouple the storage from the read function, allows us to provide in these structures a larger overlap that leads to significant improvement in the write times and a scalable transistor design that leads to significantly improved electrostatics and charge transport control and hence lower operational power. Fig. 13. Simulated programming characteristic of the back-floating gate memory cell for two drain bias (3 and 4 V) conditions. Also shown is the significantly slower charging behavior of a conventional front floating gate flash cell under similar programming conditions. While this figure is qualitative, Fig. 11 shows the calculated injection current density as a function of position along the overlap region of the back-floating gate. The maximum in this injection occurs around 15 nm in the drain junction and rapidly decays beyond that position. This is quite similar in dimension to the energy relaxation length scale for the hot carriers as discussed before. The back floating gate is not constrained in its size by the front floating gate length and allows for a larger overlap with the channel s doped regions, thus providing for more efficient coupling for programming by cold and hot electron injection processes. Thus, for Fowler-Nordheim tunneling the advantages of low power are maintained while improving the scalability and reducing write times through increased source function. For hot carrier processes, where much of the scattering now occurs in the doped extension regions, the larger overlap allows large coupling to be maintained even down to the field-effect limit of transistor [4] gate lengths. Injection in these structures can also be affected by providing additional carriers through the biasing of the front/read gate: biasing the front/read gate has an interesting effect on the injection current density even though the carrier density in the Si body is made higher by the channel formation near the front/read oxide interface [see Fig. 12(a)]. Biasing the front gate causes a decrease in the peak average kinetic energy gained by the electron in the channel and then it loses the energy over a longer length scale [see Fig. 12(b)]. Biasing of the front gate causes a reduction in the vertical field in the structure and in larger carrier density and hence electron-electron scattering. Two distinct regions are evident where one bias condition dominates the injection current density [see Fig. 12(c)] over the other and iterates the strong dependence of transmission probability on energy. Knowing the injection current density at the interface along the channel and in the drain extensions, the quasistatic calculation of programming time follows directly. Fig. 13 shows the threshold voltage shift as a function of time using the procedure described in the flow-chart for both the back-floating and IV. SUMMARY We have described the operation of a new backside floating gate Flash memory that decouples sense function from storage function and compared its operation to a conventional front floating gate structure. This decoupling provides large improvement in scalability beyond present-day practice of nonvolatile memories and efficient programming even at many 10 s of nm device dimensions. Our proposed structure is compatible with the back-plane and double-gate approaches for scalable transistors. We also described a procedure by which the accuracy of Monte Carlo simulations can be employed to simulate the nonvolatile memory structures that depend on tunneling of charge for storage. The method allows us to bridge the short and the long time step needs. ACKNOWLEDGMENT Discussions with S. Laux and M. Fischetti of IBM Research have been invaluable to this effort. The authors would also like to thank A. Kumar of IBM Research from the time one of them (S. Tiwari) was at IBM and where the idea of back-floating gate memories was first born (Patent ). REFERENCES [1] S. Aritome, Advanced flash memory technology and trends for file storage application, in Tech. Dig. IEDM, 2000, p [2] S. E. Laux, M. V. Fischetti, and D. J. Frank, Monte Carlo analysis of semiconductor devices: The DAMOCLES program, IBM J. Res. Develop., vol. 34, p. 466, [3] D. J. Frank, Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?, in Tech. Dig. IEDM, vol. 92, 1992, p [4] I. C. Yang, C. Vieri, A. Chandrakasan, and D. A. Antoniadis, Backgated CMOS on SOIAS for dynamic threshold voltage control, IEEE Trans. Electron Devices, vol. 44, p. 822, May [5] S. Tiwari, P. Solomon, J. J. Welser, E. C. Jones, F. R. McFeely, and E. Cartier, CMOS and memories: From 100 nm to 10 nm!, Microelectron. Eng., vol. 46, p. 3, [6] L. Xue and S. Tiwari, Multi-Layers with Buried Structures (MLBS): An approach to three-dimensional integration, in Tech. Dig. IEEE SOI Conf., 2001, p. 12. [7] J. D. Bude, M. Mastrapasqua, M. R. Pinto, R. W. Gregor, P. J. Kelley, R. A. Kohler, C. W. Leung, Y. Ma, R. J. McPartland, P. K. Roy, and R. Singh, Secondary electron flash A high performance low power flash technology for 0.35 m and below, in Tech. Dig. IEDM, 1997, p [8] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Norwell, MA: Kluwer, 1999, pp [9] M. V. Fischetti and S. E. Laux, Monte Carlo study of subband-gap impact ionization in small silicon field-effect transistors, in Tech Dig. IEDM, p. 305, 1005.

46 254 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002 Arvind Kumar (S 98) received the B. Tech. degree from Indian Institute of Technology at Kanpur, India, in He is currently working toward the Ph.D. degree in electrical and computer engineering from Cornell University, Ithaca, NY. His primary research interests include modeling and experimental investigation of scalable nonvolatile memory structures and fault tolerant architectures in CMOS integration. Sandip Tiwari (S 76 M 80 SM 87 F 94) is Professor of Electrical and Computer Engineering at Cornell University, Lester B. Knight Director of Cornell Nanofabrication Facility and Director of National Nanofabrication Users Network. His current research interests are in small devices and their circuits, in ideas and technologies that allow functional integration and in interesting offshoots of small structures in other areas. Among his contributions and inventions that have found large industrial application and research interest are: nanocrystal and quantum-dot low power embedded memories, vertical transistors in multi-gbit DRAM memories and the technology of heterostructure bipolar transistor used in wireless applications. He has been a Research Staff Member and Manager for Exploratory Devices and Device Modeling at IBM, has held visiting and adjunct faculty appointments at the University of Michigan and Columbia University. He is author of the textbook Compound Semiconductor Device Physics. Dr. Tiwari is a Fellow of American Physics Society (APS) and has received the Young Scientist Award of 1991 from Institute of Physics. He is the Editor-in- Chief of IEEE TRANSACTIONS ON NANOTECHNOLOGY.

47 444 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004 Investigation of Channel Hot Electron Injection by Localized Charge-Trapping Nonvolatile Memory Devices Eli Lusky, Member, IEEE, Yosi Shacham-Diamand, Gill Mitenberg, Assaf Shappir, Ilan Bloom, Member, IEEE, and Boaz Eitan, Senior Member, IEEE Abstract A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, densitiy and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be 40 nm, located over the junction edge. Index Terms Band-to-band-tunneling (BTBT), channel hot electrons (CHE), gate-induced drain leakage (GIDL), localized charge, nitride read-only memory (NROM), programming transfer function (PTF), spatial distribution, subthreshold. I. INTRODUCTION THE SPATIAL characterization of channel hot electron (CHE) injection has been investigated in the past mainly by Monte Carlo (MC) simulations [1], [2] and charge-pumping (CP) measurements [3] [10]. MC simulations are rather complicated and the spatial distribution can not be verified directly gate current measurements can only be used to compare with the simulations with no indication of the charge distribution. Experimental characterization by the CP techniques has been widely accepted as a tool to quantitatively measure the energy and lateral distribution of interface-states and oxide trapped charges in MOS transistor. CP applicability in characterizing fixed charge in the dielectric is limited. Two main drawbacks of the CP method are its inability to provide detailed information on trapped charge over the n+ junction and the relatively small signal of the trapped charge. Manuscript received August 29, 2003; revised December 8, The review of this paper was arranged by Editor J. Vazi. E. Lusky is with the Saifun Semiconductors Ltd., Netanya Israel, the Department of Physical Electronics, Tel-Aviv University and also with the Nano-Science and Nano-Technology project, Ramat Aviv, Israel. I. Bloom and B. Eitan are with the Saifun Semiconductors Ltd., Netanya Israel. Y. Shacham-Diamand, G. Mitenberg, and A. Shappir are with the Department of Physical Electronics and the Nano-Science and Nano-Technology project, Tel-Aviv University, Ramat Aviv, Israel. Digital Object Identifier /TED To use the CP technique to characterize the localized chargetrapping nonvolatile memory devices requires a uniform initial surface states distribution. This last assumption is not always true [6], [10]. To overcome the nonuniform initial surface states distribution, a long CHE stress is incorporated in CP measurements. The continuous long stress time cannot be considered in localized charge-trapping nonvolatile memory devices. Cycling is not useful either due to hot hole injection. Recently, the subthreshold slope of the NROM device has been introduced as a simple characterization method of the spatial CHE injection distribution [11] [14]. This method is based on fitting two dimensional (2-D) simulations and measurements of a cell following CHE injection. Due to the extremely high trapping cross section of the ONO-stacked dielectric and the deep nitride traps [15], the spatial distribution of the localized trapped-charge reflects the CHE injection distribution. In this paper we introduce an improved measurement method that relies on both the subthreshold slope and the gate-induced drain leakage (GIDL) characteristics [16]. Incorporating the two techniques enhances the accuracy of the extracted distribution. The signal in the proposed method is orders of magnitude larger compared with the CP technique[9], [12]. The dc measurements are yet another very significant advantage of the proposed technique over the CP ac technique. GIDL current is attributed to band-to-band tunneling (BTBT) [17] [21] in the gate to drain overlap region. In an n-mosfet, GIDL takes place when the gate is negatively biased, and the drain is positively biased. Under these conditions, a significant section of the n+ region under the gate next to the channel end is depleted from electrons. When the electric field across the dielectric becomes sufficiently large and the doping concentration is in the range of cm, minority carriers BTBT can be initiated. The generated minority carriers (holes) in the depleted region are swept laterally to the substrate. Under large junction bias ( ), part of these holes become hot enough to surmount the oxide barrier and are injected into the insulator. To become a reliable measurement technique, the injection has to be prevented. This is assured by keeping small (1.5 3 V). Since the BTBT mechanism is sensitive to the trapped-charge over the n+ junction, the GIDL characteristics can be utilized as a complementary measurement to the subthreshold slope technique. The NROM device is a localized charge-trapping device capable of two-bit per cell operation [11]. CHE injection is used as a programming method and hot hole injection as an erase /04$ IEEE

48 LUSKY et al.: INVESTIGATION OF CHANNEL HOT ELECTRON INJECTION 445 Fig. 3. GIDL characteristics of NROM device under programming windows of 1V = 0:35 V03:15 V. These values correspond to the 1V described in Fig. 3. Fig. 1. Schematic illustration of the NROM cell. The read operation is performed in the reverse mode where the source and the drain are interchanged in respect to the programming operation. Fig. 2. Subthreshold characteristics of NROM device under programming windows of 1V =9mV 0 2:17 V. mechanism. Read operation is performed in the reverse mode where the role of the source and drain are interchanged relative to the programming operation (Fig. 1). The spatial characterization of the CHE injection is important for better understanding of this mechanism, for scaling optimization of NROM technology, for programming of both floating-gate and localized charge trapping based memory cells, and for optimization of hot electron degradation in MOS devices. Following the introduction, Section II introduces the subthreshold and GIDL measurement techniques. In Section III, a study of the sensitivity of the subthreshold and the GIDL characteristics to localized charge utilizing a 2-D device simulator (MEDICI) is presented. Based on the insight gained in Section III, the spatial distribution of the localized trapped-charge is extracted in Section IV by fitting between simulations and measurements. In Section V the conclusions of this work are summarized. II. EXPERIMENTAL This work was carried out utilizing current voltage ( ) measurements and 2-D simulations of the NROMs subthreshold and GIDL characteristics. The substrate doping of the measured device was cm with cm boron pocket implant [Fig. 1], located in the channel next to the n+ junctions. The effective channel length of the device is eff m, the channel width is m and the oxide equivalent ONO thickness is nm, where the bottomoxide, nitride and top-oxide thickness are nm, nm, and nm, respectively. Due to UV radiation and electrical bias during the production process, the reported fresh cells are charged [22], resulting with initial of 1.8 V, V higher than expected. The subthreshold s are measured using the reverse read operation with low drain to source bias, V, to avoid the drain induced barrier lowering (DIBL) effect [23]. The GIDL measurements were performed by reverse biasing the n+ junction and negatively biasing the gate. The selected reverse biased junction voltage is V to avoid hole acceleration and injection into the nitride layer. Furthermore, during the measurements the applied vertical bias between the gate and the drain induces a low electrical field ( mv cm) that does not initiate any FN tunneling. A sequence of subthreshold and GIDL current measurements during the course of programming is shown in Figs. 2 and 3, respectively. The programming operation is performed with stepping drain voltage, where the gate voltage is V and the programming pulse time is. In Fig. 2 the subthreshold characteristics correspond to wide range of threshold voltage increase ( s), between 9 mv and 2.17 V. For small s, between 9 mv and 630 mv, is achieved by mere subthreshold slope reduction. For larger programming levels, represents a combined effect of shift (flatband voltage change ) and subthreshold slope reduction. The reduction in the subthreshold slope with increased is clearly observed. In previous works [12] [14] it was demonstrated that the subthreshold slope reduction is due to localized charge, trapped above the metallurgical junction. Note, refers to the required increase in gate voltage that corresponds to a pre-defined low level subthreshold current. In Fig. 3 we present the GIDL characteristics that correspond to the programming levels shown in Fig. 2. During programming, the GIDL curves are shifted laterally along the gate voltage axis. To measure the GIDL voltage ( ) a reference GIDL current of pa is selected. An important observation is that for the low programming level, is

49 446 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004 larger than. For example, mv (Fig. 3, curve #1) corresponds to mv (Fig. 2, curve #1). This indicates that for small programming levels, the GIDL measurement is by far more sensitive than the subthreshold characteristics. To establish the relation between both monitors, is plotted as a function of during programming (Fig. 4). This plot is defined as the programming transfer function (PTF). The PTF consists of three regions: (a) for mv, the slope is ; (b) V mv, the slope decreases very fast to ; and (c) V, the slope reaches a constant value of. These characteristics reflect the subthreshold slope and shift insensitivity compared to GIDL to small amount of trapped charge. Moreover, the PTF provides an insight to the CHE injection dynamics during the programming operation; Two possible explanations can be given to the initial large slope and its dramatic decrease. 1) The spatial distribution of the trapped charge is constant for the entire programming sequence. The slope change is the result of the different sensitivity of and to the electron distribution while programming advances. 2) The charge distribution widens as the programming operation advances. In such a case the proposed measurement technique of the spatial distribution, does not reflect CHE in nmosfet devices. In the following sections we show that the first explanation describes better the development of the charge distribution during the programming operation. This will establish the correlation between the trapped charge and CHE spatial distribution. III. LOCALIZED CHARGE EFFECTS ON THE SUBTHRESHOLD AND GIDL CURRENTS The 2-D device simulations were performed using the device simulator MEDICI. The device modeling is supported by a 2-D process modeling (TSUPREME4) that was verified by material science analysis techniques, SIMS, AES, and SEM metrology and imaging for dimensions verification. The device simulator solves simultaneously the 2-D Poissons, continuity and driftdiffusion equations. Automatic boundary conforming (ABC) mesh enhancement is used, allowing adjusted grid spacing according to the doping profile, the electric field and the device structure. The typical surface mesh spacing is 1 2 nm. It was found that denser meshing provides no merit when deriving the effects of localized charge on the simulated s. The Universal Mobility Model [24] and Kanes model [25] were used for the subthreshold and GIDL simulations, respectively. Simulating the charge distribution effect on the subthreshold and GIDL characteristics is a time consuming iterative process. An initial distribution is assumed, followed by simulation analysis and distribution adjustment to achieve a good fit to the measurements. Acquiring a physical insight of the involved mechanisms may minimize the iteration process and save time. In this section we show how the physical insight has been acquired. The investigation is performed in two stages. First, in Section III-A, a general spatial sensitivity to the localized charge is derived. In the second stage, in Sections III-B and C, a more Fig. 4. Transfer function of 1V as a function of 1V for various programming levels between 9 mv and 2.17 V. Fig. 5. Sensitivity function of 1V and 1V square charge packet characterized by 10-nm-wide and cm concentration. detailed analysis of the subthreshold and GIDL characteristics is performed. A. Sensitivity Functions to Localized Charge To investigate the sensitivity of the GIDL and subthreshold curves to the location of the trapped charge we simulated the effect of a narrow (10 nm) charge packet, located over the n+ junction and the channel region. The simulated and are plotted in Fig. 5 as a function of the location of the charge packet. In these simulations the charge packet is assumed to be located at the top oxide-nitride interface, with a concentration of cm [26], [27]. The highest sensitivity is achieved nm from the metallurgical junction, inside the channel. For charge packet located further toward the channel, the sensitivity is almost constant, while for trapped charge located over the n+ junction, the sensitivity decreases. Due to the narrow charge distribution, is mainly due to subthreshold slope reduction. The simulations were performed under the reverse read operation with V and V. The larger induces DIBL conditions and results in a smaller. The GIDL current sensitivity function is almost complementary to the subthreshold characteristics. It is most sensitive to a region located nm inside the n+ junction where the doping is cm. Away from this location the sensitivity of the GIDL measurement decreases. When the trapped charge is located closer toward the metallurgical junction, the sensitivity decreases due to the reduced doping concentration. When the trapped charge is

50 LUSKY et al.: INVESTIGATION OF CHANNEL HOT ELECTRON INJECTION 447 Fig. 6. Simulation of the subthreshold curves for different cases: Curve a represents fresh cell. Curves b and c simulate programmed cells with a 40-nm wide charge packet located in the opposite side of the source junction edge. Curve d simulates the effect of a 100-nm wide charge packet, located above the channel. Points A D demonstrates subthreshold slope decrease, induced by locally trapped charge. located deeper inside the n+ junction, the doping concentration increases substantially and the sensitivity decreases due to the enhanced electrical bias required to initiate BTBT. The above results indicate that though the monitors and are mostly sensitive to different regions, these locations are partially overlapping. Furthermore, it is noteworthy that the sensitivity functions are capable of providing only a qualitative description of the s response. The description is limited to the case of narrow charge distribution. Wider charge distributions will result in modified sensitivity functions. B. Subthreshold Characteristics The effect of programming on the subthreshold characteristics in localized charge trapping devices was reported in [12] ascribing it to the presence of local charge over the n+ junction and the channel. The subthreshold characteristics were further investigated in [13], [14]. In Section III-B1 we show the effect of charge location, width and concentration and in Section III-B2 we discuss and analyze the fringing field effect as the root cause for the subthreshold slope reduction and shift. 1) Effect of Localized Charge on the Subthreshold Curves: We have investigated the subthreshold slope reduction by simulating the effect of the location, concentration and width of the trapped charge. In Fig. 6 we compared the subthreshold characteristics that correspond to three different charge distributions with the same charge density of cm per unit area. The three profiles are located: 1) over the n+ junction, 2) over the channel next to the n+ junction, and 3) same as (2) with 100 nm width relative to 40 nm for the other two cases. The simulated curves indicate that subthreshold slope decrease occurs in two of the above cases. For the first case, where the charge is located over the junction (curve b), the subthreshold slope decrease is without any. In the second case, where the charge is located over the channel (curve c) a superposition of a subthreshold slope reduction combined with can be observed. For wider distribution over the channel (curve d), the subthreshold has a larger with small slope reduction. The effects of the Fig. 7. Mulations of the subthreshold characteristics that correspond to localized charge over opposite sides of the source n+ junction. The width of the localized charge are 10, 40, and 100 nm with charge concentration of cm. Uniform charge distribution was also simulated. charge width and location with increased charge concentration ( cm ) are shown in Fig. 7. The square charge packets are with 10, 40 and 100 nm widths over the n+ junction and the channel next to the junction. The effect of uniform charge distribution, located above the entire channel region is added. The uniform charge distribution serves as a reference condition where the fringing field effect associated with the localized charge is eliminated. The effect of the localized charge above the n+ junction next to the channel is mainly a reduction of the subthreshold slope with minor. The subthreshold slope reduction saturates for trapped charge with a distribution wider than 40 nm. The simulated values that correspond to the cases with 10-nm charge packet widths are 0.31 V, where for both the 40 and the 100 nm cases the value is approximately 1.96 V. The observed impact of the localized trapped charge above the channel next to the n+ junction on the subthreshold slope and are: 1) the localized charge induces a smaller than that of a uniform trapped charge. This effect is pronounced for narrow charge distributions. 2) The subthreshold slope reduction is a nonmonotonic function of the charge packet width. The maximum slope reduction is observed for nm charge packet width, the same as for the cm case. For wider or narrower distributions the slope reduction is smaller. When the charge packet width is of the order of nm, the slope returns approximately to its initial value. 2) Fringing Field Effect: The fringing field effect is responsible for the subthreshold slope decrease and shift. The effect of the fringing field when the charge is located over the n+ junction is already discussed in great length elsewhere [12]. Simulations of the channel surface potential that are associated with trapped charge over the n+ junction, reveal that the subthreshold slope reduction is ascribed to the pining of the surface potential due to the fringing field that is induced by the trapped electrons. When the trapped electrons are located over the channel and the device is under subthreshold conditions, the region underneath is depleted and the rest of the channel is inverted (Fig. 8). The fringing field lines that originate at the trapped charge and terminate at the channel form a transfer region between the inverted and depleted regions, which mostly extend into the rest of the channel and partly penetrate into the region outlined by

51 448 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004 Fig. 8. Surface channel potential in subthreshold conditions. Curves A F correspond to curves a and c under 10 pa subthreshold condition in Fig. 6, respectively. These curves demonstrate potential barrier variation induced by the locally trapped charge over the channel, next to the junction. Fig. 9. (a) Simulations of the GIDL characteristics that correspond to localized charge over the channel next to the n+junction. (b) Over the n+junction next to the channel. The width of the localized charge are 20, 40, and 100 nm with a charge concentration of 10 cm. the trapped charge. The trapped charge effect is most dominant at the silicon surface, thus the depletion region penetration under the trapped charge is most effective underneath the surface, giving rise to the sub-surface conduction [13]. The penetration of the fringing field lines to the region underneath the localized charge is responsible for the gradual increase of as a function of the charge packet width. When the trapped region is narrow, punchthrough between the source and the inverted channel reduces the effect of the trapped charge. Note, under uniformly distributed trapped charge conditions (Fig. 7) aligns with the common definition of flatband voltage change. To illustrate the fringing field effect when the trapped charge is above the channel, the surface channel potentials that correspond to curve (c) in Fig. 6 are drawn in Fig. 8. A comparison is shown between the 40-nm charge packet and the fresh cell. When the programmed cell is under flat band condition (Fig. 6, V), the surface beneath the trapped charge is depleted while the rest of the channel is in strong inversion. A transfer region between the inversion and depletion regions extends into the channel by nm and into the localized charge region by nm. As a result, the potential barrier in the subthreshold regime is no longer flat. It is interesting to note that the potential barrier that corresponds to the flat band conditions for both cases ( V for fresh cell and V for programmed cell) is not identical but rather higher for the case of the programmed cell. This is a reflection of the sub-surface current that appears under local charge trapping conditions. The fringing field can be evaluated by the charge sharing perspective [14]. In subthreshold conditions, a depletion region is developed, forming the transfer region. This region accounts for the charge sharing effect, resulting with locally larger depletion capacitance next to the source junction. The outcome is subthreshold slope reduction. This explanation gives rise to a monotonic decrease of the subthreshold slope as the charge packet becomes narrower. However, in extreme cases (for example 10 nm over the channel, Fig. 7), the junction built-in voltage supports substantial part of the depletion region underneath the localized trapped charge, thus diminishing the charge sharing effect and inducing subthreshold slope that is moderate compared to a wider distributions. C. GIDL Current Characteristics The effect of the charge packet width on the GIDL response is shown in Fig. 9. We selected for the simulations a square charge packet of 20, 40 and 100 nm width with charge density of cm. The charge packets were placed over the channel next to the n+ junction [set (A) curves] or over the n+ junction next to the channel [set (B) curves]. The simulations indicate that widening the charge packet located over the channel did not induce a substantial shift; As shown by set (A) curves, widening the charge packet from 20 to 100 nm changes by less than V, from 0.8 to 0.9 V. On the other hand, placing the charge over the n+ junction next to the channel region effectively induced an shift; widening the charge packet from 20 to 40 nm induced a substantial increase of, from 1.6 to 2.8 V. Further widening the charge packet to 100 nm induced an additional shift of V. These results indicate that the sensitivity function (Fig. 5) to localized charge depends both on the charge packet width and location. The closer the charge packet is to the junction, the more BTBT is induced. Addition of an adjacent charge packet in the channel direction is not effective. On the other hand, placing the charge over the n+ junction is of importance. Wider charge distribution induce larger shift. The enhanced shift is restricted to regions where the n+ doping is smaller than cm. Distributions that extend beyond this region will not shift further the GIDL curves. IV. CHARGE DISTRIBUTION AND DISCUSSION The previous sections showed that the GIDL characteristic is mainly sensitive to small programming levels, where most of the charge gets trapped over the junction edge. The subthreshold slope reduction and shift corresponds to larger amount of trapped charge over the n+ junction and the channel. By modeling the charge distributions and adjusting the corresponding 2-D simulations to the measurements we derived the spatial distribution of the trapped charge. By assuming a direct relation between trapped charge and charge injection the CHE injection distribution is extracted. In Figs we show the final simulations and measurement data of the subthreshold, GIDL and extracted trapped

52 LUSKY et al.: INVESTIGATION OF CHANNEL HOT ELECTRON INJECTION 449 Fig. 10. Comparison between simulations and measurement of the subthreshold I V curves under various programming levels. The fitting was achieved for 1V of 0.25, 0.63, 1.41, and 2.17 V. Fig. 11. Comparison between simulations and measurement of the GIDL I V curves under various programming levels. The fitting was achieved for 1V of 1.23, 1.83, 2.6, and 3.15 V. These values correspond to the 1V values described in Fig. 13. charge distribution, respectively. A good fitting between simulations and measurements is achieved for all cases, both for the subthreshold and the GIDL characteristics. The extracted spatial distributions that are attributed to the various programming levels indicate that the distribution width is nm over the n+ junction edge. The distribution width is approximately constant for all cases, indicating that the CHE injection is not affected substantially by the trapped charge. It is important to state that in all of the fitting attempts a smooth electron distribution is assumed. This is to state that the spatial distribution of CHE cannot have any major disruptions in continuity. In the entire volume of literature on CHE this is the case. For this paper, this implies that the uniqueness of our solution based on both subthreshold and GIDL is very high. In light of this conclusion, the PTF function (Fig. 4) can be explained; during the first stages of the program operation when a small amount of charge is trapped, the GIDL measurement corresponds immediately. The subthreshold, as indicated by the simulated sensitive function (Fig. 5) is weakly sensitive to this charge. Only when trapping a larger amount of charge, the channel potential barrier becomes wider (Fig. 8) and the subthreshold slope starts to degrade. As the programming proceeds, an shift is also induced, and become comparable, and the transfer function slope is reduced dramatically. This analysis is limited to a conditions where the drain and gate programming voltages and the programming windows allow the vertical field along the channel next to the drain junction to be in favor of electrons injection, i.e.,. Whenever this condition is not maintained, the CHE injection is expected to shift toward the channel region. is preferred rather than for this conditioning since it reflects better the maximum charge concentration as demonstrated in Figs. 4 and 12. From Fig. 12, it can be derived that for a cell of 0.35 m in width the fully programmed state ( V and V) is characterized by trapped electrons, where only electrons are located over the channel region. For the smallest programming window considered, V and V the total number of electrons is, where only are located over the channel region. The effect of the number of trapped electrons Fig. 12. Spatial distribution of trapped charge that correspond to different programming levels. The programming levels correspond to 1V and 1V of 0.25, 0.63, 1.41, and 2.17 V and 0.1, 23, 1.83, 2.6, and 3.15 V, respectively. on and is different; is approximately linearly proportional to it while is less sensitive and nonlinear with the number of trapped electrons. As a result, measurement can be utilized to monitor small quantities of trapped electrons. For example, V corresponds to a mere trapped electrons. V. CONCLUSION A novel method to characterize the spatial distribution of CHE injection is presented. The efficient trapping capability of the ONO stack in the NROM cell provides a useful measurement structure for this purpose. It is shown that the GIDL and subthreshold characteristics are sensitive to trapped charge over the n+ junction and the channel next to it. The features of the curves are attributed to the fringing field effect, associated with the localized charge. It is demonstrated that various parameters affect the fringing field. Among them are the location, width and concentration of the trapped charge and the doping profile of the device. By combining both the GIDL and the subthreshold slope techniques with 2-D simulations it was derived that CHE injection takes place in very narrow region, nm, located mainly over the n+ junction. It was shown that the distribution width is insensitive to the programming window, provided that the programming window is small enough and the electric field at the bottom-oxide is in favor of electrons injection. Deviation

53 450 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004 from these conditions will most likely result in a wider charge distribution. The above results indicate that the two-bit scaling of localized charge trapping device is not limited by the trapped electrons distribution above the channel. By setting an upper limit of of the channel length as the maximum electrons distribution to maintain the two-bit separation capability, nm cell is feasible. For floating-gate devices, the implication is that an extension of the floating gate beyond the channel region is required for improved charge collection. ACKNOWLEDGMENT Many thanks to Dr. E. Shauly from TOWER Semiconductors for providing us with process simulations. REFERENCES [1] L. Selmi, A. Ghetti, R. Bez, and E. Sangiorgi, Trade-offs between tunneling and hot-carrier injection inshort channel floating gate MOSFET, Microelectron Eng., vol. 36, no. 1-4, p. 293, [2] C. Huang, T. Wang, C. Chen, M. Chang, and J. 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Eitan, Characterization of channel hot electron injection by the subthreshold slope of NROM device, IEEE Electron Device Lett., vol. 22, pp , Nov [13] L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom, and B. Eitan, Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells, IEEE Trans. Electron Devices, vol. 49, pp , Nov [14] A. Shappir, Y. Shacham-Diamand, E. Lusky, I. Bloom, and B. Eitan, Subthreshold slope degradation model for localized-charge-trapping based nonvolatile memory devices, Solid State Electron. [15] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric, IEEE Electron Device Lett., vol. 23, pp , Sept [16] E. Lusky, I. Bloom, B. Eitan, Y. Shacham-Diamand, G. Mitenberg-Geva, and A. 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Huang, Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique, IEEE Trans. Electron Devices, vol. 45, pp , Oct [22] Y. Roizin, M. Gutman, S. Alfassi, and R. Yosefi, In-Process charging in microflash memory cells, in Proc. NVSMW, Monterey, CA, Feb. 2003, pp [23] T. A. Fjeldly and M. Shur, Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs, IEEE Trans. Electron Devices, vol. 40, pp , Jan [24] J. T. Watt, Surface Mobility Modeling, Computer-Aided Design of IC Fabrication Processes. Stanford, CA: Stanford Univ. Press, [25] E. O. Kane, Zener tunneling in semiconductors, J. Phys. Chem. Solids, vol. 12, pp , [26] E. Suzuki, Y. Hayashi, K. Ishi, and T. Tsuchiya, Traps created at the interface between the nitride and the oxide on the nitride by thermal oxidation, Appl. Phys. Lett., vol. 42, no. 7, pp , [27] E. Suzuki and Y. Hayashi, On oxide-nitride- interface traps by thermal oxidation of thin nitride in metal-oxide-nitride-oxide-semiconductor memory structures, IEEE Trans. Electron Devices, vol. ED-33, pp , Feb Eli Lusky (M 02) was born in Israel in He received the B.Sc. degree in physics, the M.Sc. degree in applied physics, and the M.B.A degree in 1994, 1996 and 1998, respectively, all from the Hebrew University, Jerusalem, Israel. In 2002, he received the Ph.D. degree in electrical engineering physical electronics, from Tel-Aviv University, Israel. His Ph.D. dissertation concerned localized trapped charge in oxide nitride oxide stacked layers. From 1996 to 1998, he was with Intel Corporation, Jerusalem, Israel. In 1998, he joined Saifun Semiconductors, Ltd., Netanya, Israel, where he serves as a Project Manager. Yosi Shacham-Diamand received the B.Sc. (summa cum laude), M.Sc., and D.Sc. degrees in 1977, 1979, and 1983, respectively, all from Technion Israel Institute of Technology, Haifa, Israel. He is a Full Professor at the Department of Electrical Engineering Physical Electronics, Fleischman Faculty of Engineering, Tel-Aviv University, Tel-Aviv, Israel. His main research topics are in the field of microtechnologies and silicon devices. From 1983 to 1986, he was with the University of California, Berkeley, as a Visiting Scientist, and six years at Cornell University, Ithaca, NY, as an Assistant Professor at the School of Electrical Engineering working at the Cornell Nanofabrication Facility (CNF). He served as the Manager of the Israel Consortium for sub-0.25/300 mm technologies, and since 2001, he has been the Academic Director of the Tel-Aviv University Research Institute for Nanoscience and Nanotechnologies. He is also the head of the Marian Gertner Institute for Medical Nanosystems and is holding the Kurt-Lion Chair for Nanoscience and Nanotechnologies. From 1998 to 2001, he was the Director of the Micro-Technologies Laboratory at the Department of Electrical Engineering Physical Electronics. Dr. Shacham-Diamand was a member of the Israel National Committee for Electro-Optics and Microelectronics and is a member of the Electrochemical Society and the Israeli Physical Society.

54 LUSKY et al.: INVESTIGATION OF CHANNEL HOT ELECTRON INJECTION 451 Gill Mitenberg, photograph and biography not available at the time of publication. Assaf Shappir was born in Israel in He received the B.Sc. degree in physics and mathematics from the Hebrew University of Jerusalem, Israel, in He received the M.Sc. degree in electrical engineering (physical electronics) from the Tel-Aviv University, Israel, in He is currently pursuing the Ph.D. degree in electrical engineering (physical electronics) at the Tel-Aviv University. The thesis concerns redistribution of localized trapped charge in oxide-nitride-oxide gate dielectric stack of a nonvolatile memory device. From 1993 to 1998 he served as a research and development officer in the Israel Defense Forces. Ilan Bloom (M 98) received the M.S. and Ph.D. degrees from the Microelectronics Research Center, Technion Israel Institute of Technology, Haifa, in 1987 and 1992, respectively. From 1992 to 1994, he was a Postdoctoral Fellow in the Physics Department, University of Illinois at Urbana-Champaign, specializing in 1=f noise in a variety of physical phenomena. From 1994 to 1998, he was appointed as a Lecturer at The Technion. From 1998 to 2003, he was the Technology Development Director at Saifun Semiconductors, Ltd., Netanya, Israel, working on a new silicon NVM technology called the NROM. Today, he is a Fellow in Saifun Semiconductors Ltd., Israel, exploring the NROM technology for future generations. Boaz Eitan (M 83 SM 00) was born in Israel in He received the B.Sc. degree in mathematics and physics in 1976 and the M.Sc. and Ph.D. degrees in applied physics in 1978 and 1981, respectively, all from the Hebrew University, Jerusalem, Israel. His Doctoral research was on physical limitations of short-channel MOS devices In 1981, he joined Intel Corporation, Santa Clara, CA, where he was involved in nonvolatile memory technology development. At Intel, he was also involved in the development of EPROM and EEPROM products. In 1983, he joined WSI, CA, as a developer of embedded memory products. There he served in several positions including a Manager of device physics group, Director of memory products, and Vice President of product and technology development. In 1992, he returned to Israel and established WSIs design center. In 1998, he established Saifun Semiconductors, Ltd., Netanya, Israel, which is developing the NROM technology. This is a localized trapping two-bits-per-cell NVM technology. He is serving as the President, CEO, and Chairman of the Board of Saifun. He served as a Director on the Boards of several public and private companies. As an active researcher in the NVM field for the last 25 years, he has published more than 45 papers, participated in 28 conferences, and has given 15 invited talks. He holds 67 issued patents and has 22 more patents pending.

55 110nm NROM Technology for Code and Data Flash Products Josef Willer, Christoph Ludwig*, Joachim Deppe*, Christoph Kleint*, Stephan Riedel*, Jens-Uwe Sachse*, Mathias Krause*, Ricardo Mikalo*, Elard Stein v. Kamienski*, Stefano Parascandola*, Thomas Mikolajick*, Jan-Malte Fischer*, Mark Isler*, Karl-Heinz Kuesters*, Ilan Bloom**, Assaf Shapir**, Eli Lusky** and Boaz Eitan** Infineon Technologies Flash, D Dresden, Germany, mailto: *Infineon Technologies, D Dresden, Germany **Saifun Semiconductors, Netanya, Israel Abstract A novel NROM generation with a bit size of 0,043µm²/bit at a 110nm design rule is introduced. The concept features mainstream CMOS type cell devices in conjunction with a metal contact based virtual ground array architecture. The new technology node serves both advanced code flash products and file storage memories up to 2 Gbit/die. Introduction Nonvolatile memories for mass storage applications are cost driven i. e. they require lowest cost/ bit product solutions. The NROM storing two separated bits in one cell is highly attractive for cost competitive products [1]. The NROM cell is based on localized charge trapping in the nitride layer of an ONO gate dielectric [2]. Historically, the contactless virtual ground array (Fig. 1) has been one of the very few cross point architectures that enable the smallest cell size (2.5-3F 2 per bit). It has also provided the symmetrical access that is necessary to address the two separate bits of the NROM cell. However, this classical array suffers from several scaling issues: (1) the device isolation between adjacent cells is performed by a channel stop implant with significant narrow width effect. (2) The S/D junctions of the cell device are implanted before the gate layer and certain furnace anneal steps, like the gate oxide growth. As a consequence, considerable lateral diffusion occurs. In order to maintain the small bit size and the low process complexity for the 110nm node conceptual innovations need to be introduced. The new cell architecture presented in this work benefits from the advanced NMOS transistors scaling concepts, including: trench isolation, n+ junction that is implanted after the policide deposition and local interconnect for S/D contacts. The process flow and device characteristics are shown. The suitability for a state of the art nonvolatile memory is demonstrated by cell endurance results. Key Technologies The basic principle of the new virtual ground array is illustrated in Fig. 2. Densely packed wordlines cross minimum pitch lines and spaces of active area and isolation trenches. A transistor is generated by the cross point area of a wordline and the active region below. The source/ drain areas are defined in a self aligned manner by the spaces between the wordlines; every S/D area serves two adjacent transistors. The structure described is very similar to a T-shape array, with ONO instead of Floating Gate as the trapping media. In order to create a symmetrical virtual ground array, two adjacent (along the WL) memory devices have to be linked together without consuming to much space (Fig. 3). This is achieved (1) by a staggered local interconnect feature which consist of a conductive gap fill that connects adjacent S/D areas. These local interconnects are interrupted by insulating fill material. In addition to that (2) minimum pitch metal 0 bitlines must contact every second local interconnect only. Thus, every bitline contact addresses the S/D junction of four different transistors. This results in a virtual ground memory which consists of a most densely packed cross point array of transistors (Fig. 4). The conceptual limitation of such an array is defined by the 2F per side pitch (4F 2 per cell or 2F 2 per bit). The practical limitation is based on Leff scaling and the cell size in 110nm technology is 0,043µm² or 3,5F² per bit. Fabrication Process The overall process flow is sketched in Fig. 5. The primary goal here is to obtain memory devices that can be fabricated using well known CMOS schemes. Indeed, the cell features a high degree of similarity with conventional NMOS devices: The overall gate structure and the whole process sequence, especially the source/drain engineering follow to a large extent the recipes of high performance, short channel NMOS transistors. Fig. 6 shows a schematic cross section along the wordline direction through the array after oxide filled isolation trenches have been processed. Fig. 7 reveals the corresponding view after ONO and the whole wordline stack have been deposited. The situation after gate patterning and liner deposition is demonstrated in the SEM photograph (Fig. 8) which exhibits the device cross section through the active channel region. The nitride of the gate dielectric appears thicker than it actually is due to the topology contrast. The following diagram (Fig. 9) displays a cross section along the wordline direction after n+ junctions have been implanted, and the gap between the encapsulated policide wordlines has been filled, planarized and patterned in order to obtain the local interconnect structures which are interrupted by insulating material. Minimum pitch dual damascene metal 0 is employed to contact the local interconnect features. Finally, Fig. 10 reveals an SEM cross section through the middle of a wordline in the situation where the bitlines are finished: This includes the formation of local interconnects and the deposition of an interlayer dielectric. Metal trenches as well as contact holes had also been etched, and metal 0 had been deposited and polished. Characteristics The read characteristics (Fig. 11) initial, programmed and erased states are shown. The subtreshold characteristics of the same states (Fig. 12) indicate that the programmed state Vt shift is a combination of a flat band increase and a slope degradation [3]. Endurance results are shown in Fig. 13. The programming is performed with 200nsec pulses, conditions that correspond to Data Flash applications. The erase is done with 1msec pulses, to emulate the fast block erase. No Vt degradation is seen throughout the endurance test. The Retention associated with the endurance test is shown in Fig. 14. The ~ 500mV saturated loss after 10K cycles guarantees a retention spec of 20 years. Conclusion In conclusion, we have demonstrated a very competitive NROM cell with NMOS like scaling. It includes the trench isolation with local interconnect. We maintained the VG array architecture; hence the design of this array is identical to our previous products. References [1] J. Willer, Proc. IEEE NVSMW, 2003, Monterey p15, (2003) [2] B. Eitan, et al., Proc. SSDM 99, Tokyo 522(1999) [3] E. Lusky et al. IEEE Electron Dev. Lett., EDL-23(9), 556(2002)

56 BL BL BL BL BL WL WL Process flow Shallow-trench-isolation L/S in minimum pitch WL WL Transistor bodies WL well implants, 3 gate dielectrics WL Wordlines WSi, nitride or oxide spacers Figure 1: Circuit diagram of virtual ground memory array WL Figure 2: Layout structure of wordlines crossing active area and STI lines BL BL BL BL BL T T T T WL Transistor extensions cell device and LDD implants High voltage Spacers CMOS S/D implants Local interconnect WL T T T T WL Gap fill and planarization BPSG...Passivation WL T T T T WL M0: bitline, W, minimum pitch M1: Al, M2: Al Figure 3: Layout structure of wordlines with spacers and local interconnects interrupted by isolation fills Figure 4: Novel virtual ground array architecture. BL and local interconnects indicated by lines only Figure 5: Process flow of STI bounded device architecture Figure 6: Shallow trench isolation Figure 8: SEM cross section of ONO based cell device perpendicular to the WL direction Figure 10: SEM cross section of STI bounded cell device along WL, channel width is 87 nm Figure 7: ONO, wordline stack Figure 11: Read characteristics of initial, programmed and erased state Figure 12: Subthreshold characteristics of initial, programmed and erased state Figure 9: Local interconnect, BL formation Figure 13: Endurance test Figure 14: Retention loss after bake

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69 !7'055 +4G 41( * 4.W* w. =4,& # 141([,417 4 #I4,yQ* 14# v,4 #F! 4. (%l,. 7! =4 1*!. * #Z". µâ )Ã)Ä ½sÅ+Æ V E T S XRl, #@=* > & # 141(CgY=fCÿ="v,4 414 G 4². =4`', +41: 414 % #s #s E =( 4± % #s # \. =4 E ', 97 * ž@! #s=4#s# #s =*+*+(]²gY Y+e gy Y=fN bgy Y3ÿ+ 4#=4. G 41(% 1( ( 7 *. =46v,4@ 4l R G 4#s. % a 4! #s 1( 4,& # 141( F& S T T S9 =4w 414 G 4 #zq [Z % #s 1(341( 4. * #s Z-7 * ;841( FG=G~ R G 4#s. % & # 141( Rv # zq [FlR* $N1* 14 #( * 1( 54. =4 :+4, D = +4 B. +4 D = +4,#. $=4( %+4#0y * ²gY Y=f. *<gy Y3ÿ++ =4 l, #Rl,. &. 41( a 4! #s 1( 4[& # 141( & gy Y3ÿ+[ =4 s* =4 7! =4 1*!. * #s ". B4. % & # 141( lf =4 4 =4F#I4 G 4#- #- =( 4)4=: =414s Çs ªNm ³ ³ È V Ek«Y3ÿ0X] 414 G 4j. =4 E [, jzq [ +41: 414#,7 * K. =4 E *+41( 4. * #? 4#I ;84 * )& # 141(R& #..!. 4*+7;84 =*+( *+: % v 7 F gy3ÿ d gy Y+S 4#=4. G 41(% y * ±gy Y+Sw. * gy Y+ew =4 l, #ž Éz[* #. +*. * 1(ŸyQ41( ( * lêi. =4œzQ % #s #,4. 4. b R G 4#s. %Ë*+7 & ( ( =* #t. 23 : 8#=4 1( 50 =:< g{š 73=* #I4 G= 4. %]*+7 % #s 1( =4=* 4 Ry * gy Y+e~. *_gy Y3ÿk =4>l, # =*. 4 # )84.! 4W.[;" =4F;84 * [0y * ²gY Y3ÿ. *us T T+U=k =4²l, #_. =4 ;84 =*+( *+: %,4G 41( * *,.F 7! > =4 1*!. * #s8". [B4. % 8& # 141( 8lR* $ =: * =4l #s ( 1* ]B ^RE. 4 =*+( *+: %< 1( ( 4w. =4,B?)DFE Q;8* % [ =4 #, yq41( ( * l` 7! =4 1*!. * #6". & # 141( w4 +=( * =:A. =4kB?)DFE. 4 =*+( *+: %A7 * 97!.! 4 :+4=4. * # v,4 # =4* 4. ]Sÿ =4#R.. 4] ]* 4. S e1* = #

70 264 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 3, NO. 2, JUNE 2004 A Nanoscale Memory and Transistor Using Backside Trapping Helena Silva and Sandip Tiwari, Fellow, IEEE Abstract We report results on a new structure that provides a scalable memory cell and a scalable transistor simultaneously in the same structure. The operational distinction is achieved through a difference in the bias range. The device employs a modified silicon-on-insulator substrate where charge is stored in a defected region underneath a thin single-crystal silicon layer employed for the formation of the transistor channel. At low voltages (below 1.5 V), the device operates as a transistor making use of the front silicon interface (preferred form), or the back interface, or both. The memory operation is obtained by use of high voltages, which allow injection of charge into the defected region in a stack of insulating films underneath the thin silicon channel, as well as the removal of the charge. The transistors are scalable because of the thin silicon technology and the memories are highly scalable because they allow efficient coupling between the carriers and storage region. The structure provides for a very useful decoupling of the memory read and transistor operation from the memory electrical storage operation. The experimental operation of the devices is described. Index Terms Back-floating gate, CMOS device scaling, EEPROM, flash memories, nonvolatile memory, scaling limits, semiconductor memories, silicon-on-insulator (SOI) technology, silicon oxide nitride oxide silicon (SONOS) memory, tunneling. I. INTRODUCTION MANY OF THE electronic applications employ logic together with nonvolatile memory, either through silicon integration such as in system-on-chip or through hybrid integration. The nonvolatile memory, in such applications, serves as the source of microcode, other operating code, or for other stored information that needs to be downloaded for the necessary computation being performed through logic and faster forms of memory such as static random access memories. Whereas MOSFET transistors appear to be on a path of scaling to the 10-nm-length scale [1] through judicious control of electrostatics and parasitics, conventional silicon nonvolatile memories (flash memories), based on front poly-silicon floating gates, do not follow this path of scaling with 90 nm [2] as the length scale for the most aggressive devices reported today. The difficulties of making smaller silicon nonvolatile memories with the conventional geometries arise from the fact that Manuscript received November 21, 2003; revised January 17, This work was supported by the National Science Foundation (NSF) under the Cornell Center for Materials Research and the Foundation for Science and Technology, Portugal. The fabrication was performed at the Cornell Nanoscale Facility, which is supported by the NSF under the National Nanofabrication Users Network. This paper was presented in part at the 2003 IEEE Silicon Nanoelectronics Workshop. The authors are with the School of Applied and Engineering Physics, Cornell University, Ithaca NY USA ( [email protected]). Digital Object Identifier /TNANO the gate stack (injection oxide, poly-silicon gate, and control oxide) cannot be thinned as required for small gate-length devices without compromising the memory performance. Smaller gate-length devices require thinner gate oxides for efficient control of the channel by the gate. In conventional flash memories, however, since the charge is stored between the channel and front gate, the thinning of the gate stack, injection, and control oxides is intrinsically coupled to issues related to the memory function, namely, retention time and reliability of the device. Also, from a low-voltage and low-power perspective, a thinner gate oxide will allow faster writing and erasing times and lower programming voltages, but worsen the retention time and reliability due to increased charge leakage. The hot-electron injection (HEI) coupling to the floating gate also degrades at small gate lengths because hot carrier mean free paths are in the nm range and a larger fraction of the hot carriers occurs in the drain junction region with the scaling of the physical gate length. Currently, it appears that in order to make smaller lower voltage and lower power silicon nonvolatile memories, alternative device structures or programming mechanisms need to be developed. High-density, isolated, and localized charge storage centers, such as dielectric defects or semiconductor nanocrystals, may provide such alternatives for silicon nonvolatile memories. As compared to a continuous conducting plate like in the current flash devices, isolated storage centers can be placed closer to the channel, resulting in a thinner gate stack with which small gate-length devices can be implemented. Carrier trapping through defects and interface states has been successfully utilized in silicon oxide nitride oxide silicon (SONOS) memories [3], where charge is stored in defects at the oxide nitride interface and within the nitride film, and these devices seem to be promising candidates for reduced dimension storage nonvolatile memory technology. Scaling of SONOS memories has been the focus of intensive research over the past years [4], [5] with significant improvements reported. However, the structure of the conventional SONOS memories, where the trapping layer still exists between the channel of the device and gate, continues to impose restrictions on scaling of these devices because of the interdependence of electrostatics, voltages needed for adequate programming, speed, capture cross sections, erasing speed, and nonvolatility. Here, we report on experimental results of a new structure [6] where the charging and discharging occurs through a trapping layer formed by a stack of insulating films similar to that of SONOS (an oxide nitride oxide (ONO) stack in the example reported here) that is placed on the back of a thin silicon channel. Conceptually, this is similar to that employed in back floating X/04$ IEEE

71 SILVA AND TIWARI: NANOSCALE MEMORY AND TRANSISTOR USING BACKSIDE TRAPPING 265 Fig. 1. Schematic of the backside trapping memory and transistor structure. The structure employs an oxide nitride oxide (ONO) stack on the back of a thin single-crystal Si channel. gates [7]. Uncoupling the charging mechanisms that lead to the memory function from the front-gate transistor operation allows efficient scaling of the front gate without compromising the memory characteristics of the device that depend only on the back insulating films stack. Unlike the front floating gate memories, where the threshold voltage shift is due to the shielding of the front-gate field by the charge in the floating gate, in the backside trapping device, the threshold voltage is controlled by charge-dependent potential of the back films stack, such as the substrate bias effect in silicon-on-insulator (SOI) transistors. The maximum threshold voltage shift in these structures is, therefore, determined by the silicon band gap, i.e., 1.1 V [8]. The technology of back-floating gate memories is considerably more complex, but allows the formation of threshold-voltage controllable scalable transistors together with the nonvolatile memories. The technology for the backside trapping memories is simpler with the only major change from SOI technology being in the type of substrate employed. The backside trapping memory device has unique properties and promising applications since it is both a scalable memory and a scalable SOI transistor in the same structure. This is accomplished by a suitable choice of structural parameters that allow the structure to operate as a transistor, similar to an SOI structure, without injection effects in insulators at low voltages, and for the structure to operate as a memory, similar to the back-floating-gate memory, with injection effects in insulators at higher voltages. This simplification and the structure s scalability holds promise for standalone nonvolatile memories, embedded memory applications, and nonvolatile memory applications. II. DEVICE STRUCTURE AND FABRICATION Fig. 1 shows a schematic cross section of a backside trapping memory and transistor. The thin active-silicon channel and the thin front oxide provides the structure the capability of scaling to tens of nanometers and the dual function of the device is obtained by use of two voltage ranges that are clearly distinct: at small voltages, the structure operates as a normal transistor and, at high voltages, with Fowler Nordheim (FN) tunneling or HEI, the structure operates as a memory device. Fig. 2 illustrates the fabrication process sequence for these devices. The starting substrate for device fabrication consists of a thin single-crystal silicon layer with an underlying charge trapping region (e.g., ONO) on an n substrate. The n substrate allows reproducible control of potential in the entire Fig. 2. Fabrication process sequence. (a) Donor p Si wafer with an ONO stack is implanted with a high dose of hydrogen (H ) approximately 600-nm deep into the silicon. (b) After CMP, the donor wafer is bonded at room temperature to a host consisting of an oxidized n Si wafer. (c) Hydrogen-induced exfoliation leaving a thin layer of p single-crystalline silicon on the host n wafer. (d) Standard CMOS techniques for transistor fabrication. Fig m20.6 m AFM scan showing the generic layout of the devices. structure, thus allowing suitable biasing schemes for transistor and memory operation. This substrate, a complex SOI substrate, is obtained using direct wafer bonding followed by a hydrogen-induced exfoliation for single-crystal silicon-layer transfer [9], [10]. The starting substrate is a low-doped silicon wafer with a thin grown thermal oxide (injection oxide), a deposited silicon nitride film and a low-temperature deposited silicon dioxide. The tunneling silicon oxide silicon nitride film interface and the nitride film provide the defected region for trapping of carriers. This donor wafer is then implanted with high dose of H. As an example, 3 10 cm dose at 140 kev forms a hydrogen-rich layer approximately 500-nm deep in the silicon [see Fig. 2(a)]. On a second silicon wafer, the host wafer, a silicon dioxide layer is thermally grown [see Fig. 2(b)]. An atomically smooth surface ( 0.3-nm rms roughness in m ), a smoothness obtainable either by chemical mechanical polishing (CMP) or by growth of oxide

72 266 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 3, NO. 2, JUNE 2004 Fig. 4. SEM cross-sectional image of a backside trapping SONOS memory array. ONO stack is 8, 15, and 40 nm, respectively. on prime substrates, is a prerequisite for formation of a strong bond between the donor and host wafers. The two wafers are directly bonded under vacuum at room temperature using a wafer bonder with a force of 1000 N [see Fig. 2(c)] and the bond is strengthened through a low-temperature anneal. Under a higher temperature anneal (400 C), the hydrogen microcavities, located at the projected range of hydrogen ions in the donor wafer, cause the donor wafer to cleave leaving a rough ( 10-nm rms roughness) single-crystal silicon layer bonded onto the host wafer [see Fig. 2(d)]. This silicon layer can then be thinned to the final desired thickness by CMP followed by oxidation or by CMP alone. In our example processes, final 50- and 20-nm layers of silicon were obtained by CMP from an initial 500-nm-thick silicon layer obtained after the hydrogen-induced exfoliation. In the research reported here, we employ back-trapping stacks consisting of injecting oxide, nitride, and control oxide films of 7, 20, and 100 nm in one set of devices and 2, 6, and 14 nm in a second set of devices. The devices are fabricated using standard CMOS techniques with mixed lithography (optical and electron beam) for obtaining the smallest dimensions. Fig. 3 shows a topographical atomic-force microscope (AFM) image of a device after deposition of the passivation oxide and after the metal via contacts were formed. Fig. 4 shows, through a scanning-electron microscope (SEM) cross section, the underlying insulator stack in a multigate-fingers geometry. The structures have smallest physical gate lengths in the nm range. The effective gate length is smaller than the physical gate length due to the underlapping source and drain extension regions. The devices were fabricated with no additional channel doping. Use of this doping will substantially improve the sub-threshold characteristics of devices. We estimate the boron doping level of the p active silicon to be 8 10 cm and the arsenic doping level of the n substrate to be 5 10 cm. Fig. 5 shows a cross-sectional SEM image of a thin single-crystal silicon layer above the back insulating films stack. In this figure, the silicon substrate was etched for shallow trench isolation (STI) of the devices, and the cross section shows the active region of devices. III. RESULTS AND DISCUSSION The experimental characteristics of fabricated devices show the unique dual-use properties of this structure. Fig. 6 shows the low-voltage transfer characteristics in the erased and written states obtained with high-voltage biasing and the output characteristics of a m physical gate-length structure. The transistor characteristics have an ratio larger than 10 and sub-threshold slope of 97 mv/decade in the erased state and Fig. 5. SEM cross-sectional image of a thin single-crystal silicon layer, approximately 15 nm, on an ONO stack. 80 mv/decade in the written state. At 100-nA current drive, a memory window of 0.68 V is obtained. The front-gate oxide is 7-nm thick, the back ONO stack is 7, 20, and 100 nm, respectively, and the active silicon layer is approximately 50 nm. The sub-threshold slope of our structures is constrained by the front-gate oxide thickness that is 7 nm and by the absence of channel doping in the 50-nm-thick silicon active region. The thick-back ONO stack used in the first set of devices, of the order of 100 nm, imposes the use of very large programming voltages in order to achieve appreciable tunneling between the active silicon and storage centers in the oxide and nitride. Voltages in the order of 50 V, corresponding to an applied field of 4 MV/cm, were used to program these devices. The minimum pulse duration we can apply at these high voltages is approximately 300 ms, and this is not indicative of the minimum writing or erasing times in these devices, but rather a limitation of our measurement setup. The charge for write state in these characteristics is injected into the trapping layer using FN tunneling. The substrate (an effective back gate) is biased, and the front gate, source, and drain are grounded. For the 0.68-V threshold-voltage shift in this structure, we estimate that there exists a trapped charge density of cm in the back insulator stack if we assume its locale to be the oxide nitride interface. Note that the estimated trapped charge density from front ONO measurements is in the mid-to-high 10 cm range. Thus, a significantly larger charge, which will cause a larger memory window, can be injected, and it is only limited in this case by the 100-nm oxide thickness employed for control oxide. The charge is also removed from the oxide nitride oxide stack by FN tunneling by applying 35 V to the back gate and grounding the front gate, source, and drain. In both the write and erase conditions, there is no voltage applied between any of the front transistor terminals. Thus, no significant damage of the

73 SILVA AND TIWARI: NANOSCALE MEMORY AND TRANSISTOR USING BACKSIDE TRAPPING 267 Fig. 7. Effect of back-gate bias in the erased (left-hand-side set) and written (right-hand-side set) states of a backside trapping memory. V = 02, 01, 0, +1, +2 V, from right- to left-hand side in each set. V = 1 V. W/L = 5:0 m=0:75 m. The front-gate oxide is 7-nm thick, the back ONO stack is 7, 20, and 100 nm, respectively, and the active silicon layer is approximately 50 nm. The same write and erase conditions were used as before. Fig. 6. Transistor and memory operation of a backside trapping memory. W/L = 3m=0:75 m. Front-gate oxide is 7-nm thick and back ONO stack is 7, 20, and 100 nm, respectively. Silicon thickness is 50 nm. (a) Transfer characteristics in erased (open symbols) and written (solid symbols) states with V = 1 V. Sub-threshold slope is 97 mv/decade in the erased state and 80 mv/decade in the written state. The memory window at 100 na is 0.68 V. The write and erase voltages were +50- and 035-V 300-ms pulses applied to the back gate, while front gate, source, and drain were grounded. (b) Output characteristics for the same device in the written state at V =0; 0:1; 0:2; 0:3; 0:4; 0:5 V. front transistor is to be expected. Since the charge is stored between the silicon channel and back gate, and the device state is read using the front gate, a much smaller read disturbance is to be expected in these devices when compared to front-side trapping memory cells. For the same ONO thickness for front and back SONOS memories, the smaller read disturb effect will, in principle, lead to better overall retention and reliability characteristics of the backside trapping devices. Fig. 7 illustrates the effect of the back-gate bias on the characteristicsofthefronttransistorin theerasedstate(left-hand-sideset of curves) and written state (right-hand-side set of curves) of the device. For both the erased and written states, five transfer curves are obtained with five different back-gate applied voltages, 2, 1, 0, 1, and 2 V. The fact that the threshold voltage shifts due to the back-gate bias are much larger in the erased state than in the written state is evidence that charges are indeed stored in the back, between the silicon channel and back gate, causing an efficient shielding of the back-gate bias on the front device characteristics. In order to test the endurance of these memory cells, multiple write/erase cycles were applied and the erased and written char- Fig. 8. Threshold voltage in the erased (open symbols) and written (solid symbols) states of a backside trapping memory device after up to 10 write/erase cycles. W/L = 3:0 m=1:0 m. The write and erase voltages are +50 and 035 V applied to the back gate for 300 ms. The front gate, source, and drain are grounded during both write and erase operations. The back ONO stack is 7, 20, and 100 nm, and the active silicon layer is approximately 50-nm thick. The same write and erase conditions were used as before. acteristics continually reproduce, approximately maintaining a good memory window larger than 0.6 V up to 10 write/erase cycles (Fig. 8). The written state of the device is very stable with minimal reduction or increase of threshold voltage after repeated cycling. The erased state is somewhat more erratic, with threshold voltage variations up to 0.2 V, but still maintains a reasonably wide memory window for the range of cycling tested. The variations observed in the erased state threshold voltage, and the very stable threshold voltage in the written state, were observed in all measured devices and seem to be inherent properties of this storage type. Further characterization of the programming, erasing, and retention times, at smaller time scales, will hopefully contribute to a better understanding of the physical mechanisms responsible for this behavior. The retention characteristics of a memory device for both written and erased states are plotted in Fig. 9. After an initial loss of charge that causes a minimal drop in threshold voltage

74 268 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 3, NO. 2, JUNE 2004 Fig. 9. Retention-time characteristics. Threshold voltage as a function of the time elapsed after a 300-ms writing pulse of +50 V (solid symbols) and after a 300-ms erasing pulse of 035 V (open symbols) applied to the back gate. W/L = 1:5 m=0:75 m. The device was kept at room temperature during the entire measurement period. Fig. 11. Memory window for a W/L = 200 nm=100 nm backside trapping device. The sub-threshold slope is 117 mv/decade in the erased state (open symbols) and 96 mv/decade in the written state (solid symbols). The front-gate oxide is 7-nm thick, the back ONO stack is 2, 6, and 14 nm, respectively, and the active silicon layer is approximately 20-nm thick. The programming voltages used in this example were +10= 0 10-V pulses applied to the back gate. Fig. 10. Memory window for a W/L = 200 nm=150 nm backside trapping device. The sub-threshold slope is 127 mv/decade in the erased state (open symbols) and 94 mv/decade in the written state (solid symbols). The front-gate oxide is 7-nm thick, the back ONO stack is 2, 6, and 14 nm, respectively, and the active silicon layer is approximately 20-nm thick. The programming voltages used in this example were +10= 0 10 V pulses applied to the back gate. of approximately 20 mv, the charge loss is very slow, holding promises of long retention times in these backside trapping memories. The initial charge loss may be due to residual charges that are stored in the tunneling oxide closer to the silicon channel and that tend to tunnel back into the silicon channel even when a small front-gate read voltage is applied. The erased state also shows good retention and the small increase in threshold voltage with time is possibly due to an initial over-erasure of the device. A memory window larger than 0.5 V is maintained up to 10 s, which is approximately 12 days. High-temperature measurements are needed in order to test the minimum requirements of ten years for nonvolatile applications, but, again, since the charge is stored in the back of the read transistor, minimal read disturb effects are expected to lead to longer retention times in these devices when compared to front SONOS memories. Figs. 10 and 11 show memory characteristics for shorter gate-length devices, 150 and 100 nm, respectively, in which Fig. 12. Transfer characteristic for a W/L = 100 nm=50 nm front transistor. Sub-threshold slope is 72 mv/decade. The front-gate oxide is 7-nm thick, the back ONO stack is 2, 6, and 14 nm, respectively, and the active silicon layer is approximately 20-nm thick. the front-gate oxide was kept 7-nm thick, but the back ONO stack was reduced to 2, 6, and 14 nm, respectively, allowing the use of standard programming voltages in the range of V. For the 150-nm gate-length device, the sub-threshold slope is 127 mv/decade in the erased state and 94 mv/decade in the written state, and the memory window is 0.67 V with 300-ms write/erase pulses of V applied to the back gate. For the 100-nm gate-length device, the sub-threshold slope is 117 mv/decade in the erased state and 96 mv/decade in the written state and the memory window is 0.78 V, with the same programming conditions. The sub-threshold slope variations are indicative of nonuniformities in the fabrication process. The active silicon layer in these devices was thinned to approximately 20 nm, which makes for better coupling between the charge stored at the back and front transistor channel and permits close to ideal sub-threshold slopes down to 50-nm gate-length transistors (Fig. 12). There is still no additional channel implant, and the sub-threshold slopes are indicative of the improvements made possible by the use of a thinner silicon layer.

75 SILVA AND TIWARI: NANOSCALE MEMORY AND TRANSISTOR USING BACKSIDE TRAPPING 269 Due to the high density of defects in oxide nitride films, even small devices can store large amounts of charge. The device shown in Fig. 12, i.e., 100 nm 50 nm, is estimated to have approximately 500 trapping sites for storage, thus providing a device-to-device reproducibility in small nonvolatile memories. In order to determine the viability of these structures, the writing and erasing times must also be characterized. However, since these depend mainly on the injection oxide, nitride, and control oxide thickness, these time scales are likely to be quite comparable to those of front SONOS devices with some potential additional advantages accrued from the uniformity and absence of damage due to CMOS processing in the backside trapping region. Doping the channel, reducing the front-gate oxide, and further thinning the active silicon channel will lead to improvements in the sub-threshold slope of the front transistor to nearideal values, making for high-performance standard logic devices at tens of nanometers gate lengths. For the memory function of the device, the thinning of the back-trapping films thickness, as well as the thinning of the silicon active channel, can reduce the writing and erasing voltages and increase the memory window, but, as with the front-floating structures, there will be retention and reliability issues associated with such a design. [2] D.-C. Kim, W. C. Shin, J.-D. Lee, J.-H. Shin, J.-H. Lee, S.-H. Hur, I.-G. Baik, Y.-C. Shin, C.-H. Lee, J.-S. Yoon, H.-G. Lee, K.-S. Jo, S.-W. Choi, B.-K. You, J.-H. Choi, D. Park, and K. Kim, A 2 Gb NAND flash memory with m cell size using 90 nm flash technology, in Int. Electron Devices Meeting Tech. Dig., 2002, pp [3] C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Hoefler, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, and J. A. Yater, An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase, in Int. Electron Devices Meeting Tech. Dig., 2002, pp [4] S. J. Wrazien, Y. Zhao, J. D. Krayer, and M. H. White, Characterization of SONOS oxynitride nonvolatile semiconductor memory devices, Solid State Electron., vol. 47, pp , [5] J. Bu and M. H. White, Design considerations in scaled SONOS nonvolatile memory devices, Solid State Electron., vol. 45, pp , [6] S. Tiwari, CMOS SOC compatible memories, Patent Applicat., [7] A. Kumar and S. Tiwari, Scaling of flash NVRAM to 10 s ofnmby decoupling of storage from read/sense using back-floating gates, IEEE Trans. Nanotechnol., vol. 1, pp , Dec [8] J.-P. Colinge, Silicon-on-Insulator Technology. Norwell, MA: Kluwer, 1997, pp [9] M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A. J. Auberton-Herve, J. M. Lamure, T. Barge, F. Metral, and S. Trucchi, Smart cut, a promising new SOI material technology, in Proc. IEEE Int. Silicon-on-Insulator Conf., 1995, pp [10] L. Xue, C. C. Liu, H.-S. Kim, S. K. Kim, and S. Tiwari, Three-dimensional integration: technology, use, and issues for mixed-signal applications, IEEE Trans. Electron Devices, vol. 50, pp , Mar IV. SUMMARY A new device structure that can be operated both as a scaled nonvolatile memory cell and as a scaled transistor has been demonstrated. This device is based on backside trapping, i.e., the charge storage medium, an ONO stack in this case, is placed at the back of a thinned silicon channel. By appropriate biasing of front gate, source, drain, and back gate, charge can be injected or removed from this medium causing a change in the potential distribution in the structure that is observed as a threshold voltage shift between the erased (without charge) and written (with charge) states of the device. The use of an ultra-thin silicon body in this structure will allow an optimized use of the dual character of these geometries, better front-gate control at very short gate lengths for the front transistor, and better coupling between active silicon channel and back gate for more efficient injection and removal of charge and for larger effect of this charge in the characteristics of the front transistor (larger memory window). This new geometry provides a device that is capable of performing both logic and memory functions, which may lead to higher densities, lowering of the technology cost, and possibly different architectures in memory and logic integration circuitry. REFERENCES [1] B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F.-F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H.-S. P. Wong, and W. Haensch, Extreme scaling with ultra-thin Si channel MOS- FETs, in Int. Electron Devices Meeting Tech. Dig., 2002, pp Helena Silva received the B.S.E. degree in engineering physics from the Technical University of Lisbon, Lisbon, Portugal, in 1998, the M.S. degree in applied physics from Cornell University, Ithaca, NY, in 2002, and is currently working toward the Ph.D. degree in applied physics at Cornell University. Her research focuses on the role of defects in small devices and on defects-based memories for scalable semiconductor nonvolatile memories. Sandip Tiwari (S 76 M 80 SM 87 F 94) is currently Professor of Electrical and Computer Engineering at Cornell University, Ithaca, NY, Lester B. Knight Director of Cornell Nanofabrication Facility, and Director of National Nanofabrication Users Network. His current research interests are mall devices and their circuits, ideas and technologies that allow functional integration, and interesting offshoots of small structures in other areas. He was a Research Staff Member and Manager for exploratory devices and device modeling at IBM. He has held visiting and adjunct faculty appointments with The University of Michigan and Columbia University. He authored the textbook Compound Semiconductor Device Physics (Boston, MA: Academic, 1992). Among his contributions and inventions that have found large industrial application and research interest are nanocrystal and quantum-dot low-power embedded memories, vertical transistors in multigigabit dynamic random access memory (DRAM) memories, and the technology of HBTs used in wireless applications. Dr. Tiwari is the editor-in-chief of the IEEE TRANSACTIONS ON NANOTECHNOLOGY. He is a Fellow of American Physics Society (APS). He was the recipient of the 1991 Young Scientist Award presented by the Institute of Physics.

76 APPLIED PHYSICS LETTERS 96, A universal semiempirical model for the Fowler Nordheim programming of charge trapping devices Ravishankar Sundararaman 1,a and Sandip Tiwari 2 1 Department of Physics, Cornell University, Ithaca, New York 14853, USA 2 School of Electrical and Computer Engineering, Cornell University, Ithaca, New York 14853, USA Received 3 August 2009; accepted 6 December 2009; published online 14 January 2010 An approximate analytical solution to the dynamics of charge trapping and detrapping by Fowler Nordheim tunneling is constructed within a simplified model that captures the essential features of the programming characteristics of tunneling devices with the fewest possible parameters. This solution is demonstrated to be an excellent fit for experimental programming characteristics of various tunneling-based nonvolatile memory devices from different laboratories including devices based on traps in silicon nitride, interface traps in silicon dioxide, and silicon nanocrystals American Institute of Physics. doi: / The time scales and energy scales in writing and erasing floating charge memories, such as polycrystalline silicon floating gate Flash, nanocrystal, and those incorporating defects, have a large spread. Bias voltages, work functions, defect state energies and their capture cross-section, etc. all affect the timing. Many varieties of defects may also exist. Modeling the characteristics of these structures is further complicated by the inherently two-dimensional geometry and the large number of variables involved, some of which are not known. These complexities have been bypassed by employing a multivariable optimization approach that combines a simple physical model with experimental characteristics to extract essential parameters. This allows one to ignore details of the defect characteristics and atomic scale effects at interfaces while achieving accuracy. The power of this approach is that the bias and time dependences can be modeled over a large range with physically meaningful parameters, and its applicability is shown for a variety of device structures in which floating charge is employed to make nonvolatile memories. This is useful in planning experiments for desired characteristics and in modeling of circuits. The analytical model is derived by considering the programming characteristics of the abstracted device shown in Fig. 1. A fraction of the carriers f cap tunneling from the substrate in field D get trapped and develop a sheet charge density Q in the trap layer. As Q increases, field D reduces while D increases; and ultimately the tunneling current out of the trap layer becomes comparable to the trapping rate, leading to saturation. The threshold voltage shift is V t =d el Q. Modeling the tunneling via the Fowler Nordheim FN relation, the dynamics of trapping and detrapping can be expressed as follows: a Electronic mail: [email protected]. dq dt = f capa 0 D 2 e A 1 /D Q e A1 /D, 1 where A 0 is the prefactor and A 1 the exponential field scale for the FN tunneling involved in trapping and is the trap frequency and A 1 the exponential field scale for the detrapping process. For a true triangular barrier of height E b in a dielectric with band-mass m diel, A 1 =4 2mdiel E b /3e. For tunneling from a quadratic band with effective mass m eff, A 0 =m eff e 3 /8 m diel he b 2. Nonidealities may break these connections with the material parameters but the functional form of the field dependence used in Eq. 1 is likely to be unaffected. Hence we work only with these abstracted parameters in developing the model. Now Eq. 1 can be rewritten in terms of V t as follows: d dt V t = V gs V t 2 V V 0 exp 0 V gs V t V t exp V 0 t V gs + d, el d el V with V 0 =A 1 d el +d el, 1 = f cap d el A 0 A 2 1 /V 0, V 0 =A 1 d el +d el, and 1 =. In the absence of the detrapping term i.e.,, Eq. 2 can be analytically solved as follows: V t t = V gs V 0 /ln e V 0 /V gs + t. Equation 3 is approximately valid when the trapped charge is far from its saturation value. Saturation occurs when d V t /dt=0, and the saturated value V t sat can be written as a Taylor series in V gs /V 0 since V 0 V gs for practical bias voltages. Saturation is incorporated into Eq. 3 by replacing t with a function f sat t that smoothly switches from t to a FIG. 1. Device structure corresponding to the simplified trap-escape model. The model accounts for tunneling from the channel in electric displacement field D and escape from the trap layer in field D /2010/96 2 /023502/3/$ , American Institute of Physics Downloaded 25 Oct 2012 to Redistribution subject to AIP license or copyright; see

77 R. Sundararaman and S. Tiwari Appl. Phys. Lett. 96, constant value t sat such that V t t sat = V sat t. Thus V t = V gs V 0 /ln e V 0 /V gs + f sat t with f sat t = t + t sat 1/, t sat = e V 0 /V gs V t sat V gs e V 0 /V gs and V sat t V gs + V gs 4 V 0. By comparing Eq. 4 to an asymptotic solution of Eq. 2 near saturation = V 0 /V 0 1 V 0 /V 0 + d el /d el, = d 2 elv 0 1 d el V 0 1+ d el /d el and 1 1+ d el d el = Threshold voltage Shift (V) Write Time (ns) V 0 + d el V 0 d el ln 1 2 V 0 typ V gs V gs=8v V gs=10v V gs=12v V gs=14v V gs=16v V gs=18v V gs=20v V gs=22v FIG. 2. Color online Comparison between the approximate analytical solution Eqs. 4 and 5 with the numerical solution of Eq. 2. This plot was generated for V 0 =300 V, =10 6 s, V =400 0 V, = s and d el =d el.. 5 The model problem 2 was defined in terms of five parameters V 0,,V 0,,d el /d el, while the approximate analytical form 4 is in terms of V 0,,,,. Figure 2 shows the numerical solution of Eq. 2 together with the analytical form 4 for the values of,, and from Eq. 5 demonstrating the adequacy of this approximation. The analytical form 4 with undetermined parameters V 0,,,, fits the experimental FN programming characteristics of a wide range of nonvolatile memory devices. Figure 3 shows examples of accurate fits to the data from various groups with various types of trapped charge devices 1 3 for oxide-oxide and nitride-oxide traps a, b, and c and silicon nanocrystals 4 d. The fit accuracy is summarized in the caption of the figure. In contrast, for channel hot electron injection dominated programming characteristics, e.g., the NAND Flash devices from, 5 the parametrization is quite poor. In principle, Eq. 5 could be inverted and the fits expressed in terms of the physical parameters Threshold voltage Shift (V) Threshold voltage Shift (V) Threshold voltage Shift (V) Threshold voltage Shift (V) (a) Oxide-Oxide interface traps (b) Nitride traps, TaN gate (c) Nitride traps, metal gate (d) Silicon nanocrystal Write Time (ns) V gs= 9V V gs=10v V gs=11v V gs=12v V gs=13v V gs=14v V gs=10v V gs=12v V gs=14v V gs=16v V gs=18v V gs=20v V gs=13v V gs=14v V gs=15v V gs=16v V gs=17v V gs=14v V gs=16v V gs=18v FIG. 3. Color online Fit to the FN programming characteristics of a the oxide-oxide interface trap device Ref. 1 V 0 = V, = s, =0.14, =2.8, =2.4, Residual= V ; the nitride trap devices with Al 2 O 3 top dielectric and b TaN gate Ref. 2, Fig.11 V 0 = V, = s, =0.32, =0.12, =1.1, Residual = V and c metal gate Ref. 3, sample A V 0 = V, = s, =0.50, =0.37, = 0.1, Residual= V ; as well as d silicon nanocrystal memory of Ref. 4 V 0 = V, = s, =0.94, =0.15, = 4.4, Residual= V. V 0,,V 0,,d el /d el. However, this is limited by the high covariance of that set of parameters. It is advantageous to work with the semiempirical parameters instead, as they translate more directly to the shape of the experimental write curves as described below. The parameter sets an overall time scale for the write process, and V 0 controls the dependence of the characteristic programming time-scale on the bias voltage: the programming becomes relevant at t e V 0/V gs. These parameters are directly related to the prefactor and exponential scale factor of the FN trapping process, as mentioned in the explanation of Eqs. 1 and 2. The parameters and represent the first and second order dependence of the saturation threshold voltage shift on the bias, while is related to the sharpness of the transition from the initial write phase to the saturation phase. These parameters physically arise from a competition of the fielddependence of the trapping and escape processes; consequently they are functions of the ratio of the exponential scale factors for the two tunneling processes and the ratio of electrical distances to the trap layer, as indicated in Eq. 5. There are a large number of fundamental device and material parameters such as barrier heights, density of states, Downloaded 25 Oct 2012 to Redistribution subject to AIP license or copyright; see

78 R. Sundararaman and S. Tiwari Appl. Phys. Lett. 96, trap frequencies, effective masses, etc., which all affect the programming characteristics of the memory device. However the dependence of the write curves on all these properties can be succintly grouped as in the combinations indicated in Eq. 5 into the fit parameters introduced in this letter. Thus, it makes sense to describe different tunneling-based nonvolatile memory devices using these fit parameters instead. In summary, a compact five-parameter physical model that captures the essential features of the FN programming of a variety of nonvolatile memory devices has been presented. The parameters can be interpreted in terms of the field and time-scales of the tunneling and trap escape processes from which they are motivated. In addition, they serve to compare the performance of significantly different devices in a unified description which could be useful in predictions as devices are scaled and new dielectrics employed. 1 M. K. Kim and S. Tiwari, Int. J. High Speed Electron. Syst. 17, C. M. Compagnoni, A. Mauri, S. M. Amoroso, A. Maconi, and A. S. Spinelli, IEEE Trans. Electron Devices 56, E. S. Choi, H. S. Yoo, K. H. Park, S. J. Kim, J. R. Ahn, M. S. Lee, Y. O. Hong, S. G. Kim, J. C. Om, M. S. Joo, S. H. Pyi, S. S. Lee, S. K. Lee, and G. H. Bae, 22nd IEEE Non-Volatile Semiconductor Memory Workshop, 2007 unpublished, Vol C. Gerardi, G. Molas, G. Albini, E. Tripiciano, M. Gely, A. Emmi, O. Fiore, E. Nowak, D. Mello, M. Vecchio, L. Masarotto, R. Portoghese, B. De Salvo, S. Deleonibus, and A. Maurelli, Tech. Dig. - Int. Electron Devices Meet. 2008, T. Kamigaichi, F. Arai, H. Nitsuta, M. Endo, K. Nishihara, T. Murata, H. Takekida, T. Izumi, K. Uchida, T. Maruyama, I. Kawabata, Y. Suyama, A. Sato, K. Ueno, H. Takeshita, Y. Joko, S. Watanabe, Y. Liu, H. Meguro, A. Kajita, Y. Ozawa, T. Watanabe, S. Sato, H. Tomiie, Y. Kanamaru, R. Shoji, C. H. Lai, M. Nakamichi, K. Oowada, T. Ishigaki, G. Hemink, D. Dutta, Y. Dong, C. Chen, G. Liang, M. Higashitani, and J. Lutze, Tech. Dig. - Int. Electron Devices Meet. 2008, 827. Downloaded 25 Oct 2012 to Redistribution subject to AIP license or copyright; see