90nm e-page Flash for Machine to Machine Applications

Transcription

1 90nm e-page Flash for Machine to Machine Applications François Maugain, Jean Devin Microcontrollers, Memories & Secure MCUs Group

2 90nm e-page Flash for M2M applications Outline M2M Market Cycling Endurance Intrinsic Retention after Cycling Extrinsic Retention after Cycling Applicative Implementation 2

3 Wireless M2M M2M establishes wireless communication between a machine and the service centre of a business Machine Wireless module Mobile Network Gateway Internet Service centre 3

4 Market Applications Telematics OEM telematics (ecall) After market (Pay-As-You-Drive insurance offers) Commercial (Fleet management) Telemetry AMI (Advanced Metering Infrastructure), Smart Metering Security, Remote monitoring, Tele health, Remote info display, WLL (Wireless Local Loop) FWT: Wireless terminal limited to permanent location Industrial PDA Car crash Fleet tracking Smart Grid ecall Security Emergency hot line Healthcare Rescue Service 4

5 Global M2M Modules shipment by Application Source: ABI Research, Cellular M2M Markets, 3Q

6 Secure MCU for M2M based on ETOX NOR Page Flash Cost effective High density Mixed code and parameter storage Flexible Erase granularity (128 bytes) Fast page erase time (3ms) Compatible with intensive cycling - more than 500K cycles per page (hardware) Low Power Scalable Reliable Extensive re-use of automotive oriented process technology and design Excellent intrinsic data retention Full program/erase stress cancellation thanks to embedded algorithm Capability to address highly reliable applications (automotive, health) 6

7 Dedicated ST specifications for M2M range Range Telecom M2M Temperature -25dC / +85dC -40dC /+105dC Cycling 100K cycles/ page 25M cycles per sector 500K cycles/ page 50M cycles per sector Retention 10 years years@ 105dC Retention after cycling N.A. 10 years (typical application profile) ST32F512 1 page = 128bytes 1 sector = 512 pages 1 sector = 64KBytes 7

9 Page Flash cycling endurance Sector aging profile Refresh counter Read Margins Page Erase time Word programming time data (cycled) Cycles (log) Cycles (log) Cycles (log) Disturb code Disturb Canceled by Read margin Embedded refresh Cycles (log) Cycles (log) 50M page erase operation per sector (512 pages) 500K cycles on 100 pages 100K cycles on all pages 9

10 Page Flash cycling endurance Product settings : performance vs reliability Distributions guarantied by reference cells & algorithms Nbits Vth distribution Depletion Verify Erase Verify Read Program Verify Vt Read Margin Benefit Tradeoff Erase time & disturbs Retention Cycling Programming time & disturbs 10

12 Retention after cycling Physical mechanisms Cycling Trap generation & filling - source control gate interpoly dielectric floating gate - x x x bulk tunnel ox drain cell density 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 Retention after cycling - Vt drift Before retention bake After retention bake Extrinsic population Poly1 Floating Gate Intrinsic drift Vg (V) Pure Retention Direct tunneling - Negligible Trap assisted tunneling - Extrinsic population - Ea ~0.65eV - Cell state dependent Retention after cycling Charge de-trapping - Intrinsic mechanism - Ea ~ 1.1eV - Low cell state sensitivity - Finite charge loss 12

13 Retention after cycling Intrinsic charge de-trapping Electron de-trapping whatever cell state : negative Vt shift Worst case conditions : retention on Nbcells after 100K cycles 2-after 24hrs@150dC Vth Distribution after 100K cycles and retention bake de-trapping Read level Vg (V) Reduced Vt shift after retention trial repetition de-trapping Vth Distribution after 100K cycles, relaxation and retention bake 3-after few cycles and reprograming 4-after 24hrs@150dC Nbcells Vg (V) 13

14 Retention after cycling Relaxation effects Tunnel oxide electron trapping/de-trapping induces bias in data retention Charges are partly de-trapped between cycles (relaxation) Cell Vt Cycling one shot Program Verify Distributed cycling Low de-trapping rate Cycling phase Read Verify Retention Phase Strong de-trapping effect Time Application profile is a key parameter Intensive cycling followed by long retention phase is not realistic Typical application profile : distributed cycling continuous de-trapping Classical qualification trials not representative Qualification trials must take relaxation into account Realistic application profile : cycling over 5 yrs, 10yrs retention 14

15 Retention after Cycling Relaxation effects Relaxation effect is independent of cell state for data retention Nbcells Vt shift on 1 less after relaxation on 1 Vt distribution after cycling and relaxation dv 1 Vt shift on 0 identical after relaxation on 1 or 0 0 Vt shift ev Read level Vg [V] pv Vt shift 90KC_RelaxFF_10KC_FF 90KC_RelaxFF_10KC_00 90KC_Relax00_10KC_FF 90KC_Relax00_10KC_00 Cycling Relaxation Retention equivalent Vt shift not critical 15

16 Retention after Cycling Relaxation Effect Modeling Retention charge loss after cycling can be simply modelized by Unified De-trapping Metric (N. Mielke) UDM = cycle *ln 1+ 1 t A t bake cycle exp Ea k 1 T cycle 1 T bake This allow to build a qualification trial equivalent to the mission profile : Mission Profile UDM Qualification trial Charge de-trapping parameters Ea ~ 1.1eV confirmed A = de-trapping efficiency Specific case Constant temperature profile Tcycle = Tbake AverageVt of less programmed after 100kcycles + bake Initial Vt = 6.2V 6200 Vgmax (mv) dC 150dC 85dC 25dC Bake Duration (hrs) 16

17 Intrinsic Retention after Cycling Experimental Trial Equivalence Mission Profile :100K, 5 years cycling + 10 years 85dC 100K Retention 0yrs Total Cycling 100K T=85dC 5yrs Retention T=85dC 15yrs Equivalent Qualification trial 90K Relaxation 10K reprog. Retention Fast Cycling 96hrs T=25dC Bake 168hrs@150dC Distributed Cycling 500hrs T=105dC Retention Bake 500hrs T=150dC 90K Relaxation 10K Relaxation 100c+reprog. Retention Fast Cycling 96hrs T=25dC Bake 7hrs@200dC Fast Cycling 4hrs T=25dC Bake 19hrs@150dC Retention Bake 500hrs T=150dC 100K Relaxation 1Kc+reprog. Retention Fast Cycling 168hrs T=25dC Bake 168hrs@150dC Retention Bake 500hrs T=150dC 17

18 Retention after Cycling Process Capability Retention vs Cycling duration for 100K ( Tcycling = Tretention ) Retention after 100K cycles for constant temperature profile 100 Cycling period Time between cycles 360ms 3.6s 36s 6min 1hr 1.E+06 Application Profile Risk Assessment 10 1.E+05 [years] Retention (yrs) E+04 1.E+03 1.E+02 Retention [hrs] (hrs) Examples 100K cycles over 5 85dC Retention >10 yrs 1 cycle every 6 105dC Retention > 1 year T=105dC T=85dC T=55dC T=25dC 1.E+01 1 cycle every 10 25dC Retention > 10 year (25dC) E Total CyclingTime for 100K cycles [years] Total cycling time for 100K cycles (yrs) 18

20 Retention after cycling Extrinsic failure rate assessment Risk assessment and ECC needs Extrinsic population (trap assisted tunneling) is masked by intrinsic de-trapping mechanism Low activation energy Strong electric field sensitivity One shot trial cycling/retention not suitable Preconditioning by extended relaxation bake needed Failure rate parameters Parameter Temperature Time Read voltage Defect Density Acceleration Ea ~ 0.65 ev 1.2 decade / decade time 1 decade / V Failure rate after 100 kcycles typically 0.1 PPM after 10yrs@85dC cumulated cell density 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 Cumulated cell density vs Vg Tbake =150dC / 310 Mcells Initial 72hrs 500hrs Critical read voltage Vg (V) 20

21 Extrinsic retention after cycling Annealing effects No annealing at 150dC Strong annealing at 200dC 1.E+00 1.E-01 Cumulative cell density (120Mcells) Repeatability vs Tbake=150dC/150dC Trial1 - Initial Trial1-500hrs@150dC 1.E+00 1.E-01 Cumulative cell density (71Mcells) Repeatability vs Tbake=150dC/200dC Trial1 - Initial Trial1-500hrs@150dC cumulative cell density 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 Trial2 - Initial Trial2-500hrs@150dC Unchanged extrinsic failure rate cumulative cell density 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 Trial2 - Initial Trial2-500hrs@200dC Few extrinsic cells at 200dC 1.E-08 1.E-07 1.E Vg(V) 1.E Vg(V) Extrinsic build in defects cured by bake at 200dC Qualification trial temperature max 150dC 21

22 Retention after cycling Qualification procedure summary Application profile definition Cycling conditions (number, frequency, temperature) Retention requirement (temperature, duration) Accelerated Cycling Relaxation Bake Intrinsic retention Retention pattern write (user) Retention bake Retention check (user) Intrinsic Vt drift monitor Nbits Read User RV PV Distribution after bake Initial Vt distribution Vg Extrinsic failure rate assessment Additional relaxation optional Specific preconditioning : over programming Retention bake, various durations Fail density / PPM extrapolation Include intrinsic offset Nbits Read User RV PV fail density Vg 22

24 Page flash endurance Applicative implementation vs Reliability Relaxation between cycles lower stress Improved program & erase efficiency Lower electrical stress Improved read margin Constant temperature profile worst in most case T(operating, relaxation) > T(idle, retention) Hardware Refresh Algorithms Electrical disturbs cancellation Benefit for retention Software implementation for extended requirements Wear leveling Software ECC on critical data 24

25 EFTL: Embedded Flash Translation Layer General presentation EFTL software layer manages a part of the flash memory Wear Leveling management between physical pages (distributed cycling) Extended cycling (up to 130 Mcycles) Anti tearing management Accelerated write access / garbage collection OS & Applications logical space Logical block access S/W Read EFTL EFTL Prog. / Erase Drivers Read descriptors metadata H/W Flash Executable Code (native access) General Data (EFTL control) physical space 25 25

26 Conclusion 90nm e-page Flash well suited to address new markets with extended reliability targets Retention after cycling fully covered by adapted qualification methodology Several tens of million cycles achieved with e-ftl Possible updates every 5 second during 20 years 26

27 Thank You! Any Questions? 27

28 References JESD 22-A117B, March 2009 Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling Mielke et al. Intel Corporation IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 3, SEPTEMBER