Dr. Tom Kean Principal Consultant Algotronix Ltd. Phone: Fax: Web:

Transcription

1 Resume Dr. Tom Kean Principal Consultant Algotronix Ltd. Phone: Fax: Web: Professional Experience The principal of Algotronix, Dr. Tom Kean has been involved with all aspects of Field Programmable Gate Array (FPGA) technology since Dr. Kean currently holds twenty United States patents in FPGA architecture with a number of patent applications pending and has published many technical papers on FPGA architecture and applications of FPGA chips to computing problems. He has been an invited speaker at international conferences on programmable logic and reconfigurable computing, regularly reviews papers in this area for IEEE journals and has been an external examiner on PhD theses. He is currently a member of the program committee of the IEEE FCCM, ACM FPGA and the European FPL conferences on FPGAs. Dr. Kean is a member of the ACM and IEEE and holds the BSc Honours (summa cum laude) and PhD degrees in Computer Science from the University of Edinburgh, Edinburgh, Scotland. Dr. Kean regularly provides due diligence consulting services to UK based venture capitalists focussing on fabless semiconductor and semiconductor intellectual property opportunities. Dr. Kean presently consults to leading US legal firms and corporations on technical aspects of patent litigation relating to programmable logic and its applications (infringement and prior art analysis). Dr. Kean acted as an expert witness for Cadence in recent litigation with Mentor Graphics which resulted in a jury verdict in US Federal Court dismissing all charges brought by Mentor. Dr. Kean also acted as a fact witness for Xilinx in patent litigation before the US International Trade Commission. Dr. Kean advises various companies on product positioning and the acquisition of semiconductor IP in the programmable logic area.

2 Prior Employment From 1985 to 1989, Dr. Kean was a PhD student at Edinburgh University. His thesis concerned the architecture and implementation of a cellular FPGA device for computing applications. During this project SRAM and mask programmed versions of the device were fabricated and tested and CAD software tools were written. This work was some of the earliest research into CMOS based FPGA chip architectures and the first to specifically consider using FPGA chips for computation. From 1989 to 1993, he was technical director of Algotronix Ltd. a start-up company formed to exploit the research in his PhD. In that role he was responsible for the silicon implementation of the CAL1024 FPGA chip, the CHS2x4 custom computer and various demonstration applications and items of CAD software. These products are widely recognised as pioneering the use of FPGA's in computing applications. In autumn 1993 Algotronix was purchased by Xilinx Inc. and Dr. Kean took on the position of Manager of Silicon Design in the XC6200 product group. In that role he defined the XC6200 architecture and managed the group of silicon design engineers implementing the XC6200 FPGA family. XC6200 chips were taped out to four separate processes and three manufacturing partners. Four family members were designed, three of which went into production. His group was also responsible for the PCI bus based XC6200 development system which was licensed to two partner companies and was widely used in the research community. His group also developed a variety of demonstration applications for the XC6200 in the areas of signal processing, image processing and cryptography. The XC6200 was the first FPGA chip to emphasise dynamic reconfiguration of the control store and communication of data between a processor and user circuitry implemented on the FPGA. It also introduced a hierarchical interconnect structure for FPGA chips. The XC6200 architecture has significantly influenced later generations of Xilinx products including Virtex and Virtex II. In 1997 he was given overall responsibility for technical leadership of silicon design, applications and CAD software for Xilinx s facility in Edinburgh, Scotland. One of his main responsibilities in that role was feasibility studies related to new products. In 1998 as a result of a re-organisation within Xilinx Dr. Kean left Xilinx to reform Algotronix as a consulting company offering impartial advice to investors in fabless semiconductor and semiconductor IP companies. 2

3 Publications Published US Patent Applications Dr. Kean is a named inventor on the following U.S. patent applications. All these patent applications are assigned to Algotronix Ltd.. 1. Method of Protecting Intellectual Property Cores on Field Programmable Gate Array, Publication No. US 2002/ Method of Using a Mask Programmed Key to Securely Configure a Field Programmable Gate Array, Publication No. US 2001/ Method and Apparatus for Secure Configuration of a Field Programmable Gate Array, Publication No. US 2001/ Issued US Patents Dr. Kean is a named inventor on the following U.S. patents. All these patents are assigned to Xilinx Inc.. 1. "Configurable cellular array", US Patent 5,243, "Hierarchically connectable configurable cellular array", US Patent 5,469, "Configurable cellular array", US Patent 5,491, "Wildcard addressing structure for configurable cellular array", US Patent 5,500, "Register with duplicate decoders for configurable cellular array", US Patent 5,528, "Mask register for a configurable cellular array", US Patent 5,552, "Register Protection Structure for FPGA", US Patent 5,600, "Circuit for simultaneously inputting and outputting signals on a single wire", US Patent 5,612, "High speed mask register for a configurable cellular array", US Patent 5,670, "Routing Resources for hierarchical FPGA", US Patent 5,701, "FPGA with parallel and serial user interfaces", US Patent 5,737,235 3

4 12. Match Register with Duplicate Decoders U.S. Patent 5,798, "Embedded memory for field programmable gate array", US Patent 5,801, "Function unit for fine-grained FPGA", US Patent 5,831, Hierarchically Connectable Configurable Cellular Array, U.S. Patent 5,861, "FPGA using RAM control signal lines as routing or logic resources after configuration", US Patent 5,909, FPGA using RAM control signal lines as routing or logic resources after configuration, US Patent 6,157, "Programmable Switch for FPGA input/output signals", US Patent 5,705,938 re-issued as US RE 37, Configurable cellular array, US Patent 6,292, FPGA using RAM control signal lines as routing or logic resources after configuration, US Patent 6,304,103 Papers 1. "Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation", PhD Thesis CST62-89, University of Edinburgh, Dept. Computer Science. 2. "Configurable Hardware, A New Paradigm for Computation'', Advanced Research in VLSI, Proc Decennial Caltech Conference, MIT Press. 3. "Configurable Hardware: Two Case Studies of Micro-Grain Computation'', Proc. International Conference on Systolic Arrays, Killarney 1989, Prentice Hall. 4. "Configurable Hardware: Two Case Studies of Micro-Grain Computation'', Journal of VLSI Signal Processing 2, 9-16, Kluwer Academic Publishers. 5. "A Novel Implementation Style for Teaching VLSI'', Proc VLSI Education Conference, Santa Clara, July "Image Pattern Recognition using Configurable Logic Cell Arrays'', Proc. Computer Graphics International, Leeds Published by Springer- Verlag. 7. "Implementation of Configurable Hardware using Wafer Scale Integration'', Proc. International Conference on Wafer Scale Integration "Bipolar CAL Chip Doubles Speed of FPGA's'', Proc. Oxford 1991 International Workshop on FPGA's, Abingdon EE &CS Books England. 4

5 9. "The Use of FPGA's in a Novel Computing Subsystem'', Proc. FPGA 1992 First International ACM Workshop on Field Programmable Gate Arrays, Berkeley CA. 10. "Using CAL to Accelerate Maze Routing of CAL Designs'', Field Programmable Logic and Applications, Proc. 2nd International Workshop. Vienna, Austria Chapter 3 and sections of chapter 6 in " Field Programmable Gate Arrays", John V. Oldfield and Richard C. Dorf, John Wiley "XC6200 Fastmap Processor Interface", Field Programmable Logic and Applications, Proc. 5th International Workshop. Oxford, Springer LNCS "A Fast Constant Coefficient Multiplier for the XC6200", Field Programmable Logic and Applications, Proc. 6th International Workshop. Darmstadt, Springer LNCS. 14. "An 800Mpixel/sec Reconfigurable Image Correlator on XC6216", Field Programmable Logic and Applications, Proc. 7th International Workshop. London, Springer LNCS "Reconfigurable Computing and the Xilinx XC6200", Invited Tutorial Paper, VLSI97, Gramado, Brazil "DES Key Breaking, Encryption and Decryption on the XC6216", Proceedings IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), Napa CA, "Soft RF: new frontier for hackers", EE Times, issue 1074, August 16, "Its FPL Jim - But not as we know it! Opportunities for the new commercial architectures", Invited Keynote Talk, Field Programmable Logic and Applications, Proc. 10 th International Workshop, Villach, Springer LNCS "The Third Wave is Hitting the Beach", Comment Article, Electronic Business, October Secure Configuration of a Field Programmable Gate Array, Proceedings IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), Rohnert Park CA, Secure Configuration of Field Programmable Gate Arrays, Programmable Logic and Applications, Proc. 11th International Workshop. Belfast, Springer LNCS A Reconfigurable Embedded Input Device for Kinetically Challenged Persons, Proc. 11th International Workshop. Belfast, Springer LNCS Parameterized hardware libraries for configurable system-on-chip technology, Canadian Journal Electrical and Computer Engineering, Vol. 26, No. 3/4, July/October

6 24. Cryptographic Rights Management of FPGA Intellectual Property Cores, Proceedings Tenth ACM International Symposium on FPGA s. Monterey CA, "Cryptographically Enforced Pay-Per-Use Licensing of FPGA Design Intellectual Property", Proceedings IP Based Design Grenoble, France, Video "Reconfigurable Processing: The Third Computing Paradigm", Number 12, The Distinguished Lecture Series, University Video Communications,