SMA Compound Semiconductors Lecture 9 - Metal-Semiconductor FETs - Outline

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1 SMA Compound Semiconductors Lecture 9 - Metal-Semiconductor FETs - Outline Device structure and operation Concept and structure: General structure Basis of operation; device types Terminal characteristics Gradual channel approximation w. o. velocity saturation Velocity saturation issues Characteristics with velocity saturation Small signal equivalent circuits High frequency performance Fabrication technology Process challenges: 1. Semi-insulating substrate; 2. M-S barrier gate; 3. Threshold control; 4. Gate resistance; 5. Source and drain resistances Representative sequences: 1. Mesa-on-Epi; 2. Proton isolation; 3. n+/n epi w. recess; 4. Direct implant into SI-GaAs (areas where heterostructures can make life easier and better) C. G. Fonstad, 3/03 Lecture 9 - Slide 1

2 BJT/FET Comparison - cont. Emitter/ Source Base/ Channel Collector/ Drain 0 w B or L Controlled by veb in a BJT; by v in an FET GS v CE or v DS C. G. Fonstad, 3/03 0 w B or L Lecture 9 - Slide 2

3 BJT/FET Comparison - cont. OK, that's nice, but there is more to the difference than how the barrier is controlled BJT FET Charge minority majority carriers in base in channel Flow diffusion drift mechanism in base in channel Barrier direct contact change induced control made to base by gate electrode The nature of the current flow, minority diffusion vs majority drift, is perhaps the most important difference. C. G. Fonstad, 3/03 Lecture 9 - Slide 3

4 FET Mechanisms - MOSFET and JFET/MESFET MOSFET Induced n-type channel JFET Doped n-type channel C. G. Fonstad, 3/03 Lecture 9 - Slide 4

5 Junction Field Effect Transistor (JFET) Reverse biasing the gate-source junction increases depletion width under gate and constricts the n-type conduction path between the source and drain. Ref: Fonstad, Mircoelectronic Devices and C. G. Fonstad, 3/03 Circuits, Chap posted on SMA5111 Website Lecture 9 - Slide 5

6 JFET, cont. Operating regions: (a) linear (or triode) well below pinch-off (a) (b) small V p < v GS < 0, v DS (b) linear nearing pinch-off V p < v GS < 0, v DS nearing (v GS - V p ) (c) (c) (d) (c) pinch-off V p < v GS < 0, v DS > (v GS - V p ) Ref: Fonstad, Chap. 10 (d) cut-off v GS < V p < 0 (a) (b) (d) C. G. Fonstad, 3/03 Lecture 9 - Slide 6

7 MEtal Semiconductor FET - MESFET The operation is very similar to that of a JFET. The p-n junction gate is replaced by a Schottky barrier, and the lower contact and p-n junction are eliminated because the lightly doped p- type substrate is replaced by a semi-insulating substrate. C. G. Fonstad, 3/03 Lecture 9 - Slide 7

8 MESFET current-voltage (i-v) characteristic We have two currents, i G and i D, that we want to determine as functions of the two voltages, v GS and v DS : i g (v gs,v ds ) and i d (v gs,v ds ) If we restrict our model to drain-to-source voltages greater than zero, and gate-to-source voltages less than the turn-on voltage of the gate Schottky diode, then, say that the gate current is negligible and i G 0: i g (v gs,v ds ) ª 0 if v gs V on, and v ds 0. Our real problem then is to find an expression for the drain current, i D. The path for the drain current is through the channel to the source, and we model it using the gradual channel approximation (next slide). C. G. Fonstad, 3/03 Lecture 9 - Slide 8

9 MESFET current-voltage (i-v) characteristic The model used to describe the drain current-voltage expression for an FET is the Gradual Channel Approximation. In this model we assume the current flow in the channel is entirely in the y-direction, and that the field lines terminating on the gate are entirely vertical. Gradual Channel Approximation Field lines above channel are strictly vertical Current flow is strictly horizontal C. G. Fonstad, 3/03 Lecture 9 - Slide 9

10 MESFET i-v: gradual channel approximation If the Gradual Channel Approximation is valid we can solve two independent 1-d problems in sequence: (1) an electrostatics problem in the vertical (x-) direction to find the mobile charge sheet density at any point, y, in the channel; (2) a drift problem in the horizontal (y-) direction to relate the voltage drop along the channel to the current. We integrate this relation from y = 0 to y = L to get the final expression relating the drain current to the gate and drain voltage. Electrostatics problem in the x-direction Carrier drift problem in the y-direction C. G. Fonstad, 3/03 Lecture 9 - Slide 10

11 MESFET i-v: vertical electrostatics problem Depletion region v GS The sheet carrier density 0 at the position y along the channel is: x d (y) N ch (y) = N Dn [a - x d ( y )] N Dn And the depletion width there is: a v CS (y) x d ( y)= 2e S {f b - [v GS - v CS ( y)]} qn Dn Combining these yields: È x N ch (y) = N Dn ÎÍ a - 2e S {f b - [v GS - v CS ( )]} qn Dn y This is the information we wanted to C. G. Fonstad, 3/03 get from the vertical problem. Lecture 9 - Slide 11

12 MESFET i-v: horizontal drift current problem i D Define v CS (y) as the voltage in the channel relative to the source at y. v CS (y) varies from v DS at y = L to 0 at y = 0 the horizontal E-field in the channel, E y, is - dv CS (y)/dy The drain current, i D, flows right to left in the channel: - i D is a constant and is not a function of y - at any y, i D is the sheet charge density at that y, times its net drift velocity, times the channel width C. G. Fonstad, 3/03 Lecture 9 - Slide 12

13 MESFET i-v: horizontal drift current problem, cont We write thus the current as: i D =--qn ch (y) W s y (y)] [ where -q is the charge per carrier; W is the channel width; and N ch (y) is the sheet carrier density at point y along the channel, which we have already determined by solving the vertical electrostatics problem: È N ch (y) = N Dn ÎÍ a - 2e S {f b - [v GS - v CS ( y)]} qn Dn In the low- to moderate-field region, the average net carrier velocity in the y-direction is the drift velocity: s y (y) =-m F y (y) = m dv CS (y) e e dy C. G. Fonstad, 3/03 Lecture 9 - Slide 13

14 MESFET i-v: horizontal drift current problem, cont Putting this all together we get: È i D =-qn Dn v GS W dv CS (y) a - 2e S ]} qn Dn m ÎÍ { f b - [ - v CS ( y ) e dy We rearrange terms, multiply by dy, and integrate each side from y = 0, v CS = 0, to v = L, v CS = v DS : L Ú 0 i D dy = m qn e Dn W Ú v DS 0 È Ía - Î 2e S qn Dn ( f b Doing the integrals, and dividing both sides by L yields: - [ v GS - v CS ( y) ] 1/2 ) dv CS i D W Ï 2 2e = a qm S [ e N Dn Ìv DS - ( f b - v GS + v DS L Ó 3 qn Dn a 2 ) 3/2 - (f b - v GS ) 3/2 ] C. G. Fonstad, 3/03 Lecture 9 - Slide 14

15 MESFET i-v: linear or triode region Our result thus far: W Ï i D = a qm e N Dn Ì L Ó Plotting this: v DS 2 2e - S [(f b - v qn Dn a 2 GS + v DS 3 ) - (f b is only valid until x d (y) = a, which occurs at y = L when 3/2 ( ) v DS = v GS - f b - qn Dn a 2 2e S - v GS ) 3/2 ] Region of validity C. G. Fonstad, 3/03 Lecture 9 - Slide 15

16 MESFET i-v: saturation region For larger v DS, i.e. when: v DS > v GS - ( f b - qn Dn a 2 2e S ) The current, i D, stays constant at the peak value, which is: ÏÔ È 3/2 3/2 ( f Ô Ì ( b - V P ) - f ( b - v GS ) i D = G V P ) o v GS - - 1/2, 3 ( f b - V P ) ÔÓ 2 ÍÍ Î where Vp f b - qn Dn a 2 2e S ( ) Ô and G o W a qm e N Dn L Plotting this: Saturated current C. G. Fonstad, 3/03 Lecture 9 - Slide 16

17 MESFET i-v: summary of characteristics We identify the pinch-off voltage, V P, and undepleted channel conductance, G o : ( f - 2 W V p b qn Dn a 2e S ) Go a qm e L We can then write the drain current, i D, for each of the three regions: Cutoff: When ( v GS - Saturation: When 0 Linear: ( ) V P v GS - When 0 v DS ( 0 v DS, i D V P ) v GS v DS, i D - V P ), i D = G = 0 ÏÔ Ì ÔÓ o ( ÏÔ = G Ì ÔÓ v GS o v DS - ) V P 2 È ( - Í 3 ÍÎ When v GS <V P the channel is pinched off for all v DS, and the device is cut-off,ii.e., i D = 0. 2 È ( - Í 3 ÍÎ f b f b - ) ( f b ) - v GS + v DS - ( V P f b 3/2 - (f b - 1/2 -V P ) 3/2 - (f b ) V P 1/2 - N Dn v GS v GS ) ) 3/2 3/2 Ô Ô Ô Ô C. G. Fonstad, 3/03 Lecture 9 - Slide 17

18 MESFET characteristics - channel-length modulation In practice we find that i D increases slightly with v DS in saturation. This is because the effective channel length decreases with increasing v DS above pinch-off. We model this by saying L Æ L(1 - lv DS ) which means 1/ L Æ (1 + lv DS )/ L and consequently G o Æ (1 + lv DS )G o Approx. extrapolation id Slope exagerated for emphasis -1/l = -V A Note: The parameter l has the units of inverse voltage, and by convention its inverse is called the Early voltage: Early voltage, V A 1/ l C. G. Fonstad, 3/03 Lecture 9 - Slide 18 vds

19 Large signal model: Enhancement mode FETs In our discussion thus far we have indicated that there is a conducting channel between the source and drain when the gate is unbiased, I.e., when v GS = 0. Such a device is called a "depletion mode" FET. If the doped layer under the gate is thin enough and/or lightly doped, is possible that the it will be fully depleted when the gate is unbiased. Such a device is called an enhancement mode FET (this is the type of FET most typical of MOSFETs). The gate of an enhancement mode MESFET must be forward biased to open the channel and turn it on. Clearly an enhancement mode MESFET can not be turned on very much before the gate diode begins to connect. This is an important limitation, and important difference between MOSFETs and MESFETs. C. G. Fonstad, 3/03 Lecture 9 - Slide 19

20 MESFET - linear equivalent circuit g i g + + i d d s v gs v ds - - s i G v + ig = Q gs v GS i G Q v ds = g i v gs + g r v ds v DS i = i D d v GS v + i D v = g v + g v Q gs Q ds m gs o ds v DS gi i G v GS v DS Q, g r i G Q g m i D Q v GS v DS C. G. Fonstad, 3/03 Lecture 9 - Slide 20 Q, g o i D

21 MESFET - linear equivalent circuit, cont The equations on the previous foil are mathematical identities; they tell us nothing about the physics of the device. That comes from using our model to evaluate the derivatives. We want a model to use when the FET is biased in saturation, so we use the current expressions there: (Remember i G = 0, so g i and g r are zero.) g i i G v GS g m i D v GS v DS Q = 0 g r i G È o Î Í Q = 0 (f b - v GS ) Q = G Í1- ( f b -V P ) g o i D v DS Q ª li D = I D /V A C. G. Fonstad, 3/03 Lecture 9 - Slide 21

22 Linear equivalent circuit models - schematics A circuit representation of these results is: g + d s vgs gmvgs go - s To extend this model to high frequencies we introduce small signal linear capacitors representing the charge stored on the gate: g + Cgd d s vgs - q G Cgs gmvgs go s C Q C gd q G gs v GS v DS Q More on this later. C. G. Fonstad, 3/03 Lecture 9 - Slide 22

23 The velocity saturation issue for MESFETs (Images deleted) See Fig : Shur, M. S., Physics of Semiconductor Devices Englewood Cliffs, N.J.: Prentice-Hall, 1990 C. G. Fonstad, 3/03 Lecture 9 - Slide 23

24 Velocity saturation models - impact on MESFET i-v Model A Model B Model A Model B m F s (F ) = m F e y y y e y if F y F crit s y (F y ) = Fy = m e F crit s sat if F y F crit 1+ F crit C. G. Fonstad, 3/03 Lecture 9 - Slide 24

25 Impact of velocity saturation - Model A * Results of previous modeling hold until s y at some point equals s sat ; after that the current saturates: * Model A s y (F y ) = m F e y if F y F crit = m e F crit s sat if F y F crit C. G. Fonstad, 3/03 Lecture 9 - Slide 25

26 Impact of velocity saturation - Model B * Model B s y (F y ) = m F e y F y 1+ Fcrit i D It is easy to show that the expression we derived in the linear region with no velocity saturation becomes with this model: 1 ÏÔ v o Ì DS - 2 È ( f Í b - v GS + v DS ) - f - = G 1/2 1+ v DS F crit L ÔÓ 3 ÍÎ ( f b - V P ) when 0 v DS v ( GS - V P ) ( b v GS ) Ô 3/2 3/2 Ô This is the original expression multiplied by the factor 1/(1+v DS /F crit L) C. G. Fonstad, 3/03 Lecture 9 - Slide 26

27 High f models and f \ C. G. Fonstad, 3/03 Lecture 9 - Slide 27

28 A mushroom- or T-gate MESFET (Image deleted) See Hollis and Murphy in: Sze, S.M., ed., High Speed Semiconductor Devices New York: Wiley 1990 C. G. Fonstad, 3/03 Lecture 9 - Slide 28

29 Representative processing sequences for MESFETs Double recess process (Image deleted) SAINT process (Image deleted) See Hollis and Murphy in: Sze, S.M., ed., High Speed Semiconductor Devices New York: Wiley 1990 C. G. Fonstad, 3/03 Ref: Hollis and Murphy in Sze HSSD Lecture 9 - Slide 29