Data Sheet. ACPL-077L Low Power 3.3 V / 5 V High Speed CMOS Optocoupler Design for System Level Reliability. Description. Features. Functional Diagram

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1 ACPL-077L Low Power 3.3 V / 5 V High Speed CMOS Optocoupler Design for System Level Reliability Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxe denotes a lead-free product Description Avago s ACPL-077L optocoupler utilizes the latest CMOS IC technology to achieve outstanding speed and low power performance of minimum 5 MBd data rate and 6 ns maximum pulse width distortion with enhanced reliability relative to system level IEC X testing (ESD/Burst/Surge). Available in SO-8 package, the basic building blocks of ACPL-077L are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC, which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. Functional Diagram **V DD V I NC* GND 3 LED SHIELD ACPL-077L I O V DD ** NC* V O GND TRUTH TABLE (POSITIVE LOGIC) V I LED V O HIGH OFF HIGH LOW ON LOW * Pin 3 is multiplexed as a test pin that can connect to V DD or left unconnected. Pin 7 is not connected internally. ** A 0. µf bypass capacitor must be connected between pins V DD and GND, and V DD and GND Features Enhance reliability relative to system level IEC X testing (ESD/Burst/Surge) 3.3 V and 5 V CMOS Compatibility CMOS buffer input Allow level shifting functionality High Speed: DC to 5 MBd 35 kv/µs minimum Common Mode Rejection (CMR) at V CM = 000 V Guaranteed AC and DC performance over wide temperature: -0 C to +05 C Safety and Regulatory Approvals: UL Recognised 3750 V rms for min. per UL577 CSA Component Acceptance Notice #5 IEC/EN/DIN EN V IORM = 567 V peak for Option 060E Lead-free option available Applications Digital Fieldbus Isolation: CC-Link, DeviceNet, Profibus, SDS Multiplexed Data Transmission General Instrument and Data Acquisition Computer Peripheral Interface Microprocessor System Interface

2 Ordering Information ACPL-077L is UL Recognized with 3750 Vrms for minute per UL577. Part number Option RoHS Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN Quantity ACPL-077L -000E SO-8 X 00 per tube -060E X X 00 per tube -500E X X 500 per reel -560E X X X 500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-077L-500E to order product of Mini-flat Surface Mount 8-pin package in Tape and Reel packaging with RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Regulatory Information The ACPL-077L will be approved by the following organizations: UL Approval under UL 577, component recognition program up to V ISO = 3750 V RMS. CSA Approval under CSA Component Acceptance Notice #5. IEC/EN/DIN EN (Option 060E only)

3 Package Outline Drawings ACPL-077L SO-8 Package ROHS-COMPLIANCE INDICATOR ± 0.7 (0.55 ± 0.005) PIN ONE XXXV YWW ± 0.03 (0.36 ± 0.008) 0.06 ± (0.06 ± 0.003).70 (0.050) BSC TYPE NUMBER (LAST 3 DIGITS) DATE CODE LAND PATTERN RECOMMENDATION.9 (0.075) 3.95 (0.56).3 (0.5) 0.6 (0.05) 7.9 (0.95) * ± 0.7 (0.00 ± 0.005) 7 5 X 0.3 (0.07) 3.75 ± 0.7 (0.5 ± 0.005).5 (0.060) 0 ~ ± 0.05 (0.009 ± 0.00) * Total package length (inclusive of mold flash) 5.07 ± 0.5 (0.05 ± 0.00) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is 0.5 mm (6 mils) max. Lead coplanarity = 0.0 mm (0.00 inches) max. Option number 500 not marked (0.0) MIN ± 0.0 (0.008 ± 0.00) Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-00 (latest revision). Non-Halide Flux should be used. 3

4 Insulation and Safety Related Specifications Parameter Symbol ACPL-077L Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(0).9 mm Measured from input terminals to output terminals, shortest distance through air. L(0).8 mm Measured from input terminals to output terminals, shortest distance path along body mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI 75 Volts DIN IEC /VDE 0303 Part Isolation Group IIIa Material Group (DIN VDE 00, /89, Table ) IEC/EN/DIN EN Insulation Characteristics* (Option 060E) Description Installation classification per DIN VDE 00/39, Table for rated mains voltage 50 V rms for rated mains voltage 300 V rms for rated mains voltage 600 V rms Symbol Characteristic ACPL-077L I IV I III I II Climatic Classification 55/05/ Pollution Degree (DIN VDE 00/39) Unit Maximum Working Insulation Voltage V IORM 567 V peak Input to Output Test Voltage, Method b* V IORM x.875 = V PR, 00% Production Test with t m = sec, Partial discharge < 5 pc Input to Output Test Voltage, Method a* V IORM x.6 = V PR, Type and Sample Test, t m = 0 sec, Partial discharge < 5 pc Highest Allowable Overvoltage (Transient Overvoltage t ini = 60 sec) Safety-limiting values maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** V PR 063 V peak V PR 907 V peak V IOTM 6000 V peak T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = 500 V R S >0 9 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN ) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to figure 0 for dependence of P S and I S on ambient temperature C ma mw Absolute Maximum Ratings Parameter Symbol Min Max Units Storage Temperature T S C Operating Temperature T A C Supply Voltage V DD, V DD V Input Voltage V I -0.5 V DD +0.5 V Output Voltage V O -0.5 V DD +0.5 V Average Output Current I O 0 ma Lead Solder Temperature T LS 60 C for 0 sec.,.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section

5 Recommended Operating Conditions Parameter Symbol Min Max Units Operating Temperature T A C Supply Voltage (3.3V) V DD, V DD V Supply Voltage (5V) V DD, V DD V Logic High Input Voltage V IH 0.7 x V DD V DD V Logic Low Input Voltage V IL x V DD V Input Signal Rise and Fall Times t r, t f ms Electrical Specifications (DC) Over recommended temperature (T A = 0 C to 05 C) and supply voltage (.5 V V DD 5.5 V,.5 V V DD 5.5 V), (3 V V DD 3.6 V, 3 V V DD 3.6 V), (.5 V V DD 5.5 V, 3 V V DD 3.6 V) and (3 V V DD 3.6 V,.5 V V DD 5.5 V). All typical specifications are at V DD = V DD = +3.3 V, T A = 5 C Parameter Symbol Min Typ Max Units Test Conditions Logic Low Input Supply Current [] I DDL ma V I = 0 V. Figure Logic High Input Supply Current [] I DDH 0.6 ma V I = V DD. Figure Logic Low Output Supply Current I DDL.5.5 ma V I = 0 V. Figure 3 Logic High Output Supply Current I DDH.5.5 ma V I = V DD. Figure Input Current I I -0 0 ma Logic High Output Voltage V OH V I O = 0 ua, V I = V IH, V DD = 3.3 V.9.9 V I O = ma, V I = V IH, V DD = 3.3 V.0.7 V I O = ma, V I = V IH, V DD = 5.0 V Logic Low Output Voltage V OL 0 0. V I O = 0 µa, V I = V IL V I O = ma, V I = V IL Switching Specifications (AC) Over recommended temperature (T A = -0 C to 05 C) and supply voltage (.5 V V DD 5.5 V,.5 V V DD 5.5 V), (3 V V DD 3.6 V, 3 V V DD 3.6 V), (.5 V V DD 5.5 V, 3 V V DD 3.6 V) and (3 V V DD 3.6 V,.5 V V DD 5.5 V). All typical specifications are at V DD = V DD = +3.3 V, T A = 5 C Parameter Symbol Min Typ Max Units Test Conditions Propagation Delay Time to t PHL 0 ns C L = 5 pf, CMOS Signal Levels Logic Low Output [3] Figure 5,6 Propagation Delay Time to t PLH 3 0 ns C L = 5 pf, CMOS Signal Levels Logic High Output [3] Figure 5,6 Pulse Width t PW 0 ns C L = 5 pf, CMOS Signal Levels Maximum Data Rate 5 MBd C L = 5 pf, CMOS Signal Levels Pulse Width Distortion [] t PHL t PLH PWD 6 ns C L = 5 pf, CMOS Signal Levels Figure 7, 8 Propagation Delay Skew [5] t PSK 5 ns C L = 5 pf, CMOS Signal Levels Output Rise Time (0% 90%) t R ns C L = 5 pf, CMOS Signal Levels Output Fall Time (90% 0%) t F 3 ns Figure 9 Common Mode Transient CM H kv/µs V CM = 000 V, T A = 5 C, Immunity at Logic High Output [6] V I = V DD, V O > 0.8 x V DD Common Mode Transient CM L kv/µs V CM = 000 V, T A = 5 C, Immunity at Logic Low Output [6] V I = 0 V, V O < 0.8 V 5

6 Package Characteristics All typical at T A = 5 C Parameter Symbol Min Typ Max Units Test Conditions Input-Output Insulation [7,8,9] V ISO 3750 V rms RH < 50% for min. T A = 5 C Input-Output Resistance [7] R I-O 0 Ω V I-O = 500 V Input-Output Capacitance C I-O 0.6 pf f= MHz, T A = 5 C Input Capacitance [0] C I 3.0 pf Notes:. Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality.. The LED is ON when V I is low and OFF when V I is high. 3. t PHL propagation delay is measured from the 50% level on the falling edge of the V I signal to the 50% level of the falling edge of the V O signal. t PLH propagation delay is measured from the 50% level on the rising edge of the V I signal to the 50% level of the rising edge of the V O signal.. PWD is defined as t PHL - t PLH. % PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. 5. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions. 6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD. CML is the maximum common mode voltage slew rate that can be sustained while maintaining V O < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. Device considered a two-terminal device: pins,, 3, and shorted together and pins 5, 6, 7, and 8 shorted together. 8. In accordance with UL577, each ACPL-077L is proof tested by applying an insulation test voltage 500 V RMS for second (leakage detection current limit, I I-O 5 μa). 9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Technologies Application Note 07 entitled Optocoupler Input-Output Endurance Voltage. 0. C I is the capacitance measured at pin (V I ). 6

7 IDDL - LOGIC LOW INPUT SUPPLY CURRENT - ma V 3.3 V Figure. Typical Logic Low Input Supply Current versus temperature. IDDH - LOGIC HIGH INPUT SUPPLY CURRENT - ma V 3.3 V Figure. Typical Logic High Input Supply Current versus temperature. IDDL - LOGIC LOW OUTPUT SUPPLY CURRENT - ma V 3.3 V 0.8 Figure 3. Typical Logic Low Output Supply Current versus temperature. IDDH - LOGIC HIGH OUTPUT SUPPLY CURRENT - ma V 3.3 V 0.8 Figure. Typical Logic High Output Supply Current versus temperature. Tphl, Tplh (ns) T plh T phl Figure 5. Typical propagation delay versus temperature at 3.3 V supply voltage. Tphl, Tplh (ns) T plh T phl C L (pf) Figure 6. Typical propagation delays vs load capacitance at 3.3 V supply voltage. 7

8 PWD (ns) Figure 7. Typical pulse width distortion vs temperature at 3.3 V supply voltage. PWD (ns) C L (pf) Figure 8. Typical pulse width distortion vs load capacitance at 3.3 V supply voltage. Tr, Tf (ns) Rise Time Fall Time Figure 9. Typical rise and fall time versus temperature at 3.3 V supply voltage. Output Power - Ps, Input Current - Is Is (ma) Ps (mw) T A - Case Temperature - C Figure 0. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN

9 Application Information Bypassing and PC Board Layout The ACPL-077L optocoupler is extremely easy to use. No external interface circuitry is required because ACPL-077L uses high speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.0 μf and 0. μf. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 0 mm. V DD V I C 077L * 3 6 V O 8 7 NC C V DD Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew The propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from a low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (Figure ). Pulse-width distortion (PWD) is the difference between t PHL and t PLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 0-30% of the minimum pulse width is tolerable. GND Figure. Recommended Circuit Diagram C, C = 0.0 µf TO 0. µf 5 GND * Pin 3 is multiplexed as a test pin that can connect to V DD or left unconnected. Pin 7 is not connected internally. INPUT V I 50% t PLH t PHL OUTPUT 90% 90% V O 0% 0% Figure. Signal plot shows how propagation delay is defined 5 V CMOS 0 V V OH.5 V CMOS V OL 9

10 Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 3, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tpsk is the difference between the shortest propagation delay, either t PLH or t PHL and the longest propagation delay, either t PLH and t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumes to be clocked off of the rising edge of the clock. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. V I V O 50%.5 V, CMOS INPUTS DATA CLOCK t PSK V I 50% DATA V O Figure 3. Propagation delay skew waveform.5 V, CMOS OUTPUTS t PSK CLOCK t PSK Figure. Parallel data transmission example For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV0-357EN - September 0, 03

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