Data Sheet. ACPL-M21L, ACPL-021L, ACPL-024L, ACPL-W21L and ACPL-K24L Low Power, 5 MBd Digital CMOS Optocoupler. Description.

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1 ACPL-ML, ACPL-L, ACPL-L, ACPL-WL and ACPL-KL Low Power, MBd Digital CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description ACPL-ML (single channel SO- package), ACPL-L (single channel SO-8 package), ACPL-L (dual channel SO-8 package), ACPL-WL (single channel stretched SO- package) and ACPL-KL (dual channel stretched SO-8 package) are optically-coupled logic gates. The detector IC has CMOS output stage and optical receiver input stage with built-in Schmitt trigger to provide logic-compatible waveforms, eliminating the need for additional waveshaping. An internal shield on the ACPL-ML/L/L/WL/ KL guarantees common mode transient immunity of kv/µs at a common mode voltage of V. The ACPL-xxL optocouplers' series operates from a.7 V to. V supply with guaranteed AC and DC performance from an extended temperature range of - C to C. Glitches free output upon power-up and power-down of optocoupler. Functional Diagram Anode Cathode NC Anode Cathode NC ACPL-ML VDD VO GND 8 VDD 7 VO NC GND ACPL-L ACPL-L/KL TRUTH TABLE (POSITIVE LOGIC) LED VO ON OFF Anode HIGH LOW NC Cathode Anode 8 V DD Cathode Cathode Anode ACPL-WL VDD VO GND 7 V V GND Features CMOS output Wide supply voltage:.7 V. V Low power supply current I DD :. ma/channel max. Low forward current :. ma min Speed: MBd typ Pulse width distortion (PWD): ns max Propagation delay skew (tpsk): ns max Propagation delay (tp): ns max Common mode rejection: kv/µs min at V CM = V Hysteresis:. ma typ Temperature range: - C to C Safety and regulatory approvals UL 77 recognized 7 Vrms for minute for ACPL-ML/L/L and Vrms for minute for ACPL-WL/KL CSA Approval IEC/EN 77--, Approval for Reinforced Insulation Applications Low isolation of high speed logic systems Computer peripheral interface Microprocessor system interface Ground loop elimination Pulse transformer replacement High speed line receiver Power control systems A. μf bypass capacitor must be connected between pins Vdd and GND

2 Ordering Information ACPL-ML, ACPL-L and ACPL-L are UL Recognized with 7 V rms for minute per UL77. ACPL-WL and ACPL-KL are UL Recognized with Vrms for minute per UL77. Part number Option RoHS Compliant Package Surface Mount Tape & Reel UL77 V rms / Minute Rating IEC/EN 77-- Quantity ACPL-ML -E SO- X per tube -E X X per tube -E X X per reel -E X X X per reel ACPL-L -E SO-8 X per tube -E X X per tube -E X X per reel -E X X X per reel ACPL-L -E SO-8 X per tube -E X X per tube -E X X per reel -E X X X per reel ACPL-WL -E Stretched X X per tube -E SO X X X per tube -E X X X per reel -E X X X X per reel ACPL-KL -E Stretched X X 8 per tube -E SO8 X X X 8 per tube -E X X X per reel -E X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-ML-E to order product of SO- package in Tape and Reel packaging with RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3 Package Outline Drawings ACPL-ML SO- Package ROHS-COMPLIANCE INDICATOR PART NUMBER LAND PATTERN RECOMMENDATION. (.).7 (.). (.) DATE CODE. ±. (.7 ±.) 7. ±. (.7 ±.8) EEE.9 (.7) 8. (.) Lot ID. ±.* (. ±.). ±. (. ±.). (.).8 (.7). ±. (.98 ±.). ±. (. ±.). ±. (. ±.).7 (.) BSC.7 (.8) MIN 7 MAX. Dimensions in millimeters (inches). Note: Foating Lead Protrusion is. mm ( mils) max. * Maximum Mold flash on each side is. mm (.). ACPL-L/L SO-8 Package LAND PATTERN RECOMMENDATION MAX. LEAD COPLANARITY =. (.) ROHS-COMPLIANCE INDICATOR.97 ±.7 (. ±.) PIN ONE 8 7 EEE.99 ±. (. ±.8). ±.7 (. ±.).7 (.) BSC PART NUMBER DATE CODE Lot ID.9 (.7).9 (.).7 (.). (.) 7.9 (.9) *.8 ±.7 (. ±.) 7 X. (.7).7 ±.7 (. ±.). (.) ~ 7.8 ±. (.9 ±.) * Total package length (inclusive of mold flash).7 ±. (. ±.) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is. mm ( mils) max. Lead coplanarity =. mm (. inches) max. Option number not marked.. (.) MIN.. ±. (.8 ±.)

4 ACPL-WL Stretched SO- Package.8±. (.8±.).7 (.) BSG LAND PATTERN RECOMMENDATION. (.98) ROHS-COMPLIANCE INDICATOR.7 (.) EEE PART NUMBER DATE CODE Lot ID.9 (.7) 7.8±.7 (.±.). (.8) 7.87 ( ).9±.7 (.±.).±. (.8±.).8±.7 (.±.) Dimensions in Millimeters (Inches). Lead coplanarity =. mm (. inches). ACPL-KL Stretched SO-8 Package.7±. (.9±.).±. (.±.).8±. (.±.) LAND PATTERN RECOMMENDATION 8 7 PART NUMBER ROHS-COMPLIANCE INDICATOR EEE DATE CODE Lot ID.87±.7 (.8±.). (.).9 (.) 7. (.8) 7.9±.7 (.±.).8±.7 (.±.).±. (.±.).7 (.) BSG.8±. (.±.) Dimensions in Millimeters (Inches). Lead coplanarity =. mm (. inches)..7±. (.9±.).±. (.±.)

5 Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-ML/L/L/WL/KL is approved by the following organizations: UL Approval under UL 77, component recognition program up to V ISO = 7 V RMS for ACPL-ML/L/L and VISO = V RMS for ACPL-WL/KL CSA Approval under CSA Component Acceptance Notice #. IEC/EN 77-- (Option and only) Insulation and Safety Related Specifications Parameter Symbol ACPL-ML Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) ACPL-L /L ACPL-WL /KL Units Conditions L().9 8 mm Measured from input terminals to output terminals, shortest distance through air. L().8 8 mm Measured from input terminals to output terminals, shortest distance path along body mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI Volts DIN IEC /VDE Part Isolation Group IIIa IIIa IIIa Material Group (DIN VDE, /89, Table )

6 IEC/EN 77-- Insulation Characteristics* (Option and only) Description Installation classification per DIN VDE /9, Table for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms Symbol ACPL-ML/ L/L I IV I III I II Characteristic ACPL-WL/ KL I IV I IV I III I III Climatic Classification // // Pollution Degree (DIN VDE /9) Unit Maximum Working Insulation Voltage V IORM 7 V peak Input to Output Test Voltage, Method b* V IORM x.87 = V PR, % Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and Sample Test, t m = sec, Partial discharge < pc Highest Allowable Overvoltage (Transient Overvoltage t ini = sec) Safety-limiting values maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** V PR 7 V peak V PR 89 8 V peak V IOTM 8 V peak T S I S, INPUT P S, OUTPUT Insulation Resistance at TS, V IO = V R S > 9 > 9 W * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN 77--) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of P S and I S on ambient temperature. 7 C ma mw Absolute Maximum Ratings Parameter Symbol Min Max Units Condition Storage Temperature T S - C Operating Temperature T A - C Reverse Input Voltage V R V Supply Voltage V DD. V Average Forward Input Current 8 ma Peak Forward Input Current (TRAN) A ms Pulse Width, < pulses per second Output Current I O ma At max V DD Output Voltage V O -. V DD +. V Lead Solder Temperature T LS C for sec.,. mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section

7 Recommended Operating Conditions Parameter Symbol Min Max Units Operating Temperature T A - C Input Current, Low Level L µa Input Current, High Level H.* ma Power Supply Voltage V DD.7. V Forward Input Voltage V F (OFF).8 V * The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % LED degradation guardband. Electrical Specifications (DC) Over recommended temperature (T A = - C to C) and supply voltage (.7 V V DD. V). All typical specifications are at V DD =.7 V, T A = C, unless otherwise specified. Parameter Symbol Channel Min Typ Max Units Test Conditions Input Forward Voltage V F.. V =. ma (Figure & ) Input Reverse Breakdown Voltage BV R 8 V I R = µa Logic High Output Voltage V OH V DD -. V =. ma, I O = - µa V DD -. V =. ma, I O = -. ma (Figure ) Logic Low Output Voltage V OL.. V = ma, I O = µa.. V = ma, I O =. ma (Figure ) Input Threshold Current I TH.. ma Figure Logic Low Output Supply Current Logic High Output Supply Current I DDL Single.. ma V F = V, V DD =. V, Dual.. I O = Open (Figure ) I DDH Single.. ma =. ma, V DD =. V, Dual.. I O = Open (Figure 7) Input Capacitance C IN 77 pf f = MHz, V F = V Input Diode Temperature Coefficient ΔV F /ΔT A -.9 mv/ C =. ma 7

8 Switching Specifications (AC) Over recommended temperature (T A = - C to + C), supply voltage (.7 V V DD. V). All typical specifications are at V DD =.7 V, T A = C Parameter Symbol Min Typ Max Units Test Conditions Propagation Delay Time t PHL ns =.ma, C L =pf (Figure 8, ) to Logic Low Output [] CMOS Signal Levels Propagation Delay Time t PLH ns =.ma, C L =pf (Figure 9, ) to Logic High Output [] CMOS Signal Levels Pulse Width Distortion [] PWD ns CMOS Signal Levels Propagation Delay Skew [] t PSK ns Output Rise Time (% 9%) Output Fall Time (9% %) Static Common Mode Transient Immunity at Logic High Output [] Static Common Mode Transient Immunity at Logic Low Output [] t R ns =. ma, C L = pf, CMOS Signal Levels. t F ns =. ma, C L = pf, CMOS Signal Levels. CM H kv/ms V CM = V, T A = C, =. ma, C L = pf, V I = V (R T =. kω) or V I =. V (R T = 8 Ω) CMOS Signal Levels Figure CM L kv/ms V CM = V, T A = C, = ma, C L = pf, V I = V (R T =. kω) or (R T = 8 Ω) CMOS Signal Levels Figure Notes:. t PHL propagation delay is measured from the % (V in or ) on the falling edge of the input pulse to the % V DD of the falling edge of the V O signal. t PLH propagation delay is measured from the % (V in or ) on the rising edge of the input pulse to the % level of the rising edge of the V O signal. PWD is defined as t PHL - t PLH. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.. CM L is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state.. Use of a. μf bypass capacitor connected between Vdd and ground is recommended. Package Characteristics All typical at T A = C Parameter Symbol Part Number Min Typ Max Units Test Conditions Input-Output Insulation V ISO ACPL-ML /L/L ACPL-WL /KL 7 V rms RH < % for min. T A = C Input-Output Resistance R I-O W V I-O = V Input-Output Capacitance C I-O. pf f = MHz, T A = C 8

9 VF - FORWARD VOLTAGE - V IF - FORWARD CURRENT - ma Figure. Forward Voltage vs. Temperature V F - FORWARD VOLTAGE - V Figure. Forward Current vs Forward Voltage VOH - HIGH LEVEL OUTPUT VOLTAGE - V 7 I O = -. ma 7 V DD - SUPPLY VOLTAGE - V Figure. Logic High Output voltage vs Supply Voltage VOL - LOW LEVEL OUTPUT VOLTAGE - V..... V DD =. V V F = V I O =. ma Figure. Logic Low Output Voltage vs. Temperature Ith - INPUT THRESHOLD CURRENT - ma Figure. Input Threshold Current vs. Temperature I TH _. V I TH _. V IDDL - LOGIC LOW OUTPUT SUPPLY CURRENT - ma I V I V Figure. Logic Low Output Supply Current vs. Temperature 9

10 IDDH - LOGIC HIGH OUTPUT SUPPLY CURRENT - ma I DDH_. V I DDH_. V Figure 7. Logic High Output Supply Current vs. Temperature Tp - PROPAGATION DELAY - ns =.,. and ma V DD =.7 V Figure 8. Propagation Delay, t PHL vs. Temperature TPLH - PROPAGATION DELAY - ns =. ma =. ma 9 8 =. ma 7 V DD =.7 V Figure 9. Propagation Delay, t PLH vs. Temperature Vo - OUTPUT VOLTAGE - V.... V DD =. V INPUT CURRENT - A Figure. Output Voltage vs Input Vdd =. V Vo - OUTPUT VOLTAGE - V V DD =. V INPUT CURRENT - A Figure. Output Voltage vs Input Vdd = V

11 PULSE GEN t r = t f = ns f =. MHz % DUTY CYCLE ACPL-ML Vdd OUTPUT V O PULSE GEN t r = t f = ns f =. MHz % DUTY CYCLE ACPL-WL Vdd OUTPUT V O * * INPUT Rm C L = pf INPUT Rm C L = pf PULSE GEN t r = t f = ns f =. MHz % DUTY CYCLE INPUT Rm ACPL-L 8 7 Vdd * OUTPUT V O C L = pf PULSE GEN t r = t f = ns f =. MHz % DUTY CYCLE INPUT Rm ACPL-L/KL 8 7 Vdd * OUTPUT V O C L = pf INPUT (ON) % (ON) ma t PLH t PHL OUTPUT V O V OH % V OL Figure. Circuit for t PLH, t PHL, t r, t f *. µf BYPASS SEE NOTE above. []

12 ACPL-ML, ACPL-L, ACPL-L, ACPL-WL, ACPL-KL : V I =. V: R = Ω ± %, R = Ω ± % V I =. V: R = kω ± %, R = Ω ± % R T = R + R R / R. V I R V DD V I R V DD C V o C V o GND R GND GND R GND ACPL-ML ACPL-WL 8 V DD V I R 8 V DD R V I 7 V o R C GND NC GND GND R R 7 C V o V o GND V I R GND ACPL-L ACPL-L/KL C =.µf Figure. Recommended printed circuit board layout and input current limiting resistor selection For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. AV-EN - December,