HCPL-2201, HCPL-2202, HCPL-2211, HCPL-2212, HCPL-2231, HCPL-2232, HCPL-0201, HCPL-0211, HCNW2201, HCNW2211. Logic Gate Optocouplers.

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1 HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCNW, HCNW Very High CMR, Wide Logic Gate Optocouplers Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The HCPL-XX, HCPL-XX, and HCNWXX are optically-coupled logic gates. The HCPL-XX, and HCPL-XX contain a GaAsP LED while the HCNWXX contains an AlGaAs LED. The detectors have totem pole output stages and optical receiver input stages with built-in Schmitt triggers to provide logic-compatible waveforms, eliminat ing the need for additional waveshaping. A superior internal shield on the HCPL-/, HCPL-, HCPL- and HCNW guarantees common mode transient immunity of kv/μs at a common mode voltage of volts. Functional Diagram NC ANODE CATHODE ANODE CATHODE CATHODE HCPL-/ HCPL-/ HCNW/ NC GND SHIELD HCPL-/ V O NC V O V O ANODE GND SHIELD A. μf bypass capacitor must be connected between pins and. NC ANODE CATHODE HCPL-/ NC GND SHIELD TRUTH TABLE (POSITIVE LOGIC) LED V O ON HIGH OFF LOW NC V O Features kv/μs minimum Common Mode Rejection (CMR) at V CM = V (HCPL-///, HCNW) Wide operating range:. to Volts ns propagation delay guaranteed over the full temperature range Mbd typical signal rate Low input current (. ma to. ma) Hysteresis Totem pole output (no pullup resistor required) Available in -Pin DIP, SOIC-, widebody packages Guaranteed performance from - C to C Safety approval UL recognized - V rms for minute ( V rms for minute for HCNWXX) per UL CSAapproved IEC/EN/DIN EN -- approved with V IORM = V peak (HCPL-/ Option only) and V IORM = V peak (HCNWXX only) MIL-PRF- hermetic version available (HCPL-XX/XX) Applications Isolation of high speed logic systems Computer-peripheral interfaces Microprocessor system interfaces Ground loop elimination Pulse transformer replacement High speed line receiver Power control systems CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments.

2 The electrical and switching characteristics of the HCPL-XX, HCPL-XX and HCNWXX are guaranteed from - C to C and a from. volts to volts. Low I F and wide range allow compati bil ity with TTL, LSTTL, and CMOS logic and result in lower power consump tion compared to other high speed couplers. Logic signals are transmitted with a typical propagation delay of ns. Selection Guide Small- Widebody Minimum CMR Input -Pin DIP ( Mil) Outline SO- ( Mil) Hermetic On- Single Dual Single Single Single and dv/dt Current Channel Channel Channel Channel Dual Channel (V/μs) V CM (V) (ma) Package Package Package Package Packages,. HCPL- [,] HCPL- HCNW HCPL- HCPL-. HCPL-,. HCPL-9 [,], [] []. HCPL- HCPL- HCNW HCPL-. HCPL-,. HCPL-XX [] HCPL-XX [] Notes:. HCPL-/9 devices include output enable/disable function.. Technical data for the HCPL-/9, HCPL-XX and HCPL-XX are on separate Avago publications.. Minimum CMR of kv/μs with V CM = V can be achieved with input current, I F, of ma. Schematic I CC I CC I F V F I O V O V F I F SHIELD HCPL-/// HCPL-/ HCNW/ I O V O GND V F I F SHIELD SHIELD I O V O GND HCPL-/

3 Ordering Information HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL- are UL Recognized with Vrms for minute per UL. HCNW and HCNW are UL Recognized with Vrms for minute per UL. All devices listed above are approved under CSA Component Acceptance Notice #, File CA. Part number HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCPL- HCNW HCNW RoHS Compliant Option Non RoHS Compliant Package Surface Mount Gull Wing Tape & Reel UL Vrms/ Minute rating IEC/EN/DIN EN -- Quantity -E No option per tube -E - X X per tube -E - mil X X X per reel -E - DIP- X per tube -E - X X X per tube -E - X X X X per reel -E No option per tube -E - X X per tube -E - X X X per reel -E No option X per tube -E - X X per reel SO- -E - X X per tube -E - X X X per reel -E No option mil X X per tube -E - Widebody X X X X per tube -E - DIP- X X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL--E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval in RoHS compliant. Example : HCPL- to order product of mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July and RoHS compliant option will use -XXXE.

4 Package Outline Drawings -Pin DIP Package (HCPL-/////) 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER AVAGO DATE CODE LOT ID A XXXXZ OPTION CODE* YYWW UL RECOGNITION EEE P SPECIAL PROGRAM CODE UR. ±. (. ±.).9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (..) -.). (.) MIN..9 (.) MIN.. ±. (. ±.). (.) MAX.. ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. -Pin DIP Package with Gull Wing Surface Mount Option (HCPL-/////) LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.).9 (.). ±. (. ±.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.).. -. (..) -.). ±. (. ±.). (.) BSC. ±. (. ±.). ±. (. ±.) NOM. DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

5 Small-Outline SO- Package (HCPL-/) LAND PATTERN RECOMMENDATION.9 ±. (. ±.) PIN ONE XXX YWW EEE. ±. (. ±.). (.) BSC.99 ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE LOT ID. (.).9 (.).9 (.9) *. ±. (. ±.) o X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX.. (.). ±. (. ±.) MIN. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. -Pin Widebody DIP Package (HCNW/). ±. (. ±.). MAX. (.) A HCNWXXXX YYWW EEE TYPE NUMBER DATE CODE LOT ID 9. ±. (. ±.). (.) MAX. TYP.. (.) MAX.. (.) TYP (..) -.). (.).9 (.). (.) MIN.. (.) TYP.. ±. (. ±.). (.). (.) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

6 -Pin Widebody DIP Package with Gull Wing Surface Mount Option (HCNW/). ±. (. ±.) LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). (.).9 (.9). (.) MAX.. ±. (. ±.). MAX. (.). MAX. (.). ±. (. ±.). (.) BSC. ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.. ±. (.9 ±.) NOM (..) -.)

7 Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-XX/XX and HCNWXX have been approved by the following organizations: UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- (Option and HCNW only) Insulation and Safety Related Specifications -pin DIP Package Parameter Symbol Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) -Pin DIP ( Mil) Value SO- Value Widebody ( Mil) Value Units Conditions L() mm Measured from input terminals to output terminals, shortest distance through air. L()... mm Measured from input terminals to output terminals, shortest distance path along body.... mm Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. NA NA. mm Measured from input terminals to output terminals, along internal cavity. CTI Volts DIN IEC /VDE Part Isolation Group IIIa IIIa IIIa Material Group (DIN VDE, /9, Table ) Option - surface mount classification is Class A in accordance with CECC.

8 IEC/EN/DIN EN -- Insulation Characteristics (Option ) Description Symbol Characteristic HCPL-// /// Installation classification per DIN VDE, Table for rated mains voltage Vrms for rated mains voltage Vrms for rated mains voltage Vrms I IV I IV I IV HCPL- / Climatic Classification // // Pollution Degree (DIN VDE /9) I IV I IV I III Unit Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V PR V peak V IORM x. = V PR, % Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and Sample Test, t m = sec, Partial discharge < pc V PR 9 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = sec) V IOTM V peak Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT Insulation Resistance at TS, V IO = V R S 9 9 IEC/EN/DIN EN -- Insulation Characteristics (HCNWxx Option ONLY) Description Symbol Characteristic Unit Installation classification per DIN VDE, Table for rated mains voltage Vrms for rated mains voltage Vrms for rated mains voltage Vrms for rated mains voltage Vrms Climatic Classification -// Pollution Degree (DIN VDE /9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, Partial discharge < pc V PR V peak Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and Sample Test, t m = sec, Partial discharge < pc I IV I IV I IV I III V PR V peak Highest Allowable Overvoltage* (Transient Overvoltage t ini = sec) V IOTM V peak Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT Insulation Resistance at TS, V IO = V R S 9 * Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN --, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. C ma mw C ma mw

9 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - C Average Forward Input Current I F(AVG) ma Peak Transient Input Current ( μs Pulse Width, pps) I F(TRAN). A ( μs Pulse Width, < % Duty Cycle) HCNWXX ma Reverse Input Voltage V R V HCNWXX Average Output Current I O ma Supply Voltage V Output Voltage V O -. V Total Package Power Dissipation P T mw HCPL-X 9 Output Power Dissipation P O See Figure Lead Solder Temperature (Through Hole Parts Only) Solder Reflow Temperature Profile (Surface Mount Parts Only) HCNWXX C for sec.,. mm below seating plane C for sec., up to seating plane See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage. V Forward Input Current (ON) I F(ON).* ma HCPL-X. Forward Input Voltage (OFF) V F(OFF) -. V Operating Temperature T A - C Junction Temperature T J - C Fan Out N TTL Loads *The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % LED degradation guardband. The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % LED degradation guardband. 9

10 Electrical Specifications - C T A C,. V V,. ma I F(ON) * ma, V V F(OFF). V, unless otherwise specified. All Typicals at T A = C. See Note. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Fig Logic Low Output Voltage V OL. V I OL =. ma ( TTL Loads), Logic High Output Voltage V OH. ** V I OH = -. ma,, (V OUT < ). I OH = -. ma Output Leakage Current I OHH μa V O =. V I F = ma V O = V Logic Low Supply I CCL.. ma =. V V F = V Current.. = V I O = Open HCPL-X.. =. V.. = V Logic High Supply I CCH.. ma =. V I F = ma Current.. = V I O = Open HCPL-X.. =. V.. = V Logic Low Short Circuit I OSL ma V O = =. V V F = V, Output Current V O = = V V O = GND Logic High Short Circuit I OSH - ma =. V I F = ma, Output Current - = V Input Forward Voltage V F.. V T A = C I F = ma. HCNWXX.. T A = C.9 Input Reverse Breakdown BV R V I R = μa Voltage HCNWXX I R = μa Input Diode Temperature V F -. mv/ C I F = ma Coefficient HCNWXX T A -. Input Capacitance C IN pf f = MHz, V F = V, HCNWXX *For HCPL-X,. ma I F(ON) ma. **Typical V OH = -. V.

11 Switching Specifications (AC) * - C T A C,. V V,. ma I F(ON) ma, V V F(OFF). V. All Typicals at T A = C, = V, I F(ON) = ma unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time t PHL ns Without Peaking Capacitor,, to Logic Low Output Level HCNWXX With Peaking Capacitor Propagation Delay Time t PLH ns Without Peaking Capacitor,, to Logic High HCNWXX Output Level 9 With Peaking Capacitor Output Rise Time (-9%) t r ns, 9 Output Fall Time (9-%) t f ns, 9 Parameter Sym. Device Min. Units Test Conditions Fig. Note Logic High CM H HCPL-/, V/ s V CM = V = V, Common Mode HCPL- I F =. ma T A = C Transient HCPL- Immunity HCNW HCPL-/, V/ s V CM = V HCPL- I F =. ma HCPL-, V/ s V CM = kv HCNW I F =. ma Logic Low CM L HCPL-/, V/ s V CM = V V F = V, Common Mode HCPL- = V Transient HCPL- T A = C Immunity HCNW HCPL-/, V/ s V CM = kv HCPL- HCPL- HCNW *For HCPL-X,. ma I F(ON) ma. I F =. ma for HCPL-. I F =. ma for HCPL-.

12 Package Characteristics Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary V ISO V rms RH < %, t = min., Withstand Voltage * HCNWXX T A = C, Input-Output Resistance R I-O V I-O = Vdc HCNWXX T A = C T A = C Input-Output Capacitance C I-O. pf f = MHz, HCNWXX.. T A = C, V I-O = Vdc Input-Input Insulation I I-I. A Relative Humidity = %, Leakage Current t = s, V I-I = V Resistance (Input-Input) R I-I V I-I = V Capacitance (Input-Input) C I-I. pf f = MHz *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN -- Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note entitled Optocoupler Input-Output Endurance Voltage, publication number 9- Notes:. Each channel.. Derate total package power dissipation, P T, linearly above C free-air temperature at a rate of. mw/ C.. Duration of output short circuit time should not exceed ms.. For single devices, input capacitance is measured between pin and pin.. Device considered a two-terminal device: pins,,, and shorted together and pins,,, and shorted together.. The t PLH propagation delay is measured from the % point on the leading edge of the input pulse to the. V point on the leading edge of the output pulse. The t PHL propagation delay is measured from the % point on the trailing edge of the input pulse to the. V point on the trailing edge of the output pulse.. CM H is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V O >. V. CM L is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V O <. V.. For HCPL-/, V O is on pin. 9. Use of a. F bypass capacitor connected between pins and is recommended.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O A). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/ EN/DIN EN -- Insulation Characteristics Table, if applicable.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O A). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/ EN/DIN EN -- Insulation Characteristics Table.. For HCPL-/ only. Measured between pins and, shorted together, and pins and, shorted together.

13 V OL LOW LEVEL OUTPUT VOLTAGE V =. V V F = V I O =. ma - - I OH HIGH LEVEL OUTPUT CURRENT ma V O =. V V O =. V =. V I F = ma - - V O OUTPUT VOLTAGE V I O =. ma =. V T A = C. I O = -. ma.. T A TEMPERATURE C T A TEMPERATURE C I F INPUT CURRENT ma Figure. Typical logic low output voltage vs. temperature. Figure. Typical logic high output current vs. temperature. Figure. Typical output voltage vs. forward input current. I F FORWARD CURRENT ma..... I F V F HCPL-XX HCPL-XX... T A = C. V F FORWARD VOLTAGE V Figure. Typical input diode forward characteristic. I F FORWARD CURRENT ma..... HCNWXX T A = C I F V F..... V F FORWARD VOLTAGE V PULSE GEN. t r = t f = ns f = khz % DUTY CYCLE V O = V Z O = INPUT MONITORING NODE R HCPL-/ HCPL-XX HCNWXX C = GND pf OUTPUT V O MONITORING NODE C = pf THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. R. kω. kω I F (ON). ma ma Ω ma ALL DIODES ARE N9 OR N. INPUT I F * D kω V 9 Ω D D D PULSE GEN. t r = t f = ns f = khz % DUTY CYCLE V O = V Z O = INPUT MONITORING NODE R I F (ON) % I F (ON) ma HCPL-X C = GND pf OUTPUT V O MONITORING NODE C = pf THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. R.9 kω. kω I F (ON). ma ma Ω ma ALL DIODES ARE N9 OR N. * D kω V 9 Ω D D D OUTPUT V O t PLH PHL V OH. V VOL Figure. Circuit for t PLH, t PHL, t r, t f. *. μf BYPASS SEE NOTE 9.

14 t P PROPAGATION DELAY ns t PHL HCPL-XX HCPL-XX =. V, V C ( pf) PEAKING CAPACITOR IS USED. SEE FIGURE. *I F =. ma FOR HCPL-X DEVICES. t PLH T A TEMPERATURE C I F (ma).*.* - Figure. Typical propagation delays vs. temperature. t P PROPAGATION DELAY ns t PHL - HCNWXX =. V, V C ( pf) PEAKING CAPACITOR IS USED. SEE FIGURE. I F (ma) t PLH - - T A TEMPERATURE C.., P O MAXIMUM OUTPUT POWER PER CHANNEL (mw) T A = C T A = C SUPPLY VOLTAGE V Figure. Maximum output power per channel vs. supply voltage. T A = C V OH HIGH LEVEL OUTPUT VOLTAGE V TYPICAL V OH vs. AT I O = -. ma T A = C SUPPLY VOLTAGE V Figure. Typical logic high output voltage vs. supply voltage. t r, t f RISE, FALL TIME ns t r t f = V T A TEMPERATURE C Figure 9. Typical rise, fall time vs. temperature. B R IN V FF A HCPL-/ HCPL-XX HCNWXX. μf BYPASS OUTPUT V O MONITORING NODE V FF R B A HCPL-/. μf BYPASS OUTPUT V O MONITORING NODE PULSE GENERATOR V CM PULSE GENERATOR V CM V CM V V OH OUTPUT V O V OL V CM (PEAK) SWITCH AT A: I F =. ma** V O (MIN.)* SWITCH AT B: V F = V V O (MAX.)* * SEE NOTE, 9. ** I F =. ma FOR HCPL-/ DEVICES. Figure. Test circuit for common mode transient immunity and typical waveforms.

15 INPUT CURRENT THRESHOLD ma..9.. I F (ON) I F (OFF) HCPL-XX HCPL-XX =. V = V. I F (ON) I F (OFF) T A TEMPERATURE C INPUT CURRENT THRESHOLD ma Figure. Typical input threshold current vs. temperature...9. I F (ON). I F (OFF). I F (ON) I F (OFF). - HCNWXX =. V = V - - T A TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S HCPL-/ OPTION P S (mw) I S (ma) T S CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S 9 HCNWXX P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN --. HCPL-/ HCPL-XX HCNWXX ( V) ( V). kω DATA OUTPUT DATA INPUT TTL OR LSTTL * UP TO LSTTL LOADS OR TTL LOADS *. μf BYPASS Figure a. Recommended LSTTL to LSTTL circuit where ns propagation delay is sufficient.

16 ( V) Ω. kω pf HCPL-/ HCPL-XX HCNWXX ( V) DATA OUTPUT DATA INPUT TTL OR LSTTL * UP TO LSTTL LOADS OR TTL LOADS *. μf BYPASS Figure b. Recommended LSTTL to LSTTL circuit for applications requiring a maximum allowable propagation delay of ns. ( V) Ω*. kω pf* HCPL-/ HCPL-XX HCNWXX (. TO V) R L CMOS DATA OUTPUT DATA INPUT TTL OR LSTTL GND TOTEM POLE OUTPUT GATE V V V V R L. kω. kω. kω. kω * pf PEAKING CAPACITOR MAY BE OMITTED AND Ω RESISTOR MAY BE SHORTED WHERE ns PROPAGATION DELAY IS SUFFICIENT. **. μf BYPASS Figure. LSTTL to CMOS interface circuit. ( V) DATA INPUT TTL or LSTTL. kω D HCPL-/ HCPL-XX HCNWXX GND ( V) DATA INPUT Ω*. kω pf*. kω TTL OR LSTTL HCPL-/ HCPL-XX HCNWXX GND Figure. Alternative LED drive circuit. D (N) REQUIRED FOR ACTIVE PULL-UP DRIVER. OPEN COLLECTOR GATE * pf PEAKING CAPACITOR MAY BE OMITTED AND Ω RESISTOR MAY BE SHORTED WHERE ns PROPAGATION DELAY IS SUFFICIENT. Figure. Series LED drive with open collector gate (. k resistor shunts I OH from the LED). For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. Obsoletes AV-EN AV-EN - May,