Power Management & Multimarket

Transcription

1 TVS Diodes Transient Voltage Suppressor Diodes ESD15-B1-2 Series Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection Diodes ESD15-B1-2ELS ESD15-B1-2EL Data Sheet Revision 1., Final Power Management & Multimarket

2 Revision History: Rev. 4, Page or Item Subjects (major changes since previous revision) Revision 1., All Status change to Final Trademarks of Infineon Technologies AG AURIX, BlueMoon, COMNEON, C166, CROSSAVE, CanPAK, CIPOS, CoolMOS, CoolSET, CORECONTROL, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, EUPEC, FCOS, HITFET, HybridPACK, ISOFACE, I²RF, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PROFET, PRO-SIL, PRIMARION, PrimePACK, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SMARTi, SmartLEWIS, TEMPFET, thinq!, TriCore, TRENCHSTOP, X-GOLD, XMM, X-PMU, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, PRIMECELL, REALVIEW, THUMB of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Sattelite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update Final Data Sheet 2 Revision 1.,

3 Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection 1 Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection Diodes 1.1 Features ESD / Transient protection of signal lines exceeding standard: IEC (ESD): ±3 kv air / ±25 kv contact discharge IEC (EFT): ±5 A (5/5 ns) IEC (Surge): ±5 A (8/2 μs) One-line diode with ultra-small form factor down to.62 x.32 x.31 mm² (21) package size Bi-directional, symmetrical working voltage up to: V RWM =±5.5V Low capacitance C L =.3pF (typical) Very low clamping voltage, low dynamic resistance: R DYN =.36Ω (typ.) Pb-free package (RoHS compliant) and halogen free package 1.2 Application Examples USB 3.. 1/1/1 Ethernet, Firewire, DVI, HDMI, S-ATA, Display Ports Mobile HDMI Link, MDDI, MIPI, SWP, NFC 1.3 Product Description Pin 1 Pin 2 Pin 1 Pin 1 marking (lasered) TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd Figure 1 Pin configuration and Schematic diagram Table 1 Ordering Information Type Package Configuration Marking code ESD15-B1-2ELS TSSLP line, bi-directional N ESD15-B1-2EL TSLP line, bi-directional N Final Data Sheet 3 Revision 1.,

4 Characteristics 2 Characteristics Table 2 Maximum Ratings at T A = 25 C, unless otherwise specified 1) Parameter Symbol Values Unit Min. Typ. Max. ESD 2) air discharge contact discharge 1) Device is electrically symmetrical 2) V ESD according to IEC ) I PP according to IEC V ESD Peak pulse current (t p = 8 / 2 μs) 3) I PP 5 A Peak pulse power 3) P PK W t p = 8 / 2 μs 7 Operating temperature T OP C Storage temperature T stg C Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at T A = 25 C, unless otherwise specified 3 25 kv Figure 2 Definitions of electrical characteristics Final Data Sheet 4 Revision 1.,

5 Characteristics Table 3 DC Characteristics at T A = 25 C, unless otherwise specified 1) Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM 5.5 V Reverse current I R <1 2 na V R =5.5V Trigger voltage V t1 6.1 V Holding voltage V h V I R =1mA 1) Device is electrically symmetrical Table 4 AC Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Line capacitance C L.3.45 pf V R =V, f =1MHz.3.45 V R =V, f =1GHz Table 5 ESD and Surge Characteristics at T A = 25 C, unless otherwise specified 1) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Clamping voltage 2) V CL V I TLP =16A, t p =1ns I TLP =3A, t p =1ns Clamping voltage 3) I PP =2A, t p =8/2µs I PP =5A, t p =8/2µs Dynamic resistance 2) R DYN Ω t p =1ns 1) Device is electrically symmetrical 2) Please refer to Application Note AN21 [1]. TLP parameter: Z = 5 Ω, t p = 1ns, t r = 3ps, averaging window: t 1 = 3 ns to t 2 = 6 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between I TLP1 = 1 A and I TLP2 =5A. 3) I PP according to IEC (t p =8/2µs) Final Data Sheet 5 Revision 1.,

6 Typical Characteristics at T A = 25 C, unless otherwise specified 3 Typical Characteristics at T A = 25 C, unless otherwise specified I R [A] V R [V] Figure 3 Reverse current: I R = f (V R ) I R [A] T A [ C] Figure 4 Reverse current: I R = f(t A ), V R =5.5V Final Data Sheet 6 Revision 1.,

7 Typical Characteristics at T A = 25 C, unless otherwise specified.45.4 C L [pf].35.3 f = 1 MHz.25 f = 1 GHz V R [V] Figure 5 Line capacitance: C L = f (V R ), f =1MHz P PK [W] t p [s] Figure 6 Peak pulse power: P PK = f (t p ) Final Data Sheet 7 Revision 1.,

8 Typical Characteristics at T A = 25 C, unless otherwise specified 6 5 ESD15-B1-2series R DYN R DYN =.36 Ω 1 I TLP [A] Equivalent V IEC [kv] -2 R DYN =.36 Ω V TLP [V] Figure 7 Clamping voltage (TLP): I TLP = f(v TLP ) according ANSI/ESD STM Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z =5Ω, t p =1ns, t r =.6ns, I TLP and V TLP averaging window: t 1 =ns to t 2 = 6 ns, extraction of dynamic resistance using squares fit to TLP characteristics between I TLP1 = 1 A and I TLP2 = 5 A. Please refer to Application Note AN21[1] Final Data Sheet 8 Revision 1.,

9 Typical Characteristics at T A = 25 C, unless otherwise specified 7 6 ESD15-B1-2series R DYN R DYN =.9 Ω 2 1 I PP [A] R DYN =.9 Ω V CL [V] Figure 8 Pulse current (IEC61-4-5) versus clamping voltage: I PP = f(v CL ) Final Data Sheet 9 Revision 1.,

10 Typical Characteristics at T A = 25 C, unless otherwise specified Scope: 6 GHz, 2 GS/s V CL [V] V CL-max-peak = 135 V V CL-3ns-peak = 1 V t p [ns] Figure 9 IEC61-4-2: V CL = f (t), 8 kv positive pulse from pin 1 to pin 2 25 Scope: 6 GHz, 2 GS/s -25 V CL [V] V CL-max-peak = -134 V V CL-3ns-peak = -11 V t p [ns] Figure 1 IEC61-4-2: V CL = f (t), 8 kv negative pulse from pin 1 to pin 2 Final Data Sheet 1 Revision 1.,

11 Typical Characteristics at T A = 25 C, unless otherwise specified Scope: 6 GHz, 2 GS/s V CL [V] V CL-max-peak = 183 V V CL-3ns-peak = 14 V t p [ns] Figure 11 IEC61-4-2: V CL = f (t), 15 kv positive pulse from pin 1 to pin Scope: 6 GHz, 2 GS/s V CL [V] V CL-max-peak = -185 V V CL-3ns-peak = -14 V t p [ns] Figure 12 IEC61-4-2: V CL = f (t), 15 kv negative pulse from pin 1 to pin 2 Final Data Sheet 11 Revision 1.,

12 Application Information 4 Application Information Networkanalysor 5 Ohm port1 Insertion Loss in the application Networkanalysor 5 Ohm port2 Line Line ESD15-B1-2series ESD15-B1-2series_insertion_loss.vsd Figure 13 Insertion loss measured in 5 Ω environment -1 Insertion Loss [db] ESD15-B1-TSLP V / 1441MHz ESD15-B1-TSSLP V / 18142MHz f [MHz] Figure 14 Insertion loss vs. frequency of ESD15-B1-2xx in a 5 Ω system Final Data Sheet 12 Revision 1.,

13 Application Information Connector Protected signal line 1 I/O ESD sensitive device 2 The protection diode should be placed very close to the location where the ESD or other transients can occur to keep loops and inductances as small as possible. Pin 2 (or pin 1) should be connected directly to a ground plane on the board. Figure 15 Single line, bi-directional ESD / Transient protection Application_ESD5V3S1B-2LS.vsd Final Data Sheet 13 Revision 1.,

14 Package Information 5 Package Information 5.1 TSSLP-2-4 Top view Bottom view.32±.5 Figure 16 Cathode marking TSSLP-2-4 Package outline.5 MAX. 1) Dimension applies to plated terminals ).26±.35 1).2 ± ±.5 TSSLP-2-3-PO V Figure 17 TSSLP-2-4 Footprint Copper Solder mask Stencil apertures TSSLP-2-3-FP V2 4 Ey 8.35 Tape type Punched Tape Embossed Tape Ex Ey Cathode marking Figure 18 Ex TSSLP-2-4 Packing Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. TSSLP-2-3-TP V3 Figure 19 TSSLP-2-4 Marking (example) Final Data Sheet 14 Revision 1.,

15 Package Information 5.2 TSLP-2-2 Top view Bottom view.5 MAX..6 ±.5.65 ± ±.5 Cathode marking 1).5 ±.35 1) Dimension applies to plated terminals 1).25 ±.35 TSLP-2-19, -2-PO V1 Figure 2 TSLP-2-2 Package outline Copper Solder mask Stencil apertures TSLP-2-19, -2-FP V1 Figure 21 TSLP-2-2 Footprint 4.4 Cathode marking TSLP-2-19, -2-TP V2 Figure 22 TSLP-2-2 Packing 12 Type code Cathode marking TSLP-2-19, -2-MK V1 Figure 23 TSLP-2-2 Marking (example) Final Data Sheet 15 Revision 1.,

16 References References [1] Infineon Technologies AG, Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology, Application Note 21, RF and Protection Devices, April 22, 21, Rev.1. [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages Final Data Sheet 16 Revision 1.,

17 Published by Infineon Technologies AG