Annual Report Solid-State Electronics Department Halbleitertechnik/Halbleitertechnologie

Transcription

1 Annual Report 2010 Solid-State Electronics Department Halbleitertechnik/Halbleitertechnologie Faculty of Electrical and Electronic Engineering University Duisburg - Essen

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3 Annual Report 2010 Solid-State Electronics Department Prof.Dr.rer.nat. F.J.Tegude Universität Duisburg-Essen Fakultät für Ingenieurwissenschaften Institut für Technologien der Informationstechnik Halbleitertechnik/Halbleitertechnologie Lotharstrasse 55 / ZHO D Duisburg Germany Tel.: ++49 (0) (Secr.) Fax: ++49 (0) www: Editors: Dr.-Ing. Werner Prost Dr.-Ing. Wolfgang Brockerhoff Halbleitertechnik/ Halbleitertechnologie

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5 Annual Report Solid-State Electronics Department 1 1 Preface This report presents the teaching and research activities of the Solid State Electronics Department (Fachgebiet Halbleitertechnik/Halbleitertechnologie) during the year Let me thank all friends and partners for their support and fruitful cooperation, and all members and students of the Solid State Electronics Department for their excellent efforts and contributions, which is indispensable for future successful work. Duisburg, June 2011 Prof. Dr. rer. nat. F.-J. Tegude

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7 Annual Report Solid-State Electronics Department Table of Contents 1 Preface Members of the Department Teaching Activities Lectures and Laboratory Exercises Student Projects - Projektarbeiten Student Reports - Studienarbeiten Bachelor Thesis - Diplomarbeiten Diploma Thesis - Diplomarbeiten Master Thesis - Diplomarbeiten Doctor Thesis - Dissertationen Seminar on Semiconductor Electronics Research Activities Epitaxial Growth and Materials Axial GaAs Nanowire LED Formed by MOVPE Using DEZn and TESn in Vapour-Liquid-Solid Grown Mode I. Regolin, C. Gutsche, A. Lysov InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate R. Richter, K. Blekker, O. Benner, T. Waho (Sophia University, Tokyo, Japan) X-Ray Diffraction of GaN Layers and Nanostructures A. J. Stegemann, I. Regolin Device and Circuit Processing High Performance Submicron RTD Design for mm-wave Oscillator Applications A. Tchegho, B. Münstermann, R. Geitmann Nanowiretransistors in Electronic Circuits K. Blekker, O. Benner Development of Dry Etching Processes for the Fabrication of Germanium PIN Diodes B. Betting, F.-J. Tegude Spatially Resolved Opto-Electrical Performance of Axial GaAs Nanowire pn- Diodes A. Lysov, C. Gutsche, I. Regolin HBT-Technology and Design Improvements in Yield and On Wafer Variation B. Münstermann, G. Keller, A. Tchegho... 46

8 Annual Report Solid-State Electronics Department Investigation and Processing of Ohmic Contacts on Highly Doped n-ingaas P. Wang, A. Tchegho Device and Circuit Simulation, Measurement and Modelling Upgrade of the DC Measurement System Station to Increase the Measuring Accuracy A. Troost, B. Münstermann, I. Nannen Automation of a Micro Photoluminescence-Measurement Device for Spatially Resolved Measurements X. Tang, A. Lysov Opto-Electrical Characterization of Nanowire pn-junctions Audrey Nekam Simo, A. Lysov, C. Gutsche, M.Offer New Measurement Software For On-Wafer Characterization Of Microwave Voltage Controlled Oscillators K. Arzi, B. Münstermann, I. Nannen Characterization and Optimization of Readout Electronics of MEMS Based Uncooled Long Wave Infrared (LWIR) Sensor A. Troost, D. Oshinubi (Robert Bosch GmbH), F.-J. Tegude, W. Brockerhoff Conference Contributions Publications Research Projects The Mobile Electronic School Lab (MESLAB)... W. Brockerhoff Guide to the Solid-State Electronics Department... 78

9 Member and Guests of the Department 3 2 Members and Guests of the Department 379- office head of the department Prof. Dr.rer.nat. Franz-Josef Tegude LT 207 franz.tegude@uni-due.de secretary Dagmar Birke LT 206 dagmar.birke@uni-due.de scientific staff Dipl.-Ing. Oliver Benner since 09/ LT 106 oliver.benner@uni-due.de Dipl.-Ing. Kai Blekker LT 106 kai.blekker@uni-due.de Dr.-Ing. Wolfgang Brockerhoff (AOR) LT 205 wolfgang.brockerhoff@uni-due.de Dipl.-Ing. Christoph Gutsche LT 203 christoph.gutsche@uni-due.de Dipl.-Ing. Gregor Keller since 12/ LT 203 gregor.keller@uni-due.de Dipl.-Phys. Andrey Lysov LT 203 andrey.lysov@uni-due.de Dipl.-Ing. Benjamin Münstermann LT 204 benjamin.muenstermann@uni-due.de Dipl.-Ing. Ingo Nannen LT 204 ingo.nannen@uni-due.de Dipl.-Ing. Artur Poloczek LT 104 artur.poloczek@uni-due.de Dr.-Ing. Werner Prost LT 205 werner.prost@uni-due.de Dipl.-Ing. Ingo Regolin LT 104 ingo.regolin@uni-due.de Dipl.-Ing. Anselme Tchegho LT 204 anselme.tchegho@uni-due.de technical staff Udo Doerk LT 202 udo.doerk@uni-due.de Dipl.-Ing. Ralf Geitmann LT 202 ralf.geitmann@uni-due.de Svenja Köppen since 08/ LT 104 svenja.koeppen@uni-due.de Dipl.-Ing. Wolfgang Molls LT 201 wolfgang.molls@uni-due.de Andrea Merz LT 104 andrea.osinski@uni-due.de Ing. (grad.) Reimund Tilders LT 201 reimund.tilders@uni-due.de apprentices Gordon Kollmorgen since 08/ LT 105 gordon.kollmorgen@uni-due.de Sandra Schulte since 08/ LT 105 sandra.schulte@uni-due.de

10 4 Annual Report Solid-State Electronics Department students Quitsch, Wolf- Arzi, Khaled 04/ /2010 Alexander 04/ /2010 Chakroun, Faten until 03/2010 Richter, René until 09/2010 Grozna, Marcell since 06/2010 Stegemann, Almut Johanna since 12/2010 Iavarone, Dino until 06/2010 Tang, Xupu since 10/2010 Muckensturm, Kai- Marcel Nekam Simo, Audrey Cynthia since 11/2010 Wierzkowski, Thorsten since 05/2010 since 06/2010 Guests of the department: Prof. Takao Waho, Sophia University, Tokyo, Japan

11 Teaching Activities 5 3 Teaching Activities 3.1 Lectures and Laboratory Exercises Lectures and exercises Schedule International Studies in Engineering (ISE) Electrical and Electronic Engineering Nanoengineering. B.Sc. M.Sc B.Sc. M.Sc B.Sc. M.Sc. Solid-State Electronics Festkörperelektronik Basic Electronic Devices Grundlagen Elektronischer Bauelemente 4 th sem. (EEE) 5 th sem. (EEE) 2 nd sem. 4 th sem. 3 rd sem. 5 th sem. Basic Electronic Circuits Grundlagen Elektronischer Schaltungen 2 nd sem. Fundamentals of Electronics Grundlagen der Elektronik Basic FET- and Bipolar Transistor Circuits Grundschaltungen der FET und Bipolarelektronik Components for Wireless Communication Komponenten für die drahtlose Kommunikation Technology of Nanostructures Nanostrukturierung Nanoelectronics Nanoelektronik Semiconductor Microelectronics Technology 1/ III-V Technologies and Components 1/ Halbleitertechnologie 1 5 th sem. (CSCE, ACE) optional 2 nd sem. 2 nd sem. 1 st sem. 3 rd sem.

12 6 Annual Report Solid-State Electronics Department Laboratory exercises Schedule diploma course International Studies in Engineering (ISE) Electrical and Electronic Eng. Nanoengineering. B.Sc. M.Sc B.Sc. M.Sc B.Sc. M.Sc. Introduction to Operational Amplifiers Praktikum Operationsverstärker Semiconductor Technology 2 Halbleitertechnologie 2 Semiconductor Technology Praktikum Halbleitertechnologie Basic Electronic Circuits Praktikum Grundlagen Elektronischer Schaltungen Electronics and RF Praktikum Grundlagen Elektronischer und Hochfrequenzschaltungen Basic FET- and Bipolar Transistor Circuits Grundschaltungen der FET- und Bipolarelektronik 2 nd sem. optional optional 5 th sem. 2 nd sem. 2 nd sem. Seminars and Colloquia Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik Seminar on Epitaxial Problems 6

13 Teaching Activities 7 Lectures and Exercises: Solid-State Electronics Festkörperelektronik Starting with basics of Quantum Physics, i.e. Heisenberg s uncertainty relations, Schroedinger equation, atomic models, this course gives an introduction to the electronic properties of solid-state materials. Using Schroedinger s equation the simple Kronig-Penney bandstructure model is developed to distinguish between isolators, metals and semiconductors. The carrier statistics and densities in these materails for electrons and holes is develoepd and, together with transport properties especially in semiconductors (microscopic model of the mobility), the electrical conductivity is evaluated. Poisson and continuity equations are derived ending up with the fundamentals of the pn-junction and MOS-system. Basic Electronic Devices / Fundamentals of Electronics Grundlagen Elektronischer Bauelemente / Grundlagen der Elektronik Based on the solid-state electronics fundamentals MOS-capacitors and charge-coupled devices (CCD) are treated. Subsequently, the basics of field-effect transistors (MOSFET, junction FET (MESFET, JFET) and heterostructure-fet (HFET)) and bipolar devices (pn-diode, npn- and pnp-bipolar transistors, tunnel diodes and thyristors) are covered and the DC-characteristics of these devices are derived. Basic Electronic Circuits / Basic FET- and Bipolar Transistor Circuits Grundlagen Elektronischer Schaltungen / Grundschaltungen der FET- und Bipolarelektronik Based on the small-signal analysis of electronic devices like diodes, field-effect transistors (FET) and bipolar transistors fundamental methods to calculate and design komplex electronic circuits are introduced and applied. Basic circuits and their characteristics are analysed and discussed in detail. Both, analog and digital circuits are treated. Components for Wireless Communications Komponenten für die drahtlose Kommunikation This lecture introduces the fundamentals of electronic circuits for wireless communication systems. Topics are fundamentals of wireless systems and architectures and the principles and technology of modern active electronic bipolar and FET components; silicon transistor technology as well as very high frequency heterojunction tecnology will be covered. Circuit topics range from oscillators to amplifiers and mixers where we will investigate linear and non-linear properties and match, gain, power, stability and noise.

14 8 Annual Report Solid-State Electronics Department Semiconductor Microelectronics 1 Halbleitertechnologie 1 The semiconductor microelectronics technology lectures are devoted to III/V-semiconductor heterostructures for high speed electronic devices. The process steps from crystal growth to circuit fabrication are discussed. The first semester is focused on heterostructure material issues. Modern growth techniques like molecular beam epitaxy (MBE) and metal-organic vapour-phase epitaxy (MOVPE) are discussed in terms atomic layer control of thickness, composition, and doping. High Resolution X-ray diffraction, photoluminescence, and ellipsometry are explained for nondestructive material assessment in the mono-layer scale. The second semester is devoted to microelectronic fabrication techniques for high speed (f 100 GHz) devices and circuits. The lateral and vertical processing of epitaxial films, insulating layers, and metallizations are presented for high performance monolithic high speed analog and digital integrated circuits. Technology of Nanostructures Nanostrukturierung The lecture should improve the knowledge on the technological procedures to fabricate nanostructured materials and components as well as the accompanying analysis methods with help of actual examples from the electronic device production. This contains: Modern growth technologies for layer deposition in the range of mono-atom-layers like metal-organic vapour phase epitaxy (MOVPE) and molecular beam epitaxy (MBE), with regard to composition, control of the layer thickness and doping. Use of self organization mechanisms and template processes. Advanced high-resolution lithography procedures for the production of nano-scaled structures (electron beam, X-ray as well as scanning force lithography). Micro- and nano-electronic fabrication techniques for electronic and opto-electronic nanocomponents, e.g. for high frequency applications. Lateral and vertical processing of epitaxial films, insulating layers and metallisations up to monolithic integrated nano-electronic circuits. Non destructive analysis of nano-structures and devices by high-resolution X-ray difraction and by the use of the interaction of electron probes with the materials. Analysis methods with mechanical probes (scanning tunneling and the scanning force microscope) 8

15 Teaching Activities 9 Nanoelectronics Nanoelektronik The lecture treats electronic aspects of the nanotechnology and differs from the areas nano-photonic and nano-magnetism. It starts with a classification of suitable materials and nano-structures and briefly introduces fabrication techniques. The Boltzmann transport equation, transport mechanisms, in particular tunnel and ballistic transport, are treated. Transistors with two-dimensional electron gas as channel (2DEG), resonance tunnel diodes and transistors, single Electron transistors, Coulomb blockade as well as electromechanical nano-elements on semiconductor and carbon base are presented and discussed. Simple basic functions as examples for a nano-circuit technology conclude the lecture. Laboratory exercises Introduction to Operational Amplifiers Praktikum Operationsverstärker The aim of this course is the understanding of the basic principles and the characteristics of operational amplifiers (OpAmps). The laboratory exercises demonstrate their applicability in electronic circuits enabling the students to an independent design and understanding of complex circuits. Starting with the measurement and interpretation of the most important characteristic parameters of OpAmps, circuits like adders and multipliers, amplifiers and active filters are intensively calculated and investigated. Oscillators and generators are designed and measured. Semiconductor Technology 2 Halbleitertechnologie 2 Electronic devices and circuits, based on III-V semiconductors, are fabricated in the clean room facilites under supervision. Produced devices are electrically characterised Semiconductor Technology Praktikum Halbleitertechnologie The laboratory covers various areas of semiconductor technology, which are under investigation in the Department of Engineering Sciences at the University of Duisburg-Essen. It offers topics from optoelectronics, silicon semiconductor technology, the technology for high-frequency devices made from III-V semiconductors and nanotechnology for quantum devices. The focus of the experiments lays on the manufacturing and technology-based characterization of components, making clear the relationship between production parameters and components. Detailed descriptions are available for the individual experiments, within which the necessary fundamentals are recapitulated.

16 10 Annual Report Solid-State Electronics Department Comprehension questions and tasks are provided, to be solved as preparation at home. The labs include a colloquium to audit, the experimental procedure and the minutes. Experiments of the Optoelectronics Dept. (OE) Photovoltaics Packaging Experiments of the Solid-State Electronics Dept. (HLT) Fabrication of semiconductor test structures Characterization of the manufactured test structures Experiments of the Dept. of Electrical Engineering and Information Technology (WET) Nanolithography for quantum nano-devices Analysis of nanostructured devices Experiments of the Dept. of Electronic Devices and Circuits (EBS) Characterization of MOS capacitors and transistors metrology in semiconductor manufacturing Electronics and RF Praktikum Grundlagen Elektronischer und Hochfrequenzschaltungen The lab combines topics of RF-and Microwave Engineering with topics from Solid State Electronics for RF- and Microwave applications. The lab experiments are supported by extensive material on the theoretical fundamentals and by questions and tasks to be prepared by the students before the lab. The part on Electronics is organized by Fachgebiet Halbleietertechnologie and incorporates experiments on Schottky diode capacitance, switching behaviour of bipolar transistors and the dc current-voltage characteristic of field effect transistors. The part on RF technology is organized by Fachgebiet Hochfrequenztechnik and provides 12 experiments which cover the main theoretical concepts taught in the MRFT course. Basic Electronic Circuits / Basic FET- and Bipolar Transistor Circuits Praktikum Grundlagen Elektronischer Schaltungen / Grundschaltungen der FET- und Bipolarelektronik The lab is a supplement of the lecture "Basic FET and Bipolar Circuits" to intensify the understanding of the analysis of electronic circuits. 10

17 Teaching Activities 11 It consits of three practical exercises: - the investigation of simple digital circuits - the switching behaviour of bipolar transistors and - the analysis of amplifier circuits using a circuit simulator Seminars and Colloquia Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik Within this seminar actual topics of the semiconductor electronics are discussed. Students, but also members of the department, report about their own work. Seminar on Epitaxial Problems Problems of the epitaxial growth of semiconductor structures are analysed, results are interpreted and future trends are discussed.

18 12 Annual Report Solid-State Electronics Department 3.2 Student Projects (Projektarbeiten) 1. AUDREY CYNTHIA NEKAM SIMO, MADOUNFA GNINGHA, LIONEL NGUEMNENG TUMCHOU, ELEKTRISCHE CHARAKTERISIERUNG VON DOTIERTEN GAAS-NANODRÄHTEN (submitted: ) 2. THORSTEN WIERZKOWSKI, SARAH DOHLE MASKIERUNG UND SCHÄDIGUNG WÄHREND DES TROCKENÄTZENS VON GAN-SCHICHTEN (submitted: ) 3.3 Student Reports (Studienarbeiten) 1. AARON TROOST Erweiterung des DC-Messplatzes zur Erhöhung der Messgenauigkeit (submitted: ) 3.4 Bachelor-Thesis (Bachelorarbeiten) 1 ALMUT JOHANNA STEGEMANN Röntgendiffraktometrie an GaN Schicht- und Nanodrahtstrukturen (submitted: ) 2. AUDREY CYNTHIA NEKAM SIMO Opto-elektrische Charakterisierung von Nanodraht pn-übergängen (submitted: ) 3. KHALED ARZI Entwicklung einer Software zur Hochfrequenz- und Rauschcharakterisierung von Mikrowellen-Oszillatoren (submitted: ) 4. XUPU TANG Automatisierung eines Mikro-Photolumineszenz Messplatzes für ortsaufgelöste Messungen (submitted: )

19 Student Projects Diploma Thesis (Diplomarbeiten) 1. BJÖRN BETTING Entwicklung von Trockenätzprozessen für die Herstellung von Germanium pin- Dioden (submitted: ) 2. PING WANG Untersuchung und Herstellung von Ohmschen Kontakten auf hochdotiertem n- InGaAs (submitted: ) 3. OLIVER BENNER Nanodraht-Transistoren in elektronischen Schaltungen (submitted: ) 3.6 Master Thesis (Masterarbeiten) 1. RENÉ RICHTER Integration von Nanodraht-Transistoren in mikroelektronischen Schaltungen (submitted: ) 3.7 Doctor Thesis (Dissertation) 1. QUOC THAI DO Ein Beitrag zur Entwicklung des Omega-Gate InAs Nanodraht Feldeffekttransistors (date of examination: ) 2. INGO REGOLIN Wachstum von Nanodrähten mittels MOVPE (date of examination: )

20 14 Annual Report Solid-State Electronics Department 3.8 Seminar on Semiconductor Electronics BENJAMIN MÜNSTERMANN, REPORT ON STATE-OF-THE-ART OF THE PROJECT 'RTD/HBT Oszillatoren für Ku- und Ka-Band für die Satellitenkommunikation' KAI BLEKKER, CHRISTOPH GUTSCHE, REPORT ON STATE-OF-THE-ART OF THE PROJECT 'InAs Nanodraht Transistoren' INGO REGOLIN, REPORT ON: 24. DGKK Workshop 'Epitaxie von III/V Halbleitern', Berlin, Germany, WERNER PROST, ANDREY LYSOV, REPORT ON: 'Nanowire Growth Workshop' (NGW), Paris, France, INGO NANNEN, REPORT ON STATE-OF-THE-ART OF THE PROJECT 'pin-tia-arrays' SARAH DOHLE, THORSTEN WIERZKOWSKI, REPORT ON THE PROJECT WORK: 'Maskierung und Schädigung während des Trockenätzens von GaN-Schichten' LIONEL NGUEMNENG TUMCHOU, AUDREY CYNTHIA NEKAM SIMO, MADOUNFA GNINGHA, REPORT ON THE PROJECT WORK 'Elektrische Charakterisierung von dotierten GaAs-Nanodrähten' AARON TROOST, REPORT ON THE STUDENT THESIS: 'Erweiterung des DC-Messplatzes zur Erhöhung der Messgenauigkeit' KHALED ARZI, REPORT ON THE BACHELOR THESIS: 'Entwicklung einer Software zur Hochfrequenz- und Rauschcharakterisierung von Mikrowellen- Oszillatoren' BENJAMIN MÜNSTERMANN, REPORT ON: 'German Microwave Conference 2010' (GeMic), Berlin, Germany, FRANZ-JOSEF TEGUDE, REPORT ON 'Gigahertz Symposium 2010', Lund University, , WERNER PROST, REPORT ON research stay at Japan, march/april OLIVER BENNER, REPORT ON THE DIPLOMA THESIS: 'Nanodraht-Transistoren in elektronischen Schaltungen' BJÖRN BETTING, REPORT ON THE DIPLOMA THESIS: 'Entwicklung von Trockenätzprozessen für die Herstellung von Germanium pin- Dioden'

21 Seminar on Semiconductor Electronics XUPU TANG, REPORT ON THE BACHELOR THESIS: 'Automatisierung eines Mikro-Photolumineszenz Messplatzes für ortsaufgelöste Messungen' ANSELME TCHEGHO, BERICHT ÜBER DIE TAGUNG: 'IEEE Int. Conf. on InP and Related Materials' (IPRM), Kagawa, Japan, ANDREJ LYSOV, REPORT ON: '15th Int. Conf. on Metalorganic Vapour Phase Epitaxy' (MOVPE) (IC MOVPE), Lake Tahoe, USA, FRANZ-JOSEF TEGUDE, REPORT ON: 'Annual Device Research Conference' (DRC), South Bend, IN, USA, AUDREY CYNTHIA NEKAM SIMO, REPORT ON THE BACHELOR THESIS: 'Opto-elektrische Charakterisierung von Nanodraht pn-übergängen' ALMUT JOHANNA STEGEMANN, REPORT ON THE BACHELOR THESIS: 'Röntgendiffraktometrie an GaN Schicht- und Nanodrahtstrukturen' PING WANG, REPORT ON THE DIPLOMA THESIS: 'Untersuchung und Herstellung von Ohmschen Kontakten auf hochdotiertem n- InGaAs' WERNER PROST, BERICHT ÜBER DIE TAGUNG: '2010 Int. Conf. on Solid State Devices and Materials' (ssdm), Tokyo, Japan, RENÉ RICHTER, REPORT ON THE MASTER THESIS: 'Integration von Nanodraht-Transistoren in mikroelektronischen Schaltungen' CHRISTOPH GUTSCHE, OLIVER BENNER, BERICHT ÜBER DIE TAGUNG: 'Nanoelectronic Days 2010 (ND)', Aachen, Germany, ANDREY LYSOV, REPORT ON: '5th Nanowire Growth Workshop 2010 (NGW)', Rom, Italy, FRANZ-JOSEF TEGUDE, REPORT ON: 'Symposium on Opto- and Microelectronic Devices and Circuits 2010' (SODC), Berlin, Germany, ANSELME TCHEGHO, REPORT ON STATE-OF-THE-ART OF THE PROJECT: 'Optoelektronische Digitalschaltungen auf der Basis von Resonanztunnel-dioden und Photodioden' GREGOR KELLER, BERICHT REPORT ON STATE-OF-THE-ART OF THE PROJECT: 'Simulation von Heterostrukturbipolartransistoren (HBT)'

22 16 Annual Report Solid-State Electronics Department

23 Annual Report Solid-State Electronics Department 17 4 Research Activities 4.1 Materials, Growth and Characterization

24 18 Annual Report Solid-State Electronics Department Axial GaAs Nanowire LED Formed by MOVPE Using DEZn and TESn in Vapour-Liquid-Solid Grown Mode Scientist: I. Regolin, C. Gutsche, A. Lysov Introduction III/V direct band gap semiconductor nanowires excite great research interest due to their potential application in future nanoscaled electronic and especially optoelectronic devices. Among other techniques, the Vapour-Liquid-Solid (VLS) growth mechanism [1] in particular has demonstrated various high crystal quality semiconductor nanowires grown at exceptionally high growth rate. However, many fundamental questions, especially about the doping mechanism, still remain open. Until now there have only been a few publications describing successful III/V semiconductor doping of VLS-grown nanowires. A full axial pn-junction with low current density, grown by VLS, was demonstrated using InP [2-3]. For GaAs nanowires, successful p-type doping via VLS mechanism was recently published [4]. In this contribution, we report on axial pn-gaas nanowires LEDs grown on (111)B GaAs substrates by metal organic vapor-phase epitaxy (MOVPE) in the VLS growth regime based on Au seed particles. For optoelectronic characterization nanowires were transferred to insulating carrier substrates and contacted via electron beam lithography. First electroluminescence measurements show intense light emission at around 870 nm. Experimental Setup Growths were performed on (111)B GaAs substrates in a AIX200 RF MOVPE reactor with a total pressure of 50 mbar and a total gas flow of 3.4 l/min. Nitrogen was used as carrier gas and hydrogen as pick-up gas through the bubblers. Tertiarybutylarsine was used as group-v and trimethylgallium as Ga precursor. Diethylzinc (DEZn) and tetraethyl tin (TESn) were used as p- and n-type dopant precursors, respectively. Au was used for the growth seeds in all experiments. Either monodisperse Au colloids (100 nm and 150 nm) or polydisperse nanoparticles were used. The polydisperse nanoparticles were formed from a nominally 2.5 nm thin Au-layer during the annealing step prior to a growth run. The annealing step was carried out at 600 C for 5 minutes under tertiarybutylarsine flow. In all experiments the initial growth starts with a nominally undoped nanowire stump at 450 C for better nucleation. The doped nanowire growth was performed at 400 C with a V/III ratio of 2.5. A total growth time of about 50 minutes was chosen to realize structures up to 20 µm in length. The as-synthesized GaAs nanowires were characterized by means of a LEO 1530 scanning electron microscope (SEM). The nanowire suspension was dropped onto special prepared carrier substrates and some nanowires contacted via E-beam lithography to enable I-V measurements using a Keithley SCS 4200 current-voltage analyzer. For the electroluminescence (EL) measurements the samples were placed in a cold-finger cryostat equipped with a window and the sample holder mounted on a commercial Attocube XYZ Piezo translation system.

25 Epitaxial Growth and Materials 19 Results Fig. 1 shows a pn-gaas nanowire structure grown within 50 minutes. The dopant precursor was changed from DEZn to TESn after 25 minutes. No growth interruption sequence was carried out while changing from p-type to n-type doping. The length of the nanowires reaches up to 20 µm while the diameters vary with the dimension of the seed particles formed from a nominally 2.5 nm thin evaporated Au-layer. Detailed investigations of p-gaas:zn nanowires showed that a maximum carrier concentration of about to 2x10 19 cm -3 is achievable for the p-doped part, before wire deformation occurs. For n- GaAs:Sn we achieved a maximum carrier concentration of 1.x10 18 cm -3 in our n-gaas nanowires. The type of conductivity was independently proven by the transfer characteristics of nanowire MIS- FETs fabricated using either n- or p-type doped nanowires. 1 µm Fig. 1 Ensemble of pn-gaas nanowires with different diameters grown using an annealed thin Au-film of nominally 2.5 nm as growth seed For electrical measurements ohmic contacts have to be patterned on the pn-nanowire. The use of multiple contacts enables both the characterization of the whole pn-junction and also the investigation of the individually doped wire parts. While a non-annealed Ti/Pt/Ti/Au metallization was used for the p-doped part of the wire, typical Ge/Ni/Ge/Au annealed contacts were used for the n-gaas wire. The maximum annealing temperature for the n-contacts was reduced to 320 C in order to avoid the possible diffusion of Ga atoms into the Ge/Ni/Ge/Au. Fig. 2 shows the I-V characteristics of a single pn-gaas nanowire structure both in the linear as well as in the semi-logarithmic scale. The I-V characteristics clearly shows pn-diode behavior with excellent blocking in the reverse direction in the low pa-regime. The forward current is about 6 orders of magnitude higher and reaches the µa range with an ideality factor of about 2 at low current levels. The total current is limited by the lower conductivity of the n-part including its non-optimized ohmic contacts.

26 20 Annual Report Solid-State Electronics Department Fig. 2 Typical I-V characteristics of single pn-gaas nanowire in the linear (left axis), as well as in the semi-logarithmic scale (right axis) The diffusion voltage V D = 1.4 V corresponds to the band gap of the GaAs material. The axial pn- GaAs nanowire diodes I-V performance clearly exceeds previously published data of axial InP pnnanowire diodes [2, 3]. Fig. 3 shows electroluminescent spectra from a single pn-junctioned nanowire taken at 9 K under different excitation currents. The emission peak at ev is scalable with an excitation current. We attribute the peak to the tunneling assisted transition between donator and acceptor band, taking place in the compensated region of the pn-junction. Fig. 3 Electroluminescence spectra taken at the single pn-junctioned GaAs nanowire for different excitation levels at 9 K

27 Epitaxial Growth and Materials 21 Detailed optical investigations are given in the annual report from Andrey Lysov X.X.X, which also investigates the abruptness of the pn-junction. However, a graded doping junction is estimated to be likely due the exchange of dopants in the Au-seed during growth. Conclusion Axial pn-gaas LED nanowires were grown in the VLS mode using DEZn and TESn as dopant precursors. The devices show typical pn-diode I-V characteristics and currents up to a few µa in the forward direction. The current is limited by the conductivity of the n-side due to the relatively low carrier concentration of around to 1x10 18 cm -3. The reverse direction shows current blocking up to at least 10 V. First electroluminescence measurements show intense light emission at around 870 nm. Acknowledgement The authors acknowledge financial support of the German Research Foundation (DFG) within the Sonderforschungsbereich SFB 445 Nanoparticles from the gas-phase. References [1] R. S. Wagner and W. C. Ellis, Appl. Phys. Lett. 4 (1964) 89 [2] E. D. Minot, F. Kelkensberg, M. van Kouwen, J. A. van Dam, L. P. Kouwenhoven, V. Zwiller, M. T. Borgstrom, O. Wunnicke, M. A. Verheijen, E. P. A. M. Bakkers, Nano Lett. 4 (2004) [3] M. T. Borgström, E. Norberg, P. Wickert, H. A. Nilsson, J. Trägardh, K. A. Dick, G. Statkute, P. Ramvall, K. Deppert, L. Samuelson, Nanotechnology, 19, No. 44, (2008) 6. [4] C. Gutsche, I. Regolin, K. Blekker, A. Lysov, W. Prost, and F.-J. Tegude, J. Appl. Phys. 105 (2009)

28 22 Annual Report Solid-State Electronics Department InAs nanowire circuits fabricated by field-assisted selfassembly on a host substrate Student Scientist in collaboration with R. Richter K. Blekker, O. Benner T. Waho (Sophia University, Tokyo, Japan) Introduction Today, nanowire devices are referred to as a qualified successor of CMOS electronics. Both a performance superior to silicon (Si) MOSFETs and a rational, cost-efficient technique to implement multiple nanowire devices into circuits are recommended. We propose to transfer the nanowires from a growth substrate onto a carrier or host substrate using field-assisted self-assembly. This approach allows for the implementation of epitaxial nanowire independent of the choice of growth substrate and its crystal orientation. It avoids any constraints of high qualitative nanowire growth which the process needs and limitations of circuit fabrication. In this paper we present the heterogeneous integration of InAs nanowire FET as superior performance key devices into existing patterns or circuits. The electric field applied to the prepatterned electrodes causes a dipole moment within the nanowires which moves and aligns the nanowires to the regions of the highest field strength located between the electrodes [1]. Using this so called field-assisted self-assembly (FASA) there is no limitation in the choice of orientation or distribution across the substrate which makes this approach very interesting for heterogeneous integration into any microelectronic and nanoelectronic circuits including Si CMOS. With optical and electron beam lithography nanowire transistors are fabricated and heterogeneously integrated into circuits. Both, inverter and sample & hold circuits are realized. The fabricated circuits are electrically characterized and simulated with Advanced Design System (ADS). Experimental The InAs NWs were synthesized in a metal-organic vapor phase epitaxy using the vapor-liquidsolid growth mode on GaAs(111)B or InAs(111)B growth substrate. The grown 12 µm long InAs nanowires with 50 nm diameter were mechanically transferred into isopropyl alcohol. The nanowire solution was dropped on a host substrate with various pre-patterned electrodes of 15 nm titanium (Ti) (cf. Fig. 1a-b). In order to assemble the nanowires by FASA a sinusoidal voltage with 10 V peak-to-peak and a frequency of 10 khz was applied to the electrode pairs for two minutes. After assembling the nanowires, the interconnects between the FASA electrodes were removed by means of wet chemical etching. Next, the ohmic contacts of Ti and Au were patterned followed by room temperature deposition of 25 nm silicon nitride (SiN x ) gate dielectric. Finally, omega-shaped topgates of about 1 µm length were formed of Ti and Au. High-speed measurements are performed on wafer using G-S-G probes. For the clock signal a square wave voltage with a frequency f CLK = 5xf IN is used. The output signal is measured wiht active probes in order to avoid a short cut due to the 50 Ohms characteristic impedance of the high-speed measurement set-up. This acitve probe needle

29 Epitaxial Growth and Materials 23 contains, in addition to the RC network, an active amplifier, thus the measured signal is decoupled from the DUT. Inverter Circuit Fig. 1(a-c) shows a SEM micrographs of the fabricated inverter circuit using depletion-mode InAs NWFET. The active load was realized with a gate-source short-circuited (V GS = 0 V) NWFET (cf. fig. 1 (b)). In Fig. 1d the static transfer characteristic for an input voltage V IN at a supply voltage V DD = 1 V is given. The output voltage V OUT of an inverter should be as close as possible to 0 V in low state and to V DD in high state, respectively. The latter is achieved almost perfectly pointing out a sufficiently high off-resistance of the drive transistor. A small signal gain of up to about 5 was achieved. Figure 1e shows the dynamic characteristics of one of the fabricated inverters for a square-wave input signal at a frequency of 20 MHz. The output signal was corrected for the attenuation and phase shift of the setup including the active probe identified by measurements using a through test element. An adapted EEMOS M1 model was used to represent the drive and load transistor with respect to their wire number and the corresponding scaling of current and small signal parameters. The effect of the capacitive load on the time constant and the asymmetric frequency response are in good agreement with the presented results. d e V out [V] V in [V] Time [ns] Fig. 1 Inverter fabricated from self-assembled multiple InAs nanowires: (a) mask layout for FASA self-assembly of inverter circuits for high frequency speed characterization, (b) detail of one inverter with FASA line in bright color, (d) static transfer characteristics at VDD = 1 V, and (e) dynamic transfer characteristic.

30 24 Annual Report Solid-State Electronics Department For detailed understanding of the experimental results, the electronic circuits were simulated using the simulation software Advanced Design System (ADS) from Agilent. In a first step a MOSFET model was adapted using NWFET measurement results. Figure 2a shows the adapted transfer characteristic of the MOSFET model as well as the simulation results of the inverter circuit. The simulation results show good agreement with the measured curves. The measured absorption of the inverter circuit is higher than the absorption in the simulation (fig. 2 b). This difference can be caused by the measurement setup and parasitic capacities, which are not included in the simulation. In fig. 3 c) an oscilloscope with 1 MΩ input resistance was used to simulate the inverter circuit. The output signal has a much larger amplitude than previously, the absorption is only 8 decibels. Therefore, one can assume that a large part of the absorption is due to the poor 50 Ω adaptation drain current I D [µa] (a) Model NWFET M4120 input voltage V IN [V] V (b) V out3 V IN output voltage V out3 [V] gate-source voltage V GS [V] time t [ns] -1.0 Fig. 2 a) adapted transfer characteristic of the nanowire MISFET, and(b) simulation results of the inverter circuit measured with an oscilloscope with 1 MΩ input resistance Sample& Hold Circuit Fig. 3 shows a simple S/H circuit consisting of a switching FET M1, a hold capacitor C h, and an output buffer (transistors M2, M3), where the analog input signal is held as a certain amount of charges when M1 is turned off. For high speed S/H performance a very high transconductance transistor is needed which perfectly fits to the performance of InAs NW MISFET [2]. Therefore, the transistor M1 is an InAs NW MISFET. On the other hand a high current driver is required which has been realized by conventional InP heterojunction MISFETs again by heterogeneous integration. Fig. 2c shows the input and output waveforms experimentally obtained from the circuit shown in Fig. 2b which confirms the basic sample-and-hold circuit operation The observed offsets at the transition from the track mode to the hold mode are due to the clock feed through which can be suppressed by a novel differential scheme S/H circuit enabling 7 bit resolution up to almost 1 GHz sampling frequency [3].

31 Epitaxial Growth and Materials 25 (a) InP HFET M3 V DD (b) M2 clk V in M1 NW MISFET M2 V out M1 C h C h 10 µm M3 (c) V out O 0.2 [V] [V] O V ref Fig Time (ns) Sample & hold Circuit: (a) schematic, (b) SEM micrograph, and (c) input and output waveforms obtained experimentally at 100 MHz sampling frequency Summary A novel heterogeneous integration scheme for heterogeneous nanowire transistor implementation in existing circuits is proposed. Both an inverter circuit and a sample & hold circuit function is experimentally confirmed. A combination of InAs nanowire transistor with InP-based heterojunction MISFET is used to form sample & hold circuits at 100 MHz sampling frequency. These data outperform existing nanowire circuits and underline the potential of this approach.

32 26 Annual Report Solid-State Electronics Department Acknowledgment This work is supported from JST-DFG Programme on Nanoelectronics, project Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems. References: [1] (a) P. A. Smith, C. D. Nordquist, T. N. Jackson, T. S. Mayer, Appl. Phys. Lett., 77, (2000), (b) A. Vijayaraghavan, S. Blatt, D. Weissenberger, M. Oron-Carl, F. Hennrich, D. Gerthsen, H. Hahn, and R. Krupke, Nano Letters 7, (2007). [2] K. Blekker, B. Munstermann, A. Matiss, Q.-T. Do, I. Regolin, W. Prost, F.-J. Tegude, IEEE Trans. Nanotechnology, vol. 9, no. 4, pp , July [3] T. Waho, S. Taniyama, R. Richter, O. Benner, K. Blekker, W. Prost, presented at 35th Workshop on Compound Semiconductor Devices and Integrated Circuits, Catania, Italy,

33 Epitaxial Growth and Materials X-Ray Diffraction of GaN Layers and Nanostructures Student: Supervisor: A. J. Stegemann I. Regolin Introduction The band gap of GaN (WG = 3.4 ev) can be widely modified using alloy nitride semiconductors such as AlxGa1-xN and InxGa1-xN. Therefore, the GaN material system is a very important material for light emitting devices and photo detectors in the whole visible wavelength range and beyond [1]. Unfortunately, AlxGa1-xN and especially InxGa1-xN exhibit a strong dependence of the lattice constant on the composition and it is very difficult to epitaxially grow nitride based heterostructures offering the full theoretically band gap range of 0.7 ev < WG < 6.1 ev. GaN based nanowires are widely accepted as a promising candidate to relax the lattice mismatch constraints of nitride based alloy semiconductors. Up to now nitride based nanowires are mainly grown by molecular beam epitaxy. In May 2010 a new Metal Organic Vapor Phase Epitaxy apparatus (MOVPE) for nitride nanowire growth was installed in our facility in order to study MOVPE for nanowire based light emitting devices. The crystal lattices structure was examined by high resolution X-ray diffraction (HRXRD). The aim of this work is to evaluate first grown GaN samples and to study the applicability of X-ray diffraction for GaN nanowires. Experimental Setup All samples were grown by MOVPE. Most layers and structures were produced in Duisburg, while the nanowires were provided by Axitron (Aachen). The nanowires were grown on silicon and sapphire (Al 2 O 3 ), while the layers had sapphire as substrate. X-ray diffractometry was performed on a computer-controlled Stoe STADI P double-crystal diffractometer [2]. Two GaAs wafers in a parallel (400) setting act as monochromator and as a collimator to extract the CuKα 1 radiation (λ = nm) and a scintillation counter was used as detector. The ω-scan changes the position of the sample and gives accurate information on the crystal quality while the coupled 2θ-ω scan is changing the angles of both detector and sample providing information about multiple layers, different materials and tensions [3]. Results Various GaN, Al x Ga 1-x N-, and In x Ga 1-x N-layers and hetrostructures were grown during system start-up. The tension within a single GaN-layer can be identified by examining the Bragg peak position of GaN in the rocking curve. This way also the lattice parameter c can be determined. The GaN Bragg peak was found at the theoretical position of about proving that all samples are nearly relaxed beyond a thickness of 1 µm. The full width half maximum (FWHM) of the peak is around 270 `` (in a ω-scan). A FHWM between 250 ``and 350 `` indicates a good GaN-crystal with little defects.

34 28 Annual Report Solid-State Electronics Department The samples with an Al x Ga 1-x N-layer were grown on top of a GaN-buffer layer. Figure 1a) shows three different rocking curves. The Bragg peak gives direct information on the incorporated Alconcentration. With increasing Al-concentration the AlGaN-peak appears at higher angels. It changes position between the two extremes GaN (34.57 ) and AlN (36.04 ). The samples show an almost linear relationship between offered TMAl and embedded Al in the layer. GaN AlxGa1-xN 5 10 Simulation Recording Intensity TMAl III 27 % 37,4 % 39,5 % Peak Positon 35,02 35,07 35,10 Intensity Arcsecond a) b) 31,2 32,3 33,4 34,5 35,7 36,8 Angle 2θ Fig. 1. Rocking curve of GaN heterostrucutures a) GaN/AlGaN samples with different Al-concentration b) InGaN-MQW rocking curve and simulation: In-content 27 % InGaN thickness 2.3 nm; GaN thickness 16.6 nm Samples with In x Ga 1-x N/GaN multiple quantum wells (MQW) for LED application were grown. The growth starts with a GaN-buffer layer followed by five periods of In x Ga 1-x N/GaN-layers to form a MQW. These five periods create a superlattice. Figure 1b) shows a corresponding rocking curve. The highest peak corresponds to the GaN buffer layer. The smaller peaks are satellite peaks and belong to the superlattice. The distances between the peaks depend on the period length. If the distance between all satellite peaks is equal, the superlattice is equally spaced. All samples have an equally spaced superlattice. The simulation-software is supposed to determine In-concentration and the thickness of each layer. While it is easy to determine the period length, ascertaining the thickness of each individual layer is difficult. The position of each satellite peak depends on Inconcentration and the thickness of each layer. The envelope provides information of the concentration and thickness, but it is difficult for the simulation software to take the envelope in account. The same challenge appears with LEDs, since they also use a InGaN-MQWs. Second task of this thesis was to examine GaN nanowires. This was done in two different steps. First different AuGa alloys were analyzed, which support the growth of GaN nanowires via VLSgrowth. The Au nanoparticles were placed on the substrate. Afterwards TMGa was exposed to the gold. Depending on the exposure time, Gallium supply and temperature different alloys are formed, which influence the growth of the nanowires. With HRXRD it is possible to detect those alloys and determine the lattice parameters. Temperatures higher 900 C produced atom-atom distances from

35 Epitaxial Growth and Materials nm and could form the alloys Au 7 Ga 2 or Au 0.79 Ga At 744 C distances of 4.31 and 3.51 nm were found and could be Au 7 Ga 2, AuGa 2 or Au 2 Ga. In the second step fully grown nanowires were studied. Several challenges exist in analyzing GaN nanowires via X-ray diffraction. First the density of nanowires on the provided samples is often low. Secondly between the wires grew crystals (visible in Figure 2a) with the same lattice parameter like the wires and thirdly the rocking curves look almost equal. Figure 2b) shows two rocking curves, one of a sample with nanowires and one without. There are only two differences between both curves. One shows an additional gold-peak. This gold is used to catalyze the growth of nanowires. The second difference is that the GaN-peak of the Nano-wires has a higher FWHMvalue. The ω-scan had for different nanowires samples FWHM-values of `` and `` for the 2θ-ω scan. It was only possible to examine GaN nanowires grown on sapphire, because those grown on Si did not show any GaN in their rocking curves. While other measurement methods prove that the wires are made from GaN. The crystal structure is not equally enough to be studied with HRXRD. Also GaN nanowires with an additional InGaN coat showed no difference in their rocking curve. So at the moment it is impossible to state any parameters based on the rocking Sapphire (0002) GaN (0006) Intensity Au (111) 100 nm 33,4 36,1 38,9 41,7 Angle 2θ a) b) curves. Fig. 2. a) Microcraft of GaN nanowires on sapphire side view; b) rocking curves of GaN nanowires (top) and a GaN-crystal (bottom) Conclusion It is possible to examine the tension and crystal quality in a GaN-layer. The Al-concentration in Al x Ga 1-x N-layer can be determined. It is difficult to give information about thickness and Inconcentration in In x Ga 1-x N-layers. GaN nanowires have at the moment too many unwanted crystals between the wires and too little density of nanowires to give useful information. GaN nanowires still need more research.

36 30 Annual Report Solid-State Electronics Department Acknowledgement This work is part of the NaSoL Project. Special thanks to AIXTRON for providing the GaN nanowire samples. References [1] Hadis Morkoc: Handbook of Nitride Semiconductors and Devices, Volume 1: Material Properties, Physics and Growth Wiley-VCH, Weinheim, 2008, ISBN [2] Qiuming Liu: Characterization of GaInP/GaAs and GaInP/InP heterostuructures by means of X-ray diffraction and photoluminescence Doktorarbeit, Gerhard-Mercator-Universität Duisburg (1995) Shaker Verlag, ISBN [3] M.A. Moram and M. E. Vickers: X-ray diffraction of III-nitrides Reports on Progress in Physics 72 (2009), Page

37 Annual Report Solid-State Electronics Department Device and Circuit Processing

38 32 Annual Report Solid-State Electronics Department High Performance Submicron RTD Design for mm- Wave Oscillator Applications Scientist Technical assistance A. Tchegho, B. Münstermann R. Geitmann Introduction Resonant tunnelling diodes have proven their potential for high frequency generation, due to their built-in negative differential conductance region (NDC) in I-V characteristic, which enables oscillation frequencies up to 900 GHz [1]. In addition to sub-thz oscillator-application, RTD are used in combination with HBT-technology for microwave voltage controlled oscillators with high power conversion efficiency and low phase noise [2]. To predict bandwidth and spectral purity as well as frequency limits of integrable devices a precise modelling of high current density RTD, especially when biased in the NDC region is needed. To increase the switching speed and the power conversion efficiency of the RTD based oscillators, it is necessary to increase the current density of the devices without decreasing the peak-to-valley current ratio (PVCR). However, this approach can lead to a drastic increase of the intrinsic capacitance of the RTD. In this work a sophisticated design is combined with the extraction of the small signal parameters in order to set up a scalable high current density with high PVCR (J P 495 ka/cm 2 ; PVCR > 6) and a small area RTD device model. RTD Design and Technology In contrast to the InP-based RTD with double AlAs-barriers presented in [3], the thickness of the lower doped contact layer sandwiched between the non-doped spacer and the grading layer was reduced from 10 nm (sample A) to 0 nm (sample B). Additionally a heavily Si-doped n-ingaas (N D = cm -3 ) contact layer was also added to reduce the ohmic contact resistance and also the sheet resistance of the contact layer. Fig. 1 SEM-picture of the fabricated low series resistance RTD-design

39 Device and Circuit Processing 33 Fig. 1 shows a SEM picture of the experimental RTD. The design was optimized to reduce the series resistance and improve the high frequency performance. In this experiment we achieved an increase of the current density by thinning the lower doped contact layers. By removing the low doped layer thickness an increase of available RF-power up to 1.3 mw/µm 2 density was achieved (fig. 2). Fig. 2 Measured J/V characteristics for devices under test with 10 nm (sample A) and 0 nm (sample B) low doped layer thickness Measurement Principle S-parameter measurements have been performed in a stabilized 2-Port configuration setup over the total bias range to extract the small signal parameters of the devices to compare the high frequency performance of the different designs. Fig. 3 Differential conductance of 1 µm² RTD of sample A extracted from S-parameter and calculated maximum oscillation frequency f max.

40 34 Annual Report Solid-State Electronics Department We assumed the equivalent circuit shown in [3] to extract the capacitance C d and the differential conductance g d, which is in good agreement with the first derivative of the measured J/V characteristic and ensures reliable extraction (fig. 3). The various RTD designs are compared by the condition, that the absolute peak current is 1mA (fig. 4). Using this normalization it is show that a significantly reduced capacitance is achieved for devices with the low doped layer removed, though the capacitance per unit area is increased. Fig. 4 Normalized extracted capacitance C d for devices with peek current I peak = 1mA: the capacitance per unit peak current density discreased Conclusion In this work we achieved an increase of the RTD current density by thinning the lower doped contact layers and the modelling of the device was also successful. It is found that the advantage of higher current density and therefor higher available power density outweighs increased device capacitance due to the removal of the lightly doped contact layer according to high frequency performance. The optimum RTD design has 50% lower capacitance at similar DC-operating point, 65% higher available RF-power and an increased cut off frequency up to 420 GHz. References [1] S. Suziki et al. Fundamental Oscillation at 900 GHz with low bias voltages in RTDs with spike-doped structures Appl. Phys. Epress 2, (2009). [2] Y. Jeong, S. Choi, and K. Yang, A Sub-100uW Ku-Band RTD VCO for Extremely Low Power Application, IEEE Microw. And Wirel. Comp., vol. 19, no. 09, pp , [3] A. Tchegho et al. "Scalable high-current density RTDs with low series resistance," Intern. Conf. on Indium Phosphide and Related Materials, May 31-June 4, 2010.

41 Epitaxial Growth and Materials Nanowire Transistors in Electronic Circuits Student Supervisor O. Benner K. Blekker Introduction Due to their outstanding electronic properties nanowire (NW) transistors are considered as a possible successor to today's microelectronic transistors. In particular, InAs nanowires are suitable for nanowire transistors, because of the high charge carrier mobility and low power capabilities. In this report InAs nanowires are used to produce electronic circuits with nanowire transistors. In order to fabricate nanowire transistors within electronic circuits the nanowires are aligned at predetermined positions using field-assisted self assembly (FASA) [1]. With the help of optical and electron beam lithography NW transistors are fabricated and linked to circuits. Thereby two types of sample and hold circuits, one with a single transistor and the other with a second transistor as buffer, and an inverter circuit are realised. The fabricated circuits are electrically characterized and simulated with Advanced Design System (ADS). Experimental and results For fabrication of the NW transistors the field-assisted self assembly process is used. As a first step an electrode structure of 10 nm titanium metallization is patterned by optical lithography. For NW alignment a sinusoidal voltage with a frequency of 10 khz and 10 V amplitude is applied to the FASA electrodes, and the NWs are deposited from a solution. After successful NW deposition and alignment the titanium electrodes and excessive InAs NW material are removed by wet chemical etching. Processing steps for the NW FET and hold-capacitor complete the sample and hold circuit. The hold-capacitor is realized with two values, 35 ff and 130 ff. In Figure 1 a) a SEM micrograph of the sample and hold circuit sh1 is shown. The contact pads for input, output and clock signals are indicated. In fig. 1b) a measurement result of the sample a) b) Fig. 1 a) SEM micrograph sh1 and (b) measurement diagram (C = 35 ff) of the sample and hold circuit

42 36 Annual Report Solid-State Electronics Department and hold circuit is shown. G-S-G probes are used to apply an ac voltage as input signal. For the clock signal a square wave voltage with a frequency f CLK = 5xf IN is used. The output signal is measured with the help of an active probe. This needle contains, in addition to the RC network, an active amplifier, thus the measured signal is decoupled from the DUT. The diagram proofs the functionality of the sample and hold circuit. When the clock signal is high, the nanowire transistor is open and the output signal follows the input signal. When the clock signal is low, the NW transistor is closed and the hold function is clearly demonstrated. It is striking that the output voltage is not constant in the hold phase, because of the relatively high off-current (1 µa) of the NWFET. Furthermore an offset of the hold phase voltage at the transition of hold and sample phase occurs. This can be explained by reloading of the gate-source-capacitance. In addition, an inverter, consisting of a nanowire resistance and a nanowire transistor, has been implemented. In figure 2 a) a SEM micrograph and in figure 2 b) the measurement result of the inverter circuit are shown. a) b) Fig. 2 a) SEM micrograph inverter and (b) measurement diagram (C = 130 ff) of the inverter circuit The output signal of the inverter circuit was measured with G-S-G probes. In figure 2 b) the inverted input signal and the output signal is given. The diagram proofs the functionality of the inverter circuit. The comparison of the input and output curve exhibit an absorption of 64 decibel, which can be caused by the measurement setup, parasitic capacities or the poor adaptation to the 50 Ω input of the oscilloscope. The simulations help to improve the understanding of the measurement results. Useful modifications to the circuit, as well as influences of the measurement setup should be demonstrated by the simulation results. Therefore, the electronic circuits were simulated using the simulation software Advanced Design System (ADS) from Agilent. In a first step a MOSFET model was adapted using NWFET measurement results. Figure 3 shows the adapted transvercurve of the MOSFET model as well as the simulation results of the inverter circuit. The simulation results show good agreement with the measured curves. The measured absorption of the inverter circuit is higher than the absorption in the simulation (fig. 2b/3b). This difference

43 Epitaxial Growth and Materials 37 3E-4 a) 1E b) DC.Id.i[indep(m1),::] M4120b3_sh1_r15..Id 1E-5 1E-6 TRAN.Vin, V TRAN.Vout3, mv c) TRAN.Vin, V 1E M4120b3_sh1_r15..Vgs Vgs TRAN.Vout3, V time, nsec -20 Fig time, nsec -1.0 a) adapted transvercurve and simulation results of b) the inverter circuit and c) the inverter circuit measured with an oscilloscope with 1 MΩ input resistance can be caused by the measurement setup and parasitic capacities, which are not included in the simulation. In fig. 3 c) an oscilloscope with 1 MΩ input resistance was used to simulate the inverter circuit. The output signal has a much larger amplitude than previously, the absorption is only 8 decibels. Therefore, one can assume that a large part of the absorption is due to the poor 50 Ω adaptation. Conclusion In summary, electronic circuits were fabricated, whose core element is a nanowire field-effect transistor. Therefore InAs nanowires were deposited using fieldassisted self-assembly. With the help of these wires nanowire devices were prepared and connected to electronic circuits. Though a sample and hold circuit, as well as an inverter has been realized. References: [1] A. Vijayaraghavan, S. Blatt, D. Weissenberger, M. Oron-Carl, F. Hennrich,D. Gerthsen, H. Hahn, and R. Krupke Ultra-large-scale directed assembly of single-walled carbon nanotube devices, Nano Letters 7, (2007)

44 38 Annual Report Solid-State Electronics Department Development of Dry Etching Processes for the Fabrication of Germanium PIN Diodes Student Scientist B. Betting Prof. F. J. Tegude The experimental work was performed at the Institute of Semiconductor Technology at the University of Stuttgart. Introduction Dry etching is one of the key technologies for the processing of semiconductor devices. With dry etching, it is possible to realize very small structures without under etching. For a new RIE-etcher at the Institute of Semiconductor Technology at the University of Stuttgart new etching processes needed to be developed. In this work, the SiO2 and Ge dry etching processes are developed which are used for the fabrication of germanium PIN diodes. The layout of such a diode is shown in figure 1 [1]. The requirements of the etching processes, which are all important issues for device fabrication, are: Homogeneity of the etch rate of 5 % over the sample surface, etching anisotropy, smooth and residue-free surfaces, and selective etching for the photo resist. Al 250 nm SiO 2 25 nm n + -Si/Sb 200 nm n + -Ge/Sb 500 nm i-ge 300 nm p + -Ge/B 50 nm i-ge 50 nm Si-Buffer Si-Substrate Fig. 1 Layout of the Ge PIN diode Reactive Ion Etching The ICP standard technology for etching Ge, use a 25 nm Si-cap, which is placed on top of the Ge layer. With this Si-cap the etching results in smooth surfaces. To determine if this Si-cap is needed for the new RIE etcher, experiments were made with and without a Si-cap. Before the etching processes are tested on the device, the required experiments to develop the etching processes were realized with test samples. These samples consist of SiO 2 or Ge layers on Si

45 Epitaxial Growth and Materials 39 in order to analyze the etching characteristics of each material. The experiments are performed with a photo resist mask. The best results were achieved with the resist AZ 6612 from the company microchemicals. The etch profiles of different etching processes with various process parameters were investigated. The determined process parameters for the best results are shown in table 1. In figure 2 the results of the corresponding Ge etching processes for structures are shown with and without Si-cap. From this follows that in both cases a smooth and residue-free surface is reached. etching processes process parameters SiO 2 Ge without Si-cap Ge with Si-cap gas / gas flow v [sccm]: CHF 3 / 100 CF 4 / 30; Ar / 30 CF 4 / 30; Ar / 30 power p HF [W]: presure p [mtorr]: smoothing of the surface - 20 s in H 2 O 2 - opening the Si-cap - - CF 4 / 50 sccm P HF = 20 W p = 20 mtorr Tab. 1 The determined process parameters Resist Ge Ge Si substrate Si substrate a) b) Fig. 2 SEM micrograph of the developed Ge etching process a) without Si-Cap and b) with Si-Cap The etch profile of the developed SiO 2 process is shown in figure 3. Also in this case the etching results in a smooth and residue-free surface. The other requirements, which were mentioned earlier,

46 40 Annual Report Solid-State Electronics Department are also achieved (see table 2). Just the homogeneity for the Ge process with Si-cap is slightly lower than required, due to the removal of the Si layer in a first etching step. Resist SiO 2 Si substrate Fig. 3 SEM micrograph of the developed SiO 2 etching process SiO 2 process: Ge process with Sicap: Ge process without Si-cap: etching rate [nm/min]: selectivity: homogeneity [%]: etch angle [ ]: roughness [nm]: Tab. 2 The determined etching parameters Electrical characterization After the etching processes were developed, the next step was to use the processes for the fabrication of germanium PIN diodes. Diodes were fabricated with and without a Si-cap layer. The SiO 2 etching process to open the contact window was used in both cases. To classify the functionality of the developed processes, reference germanium PIN diodes were fabricated with the germanium standard technology. Figure 3 shows the I-V characteristics of the reference probe, for a diode with Si-cap and for a diode without Si-cap. It can be seen that all diodes possess approximately the same characteristic. Therefore it can be said that the developed etching processes can be used for the fabrication of germanium PIN diodes. Furthermore, one can see that the Si-cap layer is not longer required.

47 Epitaxial Growth and Materials witout Si-cap with Si-cap Reference I [A] Fig U [V] I-V characteristic of different fabricated diodes Conclusion During this work dry etching processes for the fabrication of germanium pin diodes were developed. For this purpose etching experiments with test structures were made. Afterwards the developed etching processes were used to fabricate germanium PIN diodes. The electrical characterization of the diodes showed that the developed etching processes are suited for the fabrication of germanium PIN diodes. References [1] Mathias Kaschel, Elektrische und Optische Charakterisierung von p-i-n Photodioden aus Germanium diploma thesis, University Stuttgart, February 2007

48 42 Annual Report Solid-State Electronics Department Spatially Resolved Opto-Electrical Perfomance of Axial GaAs Nanowire pn-diodes Scientist: A. Lysov, C. Gutsche, I. Regolin Introduction III/V semiconductor nanowires are interesting candidates for the bottom-up fabrication of nanophotonic [1,2] and photo-voltaic [3] devices. Nanowire array LED was reported to possess higher light extraction efficiency than conventional broad area LED due to its large sidewall surface area. Axial nanowire based devices demonstrate good light detection properties. Although few successful demonstrations of radial nanowire solar cells and photodiodes have been reported for GaAs material system, no reports about electro-optical performance of axial GaAs nanowire pn-diodes are known so far. In this work we investigate the opto-electrical performance of single axial GaAs nanowire pn-diodes. Experimantal setup Axial pn-gaas nanowires were grown on (111)B GaAs substrates by metal organic vapor-phase epitaxy (MOVPE) in the VLS growth regimes as described in in annual report of Ingo Regolin Axial modulation of doping was achieved by subsequent switching of doping precursors without any growth interruptions. P-doping with mean hole concentration of cm 3 was realized with zinc. N-doping with mean electron concentration of cm 3 was realized with tin. Results To investigate electroluminescent properties of single nanowire pn-diodes, the contacted nanowire samples (inset on the fig. 1a) were glued to the chip-carrier and wire bonded. The single nanowire pn-junction with a diameter of 200 nm and a diode like IV characteristic (fig. 1a) was excited by a constant current in forward direction while emissions spectra were measured. Figure 1b shows electroluminescent spectra from a single pn-junctioned nanowire taken at 10 K under different excitation currents. At low currents the emission peak has a maximum at 1.32 ev (fig. 1b). For higher injection current the peak shifts to 1.4 ev and its intensity increases until an injection current of 1.85 µa. The emission is believed to come from the tunneling-assisted transitions between spatially separated degenerate donator and acceptor states, so that emission lines with the energy much lower than the band gap may appear. Donator and acceptor states are present in the region of pn-junction due to the memory effect of the Au- seed. During nanowire growth some zinc remains in gold after switching of the doping precursors from DEZn to TESn, yielding a region where both doping species are incorporated. An origin of such lines is illustrated in a Figure 1e. This assumption of radiative tunneling is supported by the shift of the emission peak to higher energies with an increasing excitation current. This shift is expected for tunneling assisted transitions and is explained by shift of the quasi-fermi levels with respect to each other. The slope of the band structure at the junction

49 Device and Circuit Processing 43 flattens at higher bias voltages causing a reduction of tunneling probability and a decrease of the tunneling emission. For this reason tunneling assisted emission peak diminishes for high injection levels and becomes dominated at 4.5 µa by band-edge emission, appearing at 1.51 ev for 10 K. a) b) c) d) e) Fig. 1 (a) I(V) characteristics of the single GaAs nanowire pn-diode in semi-logarithmic (left axis) and linear (right axis) plot at room temperature. The inset shows a SEM micrograph of the contacted nanowire-diode. (b),(c) Electroluminescence spectra taken at the single pn-junctioned GaAs nanowire for different excitation levels at 10 K and 300 K respectively. Band gap of GaAs at corresponding temperatures is indicated in the Figures. (e) Optical microscope image collected by CCD camera of a nanowire pndiode at 300 K under forward bias of 3 V. Electrical contacts to the nanowire are plotted with dashed lines. (e) Model of a band structure for a diode with a compensated region biased in forward direction. Tunneling assisted radiative transition in compensated region is indicated by an arrow.

50 44 Annual Report Solid-State Electronics Department Scattering of free carriers by phonons increases at higher temperatures. This lowers the tunneling probability and makes it more difficult to distinguish between two emission mechanisms. At room temperature broad band-band emission dominates the whole spectrum even for low injection currents (fig. 1c). The population of states above the quasi-fermi level increases with temperature and explains broadening of the emission peak at the high energy side while the low-energy tail stays saturated. For the spatially resolved investigation of the electroluminescence optical microscope image of a forward biased nanowire pn-diode was made at 300 K (fig. 1d). The image was taken by CCD camera in the imaging mode collecting all light in a range of nm. To highlight the position of the contacted nanowire sample was illuminated by scattered light from the side. In the Figure 1d strong electroluminescence in the middle of the contacted nanowire-diode at the expected position of the pn-junction is observed. This proves, that light emission originates from electroluminescence at the pn-junction and not from the recombination at contacts. Fig. 2 (a) Schematic of a measurement setup for photocurrent microscopy. The lower inset shows a SEM micrograph of the investigated nanowire-diode. (b) I(V) characteristics of the GaAs nanowire pn-diode illuminated by focused laser spot at different positions. Upper inset shows photocurrent as a function of a laser spot position. The corresponding positions are denoted by numbers on the SEM image in Figure 2a. Spatially resolved photocurrent spectroscopy was used to investigate mechanism of carrier photogeneration in nanowire pn-diodes. I(V) characteristics of nanowire pn-diodes were measured, while nanowires were locally illuminated by focused CW laser 532 nm at different positions (fig. 2b). The laser light was focused by a 50x objective lens yielding a spot of diameter ~1.5 µm. Short circuit current and photocurrent are maximal when diode is illuminated at the position of the pn-junction (position 5 in the fig. 2a). Photocurrent was observed neither in the vicinity of contacts nor in the p- and n-diode parts. To determine solar conversion efficiency of a fabricated photodiode current voltage measurement under homogeneous AM 1.5 G illumination was done (fig. 3a). A short circuit current of 88 pa and an open circuit voltage of 0.56 V were obtained yielding a fill factor of 69 %. The power conversion efficiency of the nanowire photovoltaic device illumination was estimated:

51 Device and Circuit Processing 45 V I P OC SC to 9 %. in FF Fig. 3 (a) Dark and AM 1.5 G illuminated I-V characteristics of nanowire pn-diode. b) I-V characteristics of the nanowire pn-diode measured under monochromatic homogeneous laser illumination 532 nm with various illumination powers. Power dependent photocurrent measurements made under monochromatic homogeneous laser illumination 532 nm demonstrate linear scaling of photocurrent with illumination intensity (fig. 3b). This is in conformity with the relationship ISC A q L e Lh G, where A is an area of the pn-junction and G is a generation rate. Conclusion Spatially resolved opto-electrical performance of axial GaAs nanowire pn-diodes was investigated. Nanowire diodes were shown to be strongly electroluminescent at both low and room temperature. Recombination mechanisms alter with the temperature and injection level. Tunnelling assisted donator-acceptor recombination takes place at low temperature and low excitation level, band-band transitions were observed at high temperature and high excitation levels. Nanowire pn-diodes demonstrated excellent light detection properties. Optical generation of carriers at the pn-junction was shown to dominate the photoresponse. Power dependent photocurrent measurements demonstrate linear scaling of photocurrent with illumination intensity. The fill factor of 69 % and open circuit voltage of 0.56 V at AM 1.5 G conditions are obtained. References: [1] M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber, "Growth of nanowire superlattice structures for nanoscale photonics and electronics," Nature, vol. 415, pp , [2] E. D. Minot, F. Kelkensberg, M. van Kouwen, J. A. van Dam, L. P. Kouwenhoven, V. Zwiller, M. Borgström, O. Wunnicke, M. A. Verheijen, and E. P. A. M. Bakkers, "Single Quantum Dot Nanowire LEDs," Nano Lett., vol. 7, no. 2, pp , [3] C. Colombo, M. Heiß, M. Grätzel, and A. Fontcuberta i Morral, "Gallium arsenide p-i-n radial structures for photovoltaic applications," Appl. Phys. Lett., vol. 94, no. 17, p , 2009.

52 46 Annual Report Solid-State Electronics Department HBT-Technology and Design Improvements in Yield and On Wafer Variation Scientist B. Münstermann, G. Keller, A. Tchegho Introduction The enhancement of high frequency performance in analog and digital circuits for microwave and millimeter wave applications with new devices, like the resonant tunneling diode, have been investigated intensively. The cut off frequencies of the devices go up to the sub THz region. To proove the benefits of the new devices for applications, monolithic integration with a fast and reliable transistor technology is needed to reliase impedance matching and amplification to avoid dominating parasitics caused by hybrid technology solutions. Heterojunction bipolar transistor technology is a possible candidate for combination in microwave circuits, because of high frequency cut off frequencies and good low frequency noise generation. Technology The epitaxial layers have been grown in the metal organic vapor phase epitaxy (MOVPE) machine. The single heterojunction of the bipolar transistor (SHBT) consists of the lightly doped InP emitter and the InGaAs base layer. The collector is grown on a highly doped InGaAs contact layer to achieve low contact resistance and enable high current densities in the device. The device technology is based on the well known triple-mesa design. Three wet-chemical etching steps are used to define the emitter, base-collector, and the sub-collector mesa, whereat the etch undercut is used to reduce the parasitics of the devices (Fig. 1). The definition of the emitter is performed by optical lithography, which restricts the available resolution to a minimum edge length of 1 µm. A self-aligned metallization process is used to minimize the base resistance. In this case the etch profile of the emitter has to be controlled carefully to ensure base emitter isolation during the metalisation procedure (Fig. 1b). During the etch process of the second mesa the emitter has to be protected by a photoresist, because in this case an aggressive etching solution generates a large lateral etch rate to reduce parasitic non-intrinsic parts of the base collector junction. Fig. 1 Device crosssection: a) before emitter mesa etching b) before base mesa etching c) after passivation and etching of spin-on-glass

53 Device and Circuit Processing 47 After processing the etch steps, the intrinsic device is passivated with a polymide structure to avoid layer degradation and contact seperation. Oxide plasma etching is then used, just until the emitter metal electrode is accessible (fig. 1c). Layout and process monitoring A new maskset has been created to test and monitor the epitaxial and the technolgical part of the HBT-process in terms of yield, on-wafer variations and high frequency performance. The maskset includes positive and negative patterns for the critical metalization steps (emitter,base), so a wide variety of photoresists can be tested. We used four different HBT designs which are scaled by the emitter dimensions from 1x5 µm 2 to 2x15 µm 2. The designs can be devided into standard and advanced categories, which mainly differ in adjustment error tolerance. The advanced version is designed to have a significantly improved high-frequency performance due to the reduced base-collector capacitances. On the other hand the standard version is intended to be robust and steady against process fluctuations. Especially in terms of yield investigation effective process monitoring is crucial. Therefor dummy structures have been included (fig 2) for subsequent investigations. Fig. 2 SEM-pictures of a process monitoring structure Measurement Results To analyse the transistors a completely automated DC measurement is performed. By this means a large number of transistors can be tested and evaluated. The yield of the most promissing transistor design was 93 % and 96 % for standard and advanced design respectivly. The typical dc current gain of these devices was 23 with an acceptable standard deviation of 2.7, which is mainly contributed to inhomogeneity from the center to the border of the wafer. The typical commonemitter collector I-V characteristic for a device with a 1x10 µm 2 emitter area is shown (fig. 3a). They show a low turn on voltage of around 0.2 V. Improvements in termal contacting of the emitter with a wide metallization are also recognizable comparing different designs. The gummel plot for a device is pictured in figure 3b. It is measured at a collector-base voltage of 0 V. Here ideality factors of 1.17 for the collector current and 1.22 for the base current shows good performance of the devices.

54 48 Annual Report Solid-State Electronics Department IC [ma] IB = µa Fig VCE [V] a) Common-emitter collector I-V characteristics of the preffered device type b) typical Gummel plot On wafer measurements of the rf-behavior are performed with an HP8510C network analyser for frequencies up to 50 GHz. Fig. 3a shows the s-parameters of the device operating in the active region. The base current was varied between 50 µa and 300 µa for a device with an emitter area of 1x5 µm 2. The influence of the base current is pictured in fig. 4b. It shows the current gain f T and the unilateral power gain f Max for base currents up to 350 µa. A maximum f T of 112 GHz and f Max of 143 GHz can be observed at kirk current density. Fig. 4 a) S-Parameter for active operation Points b) f T and f Max for different Base Currents Conclusion An improved HBT technology was combined with new transistor layouts to significantly improve the yield of the devices. The cut off frequency and the maximum oscillation frequency of the devices have been extracted from s-parameter measurements and emphasize the applicability in millimeterwave applications.

55 Device and Circuit Processing Investigation and Processing of Ohmic Contacts on Highly Doped n-ingaas Student Supervisor P. Wang A. Tchegho Introduction Ohmic contacts are very important for improving the functionality and the reliability of semiconductor devices. InP-based InGaAs/AlAs double barrier resonant tunneling diode needs low ohmic contact resistance to keep the voltage drop low and to achieve high frequency performance, expecialy for devices with high current density [1]. The metal combination Ti/Pt/Au is currently used for ohmic contact realization on n+-ingaas in the Solid State Electronic departement. Palladium featured as an altarnative to replace Pt. Both are goup VIII transition metals, and therefore schould not differ significantly in chemical and physical properties (similar resistivity and work function Pd: 9.93 µω cm; 4.99 ev und Pt: 9.85 µω cm; 5.32 ev respectively). In this experiment, palladium will be investigated to replace Pt as the contact metal for highly doped n-ingaas layer. The electrical characterization of fabricated ohmic contact is carried out by using the well known transmission line measurement (TLM) and the newly developed in III-V semiconductor cross-bridge Kelvin resistor (CBKR). Technology The experimented InGaAs-samples, which were lattice mached grown with doping concentration of cm -3 by molecular beam epitaxy on a semi-insulating InP-substrate, were structured by optical lithography, wet etching and metalized by evaporation deposition and lift-off techniques. The desired contact metals were deposited via electron beam evaporation or thermal evaporation for Ti; Pt or for Pd; Au respectively, however the thermal evaporation of Pd was improved after a vacuum rupture in another evaporation system. To remove the surface native oxide prior to metallization, the samples were cleaned in a solution with 10% ammonium hydroxide (NH 4 OH) after photoresist developing. After the metalization and the lift-off process, the wet chemical etching was carried out with the mixture of phosphoric acid with hydrogen peroxide and water (1:1:25/ H 3 PO 4 :H 2 O 2 :H 2 O), which is highly selective for InGaAs with aspect to InP-substrate [3]. To fabricate the CBKR with only two lithography steps, the metals connection between upper contact and contact pad of CBKR were slim designed in order to realize an air-bridges with the wet-underetching (fig. 1-b). The contacts on highly doped n + -InGaAs-samples were made with 10 nm Titanium, 10 nm Palladium, 400 nm Gold metal system and 20 nm Titanium, 20 nm Palladium, /400 nm Gold metal system. Measurement principle of cross-bridge Kelvin resistor The measurement principle of CBKR structure consists of forcing the current flow (I) from metal side to semiconductor side and measuring with the connected voltmeter the voltage drop (V 4 -V 2 ) at

56 50 Annual Report Solid-State Electronics Department the contact interface (fig. 1-a). The measured contact resistance R c can then be calculated as: R c = (V 4 -V 2 )/I (a) (b) Fig. 1 (a) functional diagram of CBKR (b) SEM micrograph of realized cross bridge Kelvin resistor: For a better limitation of the active contact area the undercuts under thin metals produce metal air bridges. The specific contact resistance can be calculated as product of contact area A and contact resistance, ρ c = R c A. Experimental Results Fig. 2 Mapping of Specific contact resistance measured from TLM (left) and CBKR (right) structure respectively.

57 Device and Circuit Processing 51 For TLM structures, except the cells on the edge, the variations among the specific contact resistances are in a small range. For CBKR, though specific contact resistances are smaller and their value variations are bigger. The CBKR structures are sensitive to the local surface states due to random doping fluctuations and other impurities, because of their small contact size. The specific contact resistances for CBKR and TLM structures are proportional, but the CBKR results are lower. CBKR can be used to quantify the local variations and can also be easily integrated. 1E-6 TLM - Ti/ Pd/ Au Specific contact resistance[ω cm 2 ] 1E-7 1E-8 C C C t [s] Fig. 3 Specific contact resistances of TLM structures with Ti/Pd/Au contacts vs. the annealing time Ti/Pd/Au is non-alloyed ohmic contact and shows a good ohmic characteristic on highly doped n + - InGaAs before and after annealing. The optimum annealing parameter for the contacts is found at T = 300 C and t = 20 s for 10 nm/10 nm/400 nm Ti/Pd/Au resulting in a specific contact resistance of 9.12x10-8 Ω cm 2 for TLM structure. The reference sample with 20 nm Ti/20 nm Pt/400 nm Au contact shows a specific contact resistance of 2.21x10-7 Ω cm 2 after his optimum annealing process (T= s). The optimized ohmic contact with Palladium has lower specific contact resistance than the reference sample (Ti/Pt/Au). In addition, the evaporation process of Palladium is flexible. Conclusion In this work Palladium has been investigated for contacts to n-doped InGaAs in InP-based devices to replace Platinum and has the best ohmic contact property. A specific contact resistance of 9.12x10-8 Ω cm 2 was obtained with Ti/Pd/Au. Future works will focus on the understanding of the difference between the results obtained by both measurement methodes (TLM and CBKR).

58 52 Annual Report Solid-State Electronics Department References [1] Tchegho, A. et al., "Scalable high-current density RTDs with low series resistance," Indium Phosphide & Related Materials (IPRM), 2010 International Conference, vol., no., pp.1-4, May June [2] Chor, E. F.; Chong, W. K.; Heng, C. H.;, "Alternative (Pd,Ti,Au) contacts to (Pt,Ti,Au) contacts for In0.53Ga0.47As," Journal of Applied Physics, vol.84, no.5, pp , Sep 1998 [3] Stavitski, N.; Klootwijk, J.H.; van Zeijl, H.W.; Kovalgin, A.Y.; Wolters, R.A.M.;, "A study of crossbridge kelvin resistor structures for reliable measurement of low contact resistances," Microelectronic Test Structures, ICMTS IEEE International Conference, vol., no., pp , March 2008

59 Annual Report Solid-State Electronics Department Device and Circuit Simulation, Measurement and Modeling

60 54 Annual Report Solid-State Electronics Department Upgrade of the DC Measurement System to Improve the Measuring Accuracy Student: Scientist: Aaron Troost Benjamin Münstermann, Ingo Nannen Introduction The accurate characterization and simulation of semiconductor devices is an important issue in their development. Therefore a precise measurement of the DC-characteristics is necessary. To increase the measuring accuracy the on wafer measuring station at the HLT was expanded. Due to these changes the measurement software needed to be adapted to the measuring station. Measurement Setup The measuring station consists of an analyzer and a probe station. Both are controlled via GPIB (General Purpose Interface Bus) from an personal computer by a measurement software programmed with LabVIEW. The DUT (Device Under Test) is contacted with the analyser by coaxial probes attached to micro positioners. Hardware Changes A new parameter analyzer KI 4200 from Keithley was installed. One advantage of the new analyzer is that it supports 4-wire-measurements. By this measurement method the influence of the contact resistance between probes and DUT can be reduced and nearly eliminated. To realize 4-wiremeasure ments, new probes became necessary because additional sense connectors are required. There are two different types of probes in use: True Kelvin probes with two tips and probes with one tip, where force and sense wires are connected near this tip. 4-wire-measurements also allow Transmission Line Measurement (TLM) with the analyzer. Before the expansion an external Source Measurement Unit (SMU) was required. Another advantage is the better measuring resolution of 10 aa instead of 50 fa before. To benefit from this advantage, the influence of leaking is reduced by guarding. Therefore triaxial cables are used from the analyser to the patch panel, which is now included in the Faraday cage. The last change is the use of low noise cables from this panel to the probes. Software Changes The measuring program (Fig. 1) is an adaptation of the previous software to the new analyser with several improvements. More flexible configuration options compared to the previous program are the most important changes. Especially the possibility to reconfigure the stepper settings after the first configuration saves a lot of time. Other important features like connecting the Y axis for Gummel plots, TLM by using the analyzer and a new data format to store more than three parameters were implemented.

61 Annual Report Solid-State Electronics Department 55 Fig. 1: User interface of the measuring program Verification of the increased measuring accuracy The measuring accuracy is improved in two ways by the expansion of the measuring station. One aspect is the reduction of the measuring inaccuracy caused by the contact resistance. The difference between 4 and 2-wire-measurements is shown by a RTD IV-characteristic in Fig. 2. By the Expansion the influence of the contact resistance was reduced from 2.3 Ω to 0.3 Ω an even 10 mω for True Kelvin probes Fig. 2: 4- and 2-Wire-Measurement of the IV-Characteristic of an RTD with 4 µm² emitter area

62 56 Annual Report Solid-State Electronics Department The second aspect is the higher measuring resolution. Measurements of the substrate current of an InP substrate have shown that the resolution of the new measuring station is in the femtoampere range. With the previous setup only 100 pa could be attained. Summary In summary the measuring accuracy has significantly been increased e.g. by the use of an new analyser and 4-wire-measurement. Also the measuring software was improved to provide better usability and functionality. References: [1] LabVIEW Funktionen- und VI-Referenzhandbuch, National Instruments, [2] LabVIEW Benutzerhandbuch, National Instruments, [3] Model 4200-SCS Semiconductor Characterization System Reference Manual, Keithley, [4] Low Level Measurements Handbook, 6th Edition, Keithley, [5] F.-J. Tegude, Elektronische Bauelemente, Skript zur Vorlesung, [6] F.-J. Tegude, Technische Elektronik 1,2, Praktikumsunterlagen, [7] F.-J. Tegude, Halbleitertechnologie 2, Praktikumsunterlagen, [8] [9] Yiyao Fu, Modellbildung von Resonanztunneldioden, Studienarbeit (thesis), University Duisburg- Essen, 2009.

63 Device and Circuit Simulation, Measurement and Modelling Automation of a Micro Photoluminnescence-Measurement Setup for Spatially Resolved Investigations Scientist/Student Technical Assistant: X. Tang A.Lysov Introduction The photoluminescence Method is often used to assess the quality of the material s coating. Prior to the study of materials, a suitable photoluminescence measuring station (PL-measuring station) must be set up. The pl-measuring station should be capable of recording the spectrums and scanning the nanowires. The general principle of our pl-measuring station is shown in Fig. 1. Fig. 1 principle of the pl-measuring station[1] The control of this measurement process was previously manually conducted. The pl-measurement was conducted with the software PL-Messlabor, what was before my bachelor's work already through the development environment LabVIEW developed. The manual start up of each measuring point is affected with the software PI MicroMove from the company physics instruments. It s impossible with this Software the scanning and the measuring of the sample to automate, because each measuring point separately be started-up and afterwards a PL measurement had to be started. No rewriting privilege will be supplied for the Windows application PI MicroMove, therefore the automatic communication between the two programs are not feasible. An automatic measurement program will be developed in my bachelor s Work to replace the laborious manual control. The program will be called as Auto Meas. This program is developed in two parts: automatic movement and automatic measurement. Through the program of automatic movement, it ensures that the laser spot is moved from one measuring point of the sample to the next. Then, the PL measurement can be automatic started by using the program of automatic

64 58 Annual Report Solid-State Electronics Department measurement. For the development of Atuo Meas, it is to resort to DLL and LabVIEW Sub-VIs from the company PI. This process can be designed like the following flow chart. Fig. 2 main flow chart of the programm At the end of the study, the functionality of the measurement program and the resolution of the test setup will be tested in a sample with periodic metal strips, as well as a nanowire sample. Acknowledgement Thanks to HLT for the structure of the PL-measuering station und the test of the software. References: [1] Dr. Werner Porst, "Technologie der III/IV-Halbleiter, Springer Verlag 1997; ISBN

65 Device and Circuit Simulation, Measurement and Modelling Opto-Electrical Characterization of Nanowire pn-junctions Student Supervisor In collaboration with Audrey Nekam Simo A. Lysov, C. Gutsche M. Offer, Physics Department, University Duisburg-Essen Introduction Semiconductor nanowires have great potential to improve the ratio between photovoltaic efficiency and total cost. Particular attention has been given to core-shell structure, which offer higher carrier collection efficiency. The main focus of this work was on the electrical and optical properties of nanowire pn junctions. The devices studied consist of radially doped GaAs nanowires as well as axially (n-inp core/p-ingaas shell) nanowires. Experimental Setup Axially and radially doped GaAs nanowires were grown on (111)B GaAs substrates by metal organic vapor-phase epitaxy (MOVPE) in the VLS growth regimes. The nanowire structures were transferred on a substrate. The contacting process was realized with electron beam lithography. Pt/Ti/Pt/Au was used to form an ohmic contact with the radially doped p-type. To contact the n- type Ge/Ni/Ge/Au and Pd/Ge/Au were evaporated. Ti/Pt/Au was used to contact p-ingaas shell. For the core shell structure the n-type InP-core of the nanowire was contacted by first etching a section of the p-type InGaAs. The etching was performed with a phosphoric solution, whose etching rate had been calibrated before. Ohmic behaviour The ohmic characteristics of contacts to n-gaas nanowires were investigated. The Pd/Ge/Aucontact annealed at 280 C for 30 s exhibits much better ohmic behaviour than Ge/Ni/Ge/Au (fig. 1). It was found that both p- and n-doped GaAs nanowires contacts have shown good ohmic characteristic independent of the direction of growth (from n-to-p or from p-to-n). For comparison some n-inp nanowires were grown using TESn as the dopant source, too. However, preliminary I-V measurements on axial n-inp core/p-ingaas shell nanowires structures have revealed low conductivity of n-inp nanowire core, grown at different IV/III ratios of and The problem n-doping in InP nanowires could not be solved within this work and needs further investigation. The current through the p-ingaas shell was up to 6 µa at 1 V and suggesting that the doping concentration in InGaAs shell was high enough.

66 60 Annual Report Solid-State Electronics Department 4 2 n-gaas nanowire (tin doped) 280 C, 30 s current [µa] C, 30 s Fig voltage V [V] I-V characteristics from the n- doped GaAs nanowires contacted with Ge/Ni/Ge/Au and annealed 30 s at 320 C (a) and Pd/Ge/Au annealed 30 s at 280 C (b). The current for the nanowire with Ge contacts was about 2 na@1 V Temperature dependent optical properties To study optical properties of pn- and np- doped nanowires, excitation power dependence of these nanowires were measured at low and high temperatures. Figure 2b and figure 2c illustrate the electroluminescence spectra of the single pn-doped GaAs nanowire taken at different temperature under different excitation power. It has been observed that the transitions at low and high excitations differ. The low energy emission (Figure 2b) was described as photon assisted tunnelling [1]. (a) n 3 µm p (b) (c) Fig. 2 Electroluminescence spectra of the single pn-doped GaAs nanowire taken at different temperature (b) 80 K (c) 250 K

67 Device and Circuit Simulation, Measurement and Modelling 61 The hole and the electron tunnel into the depletion region, where they recombine under emission of a photon. This type of recombination is dominant in highly doped GaAs diodes at low temperature [2]. The energy peak was increasing as the applied voltage increases. This shift is explained by shift of the quasi-fermi levels with respect to each other. The tunnelling probability was reduced as the bias voltage increases and the tunnelling emission simultaneously was decreased. Therefore the band-band transition dominates at I > 3.29 µa by. This is clarified by the appearance of a second peak. At 250 K the recombination was interpreted as band-band transition due to the thermal injection (fig. 2c). The origin of the emission at energies higher than that of a band gap could be due to the high injection of minority carriers at the metal-semiconductor contact. This issue should be investigated further in more details. Temperature dependent photocurrent measurements were carried out, to investigate the photovoltaic properties of axial nanowire pn-junctions. With increasing light intensity the shortcircuit current and the open-circuit voltage both increased (fig. 3a and 3b). (a) (b) (c) Fig. 3 (a) Current-voltage measurements of a nanowire pn junction in the dark and under various excitation densities from 31.8 W/cm² to W/cm 2 at 10K. (b) Short-circuit current and open-circuit voltage as a function of the illumination power, corresponding to the measurements in (a). (c) Temperature dependence of photocurrent for a GaAs nanowire pn-diode under constant excitation density of 63,7 W/cm 2

68 62 Annual Report Solid-State Electronics Department In addition, the temperature dependence from the pn-doped GaAs nanowires were studied (Figure 3c). The recombination rate of light-generated carriers probably increase as the temperature is increasing resulting in a decreasing short circuit current. The open-circuit voltage increased as expected with decreasing temperature, this has been attributed to a reduced recombination rate. With a temperature variation between 10 K and 300 K and a constant excitation density of 63.7 W/cm 2, the fill factor varied between 32 % and 79 % and the efficiency changed between 0.1 % and 0,5 % for the pn doped nanowire. Conclusion In summary, electroluminescence and photovoltaic properties for radial doped pn nanowires were proved. It has been observed that the transitions at low and high currents differ. The low energy emission at low temperature was described as photon assisted tunnelling. At high excitations and high temperature the recombination was interpreted as band-band transition. With increasing light intensity the short-circuit current and the open-circuit voltage both increased. At 10K the fill factor of 32 % and the efficiency of 0.1 % could be achieved. References [1] Gerhard Schul Elektrolumineszenz bei Mischkristallen des Systems GaAs-AlAs Rheinisch- Westfälischen Technischen Hochschule Aachen, Dissertation, 1972 [2] H. C. Casey et al J.Appl. Phys. 40, 241 (1969)

69 Device and Circuit Simulation, Measurement and Modelling New Measurement Software For On-Wafer Characterization Of Microwave Voltage Controlled Oscillators Student: Scientist: K. Arzi B. Münstermann, I. Nannen Introduction Monolithic integrated Voltage Controlled Oscillators (VCO) are getting more important in communication field due to its small size, low power consumption and competitive performance. The on-wafer characterization of VCO chips, especially in free running mode can be challenging and is not provided by customers of commercial spectrum analyzers. Thus a new Software based on the LabVIEW environment has been developed to control the biasing and measurement hardware for complete VCO characterization for oscillation frequencies up to 50 GHz. Measurement Setup The measuring station consists of a spectrum analyzer (Agilent E4448A) with a frequency range from 1 Hz to 50 GHz, a HP4145B Parameter Analyzer and a Keithley 2400 source meter units (SMU). The devices under test can be connected by coaxial cables or if needed by using coplanar RF-probe tips for on-wafer characterization. To stabilize the output Signal the DC voltage supply is buffered with capacitors to filter noise originated from the sources. The tuning voltage is connected through the DC-Path of a Bias-Tee with a 50 Ohm termination at the RF-Path to avoid reflections on this port. All instruments are connected and controlled via GPIB (General Purpose Interface Bus) by the Lab Computer. For calibration and verification of the system a commercial VCO was used.

70 64 Annual Report Solid-State Electronics Department Agilent E4448A (Spectrum Analysis) HP4145B (Biasing) Keithley 2400 (Tuning) Bias Tee Probe Station Fig. 1 Measurement setup Software The Measuring software (Fig. 2) uses nearly 400 Subprograms to control the different instrument functions. The button names are the same as the button names on the Spectrum analyzer, to make the Program easy to use for users that are familiar with the Agilent Spectrum Analyzers. Fig. 2 Front panel of Measuring Software On the left side of the Main window the novel features of the program are located, which provides the user the ability to make different automated measurements on the VCO. Apart from frequency

71 Device and Circuit Simulation, Measurement and Modelling 65 tuning and the determination of power distribution on the harmonics of the signal the tuning sensitivity and frequency pushing can be investigated over a variety of bias voltage sweeps. Phase Noise Measurement in Spectrum Analysis Mode The integrated features of the Spectrum analyzer for measuring phase noise (Spot frequency and Log Plot) could not be used to measure the phase noise, due to the fact that the Carrier signal of the VCO drifts (free running mode). Therefore an algorithm was implemented, that measures the phase noise of a drifting carrier in spectrum Analyzer mode using short images of a narrow spectra around the carrier. The noise marker function is used to determine the power density in a 1 Hz bandwidth of the spot images. Before each spot image is recorded a carrier search is performed to minimize the effect of the drifting carrier on the noise measurement. The collected noise data is then plotted versus the offset frequency and the typical phase noise characteristics of the VCO can be viewed and stored in usual file formats. Additionally the optimal tuning voltage and best biasing to achieve minimal phase noise for user defined frequencies can be determined automatically. The optimal tuning voltage and the supply voltage is extracted from the measurements after the given bias range is swept. Measurement results The results accuracy were checked through a direct comparison between the measured results and the data sheet specifications. This test showed that almost all measurements were similar to the reference values. Fig.3a shows the tuning diagram of the commercial VCO. The results of this measurement are almost identical to the required values which ensures reliable characterization of the frequency characteristics. The measured signal power (Fig. 3b) revealed a small difference of up to 2 db between measured and expected values, which can be attributed to the frequency response of the measurement set up. a. Frequency output b. Power output Fig. 3 Tune curve

72 66 Annual Report Solid-State Electronics Department The measurement results for tuning sensitivity are in good agreement to the manufacture s data sheet, which confirms the correctness of the frequency tuning measurements. Measuring the phase noise ratio of the drifting signal turned out to be complicated, due to random frequency changes of the carrier signal. It was observed, that by using low-noise battery based power supply at the tuning input of the commercial VCO the random noise could be reduced. This indicates, that for precise phase noise measurement the power supply of the VCO has to be optimized for future investigations, especially when multiple on-wafer power supply is needed. Summary A new measurement software for frequency and noise characterization of microwave VCO was developed, which enables automated coaxial and on-wafer measurement set ups. The software and the set up configurations have been verified by the characterization of a commercial VCO at 3 GHz oscillation frequency. The measurement of phase noise of randomly drifting carriers was limited by the measurement set up and could be improved by using low noise power supply or phase locking of the VCO in future set up expansions.

73 Annual Report Solid-State Electronics Department Characterization and Optimization of Readout Electronics of MEMS Based Uncooled Long Wave Infrared (LWIR) Sensor Student: Supervisor: A. Troost D. Oshinubi, Robert Bosch GmbH, F.-J. Tegude, W. Brockerhoff Introduction LWIR sensors allow thermal imaging and therefore optical detection of hot spots in a particular scene e.g. humans or rockets even at night. To develop new areas like consumer or automotive applications the costs of these imaging systems have to be reduced. One point is the complete integration of sensor production process into the CMOS line [1]. Another is to reduce the number of external components like shutter for recalibration and thermo electric cooler (TEC) for substrate temperature regulation that provide temperature stabilisation. This work introduces methods for arithmetical temperature stabilisation to achieve a shutter and TEC less sensor operation and was executed at Robert Bosch GmbH, Stuttgart. Diode based uncooled LWIR sensor Uncooled sensors rely on thermal conductance by radiation instead of direct photon detection compared to cooled sensors. Thermal radiation is absorbed by a pixel structure that is thermally insulated from the sensor substrate. Therefore, the absorbed power generates a temperature difference that is evaluated by an electrical readout mechanism [2]. The LWIR sensor developed by Robert Bosch GmbH within the European ADOSE project uses the temperature dependent diode voltage while biased by a constant current [1]. Fig. 1 schematically shows the signal flow of this sensor. A differential readout is achieved by comparing the voltage of a pixel diode to a reference diode that is thermally short circuited to the substrate. The resulting voltage difference is amplified and shifted in its level to meet the input requirements of the analog digital converter. In addition the signal is offset corrected to compensate process variations. Image processing is realised by field programmable gate array (FPGA) and computer software.

74 68 Annual Report Solid-State Electronics Department Fig. 1 Schematic signal flow of the ADOSE LWIR sensor Temperature stabilisation Gradient compensation Temperature gradients in the sensor array that superpose temperature differences caused by LWIR radiation can degrade the thermal image. Therefore they need to be compensated. Current products are recalibrated for compensation using a shutter. To achieve shutter less operation the compensation has to be arithmetically, so additional temperature sensing of the substrate becomes necessary. Due to space issues temperature sensors can only be placed around the array to record the temperature profile along the array boundary. The temperature field of the array is evaluated by an iterative method closely related to the Gauß-Seidel method using a discrete Laplace operator. Advantages of this method compared to an analytic procedure are low computing time and higher noise suppression. To overcome the disadvantage a slow convergence the grids for the iterative method can be varied during operation. The coarse grid provides a very short convergence time while the fine grid provides a high accuracy. This compensation was implemented within the FPGA and is able to negate the influence of gradients without high dynamics. Absolute temperature compensation The displayed absolute temperature measured by LWIR sensors is very sensitive to ambient drifts [3]. This effect is based on the principle of thermal conductance by radiation and the problem that not only the recorded object is radiating onto the sensor pixel. Most of the absorbed power is emitted by the sensor casing. Both parts contributing to the complete absorbed power are depending on the temperature of emitter and absorber because thermal conductance by radiation is bidirectional [4]. This leads to a displayed temperature that is not just depending on the object temperature. Substrate and casing temperature dependency are even much higher than the object one e.g. a 1.3 K substrate temperature change results in a 9 K difference in displayed temperature. The compensation is done

75 Annual Report Solid-State Electronics Department 69 by temperature measurements of substrate and casing and calculating their influence on the absorbed power. The measurement results displayed in fig. 2 show that this correction provides the opportunity for shutter and TEC less operation. But a residual difference between display and real object temperature is still present. This error is caused by inaccurate measurements of substrate and casing temperature. Consideration of quadratic error propagation gives a minimum accuracy of 170 mk for substrate and casing temperature measurements to realise 2 K accuracy of displayed temperature. Fig. 2 Substrate and casing temperature compensation Summary Algorithms for arithmetical temperature compensation were developed. The compensation of temperature gradients in the pixel array area was implemented in the FPGA capable of negating gradients without high dynamics. A method and requirements for accurate correction of disturbances concerning absolute temperature measurements were identified. These two algorithms provide the basis for a shutter and TEC less operation of an uncooled LWIR sensor.

76 70 Annual Report Solid-State Electronics Department References [1] I. Herrmann, K.-F. Reinhart, T. Pirk, A. Feyh, D. Oshinubi, M. Eckardt, E. Sommer, U. Kunz, V. Krüger, F. Freund; Low-Cost Approach for Integrated Long-Wavelength Infrared Sensor Arrays; Proc. Eurosensors XXIV, 2010 [2] Mohamed Henini, Manijeh Razeghi; Handbook of Infrared Detection Technologies; Elsevier Science Ltd., 2002; ISBN [3] A. Fraenkel, U. Mizrahi, L. Bykov, A. Adin, E. Malkinson, Y. Zabar, D. Seter, Y. Gebil, Z. Kopolovich; Advanced features of SCD s uncooled detectors; Opto-Electronics Review 14, no. 1, 47-54, 2006 [4] H.D. Baehr, K. Stephan; Wärme- und Stoffübertragung; Springer-Verlag Berlin Heidelberg, 2008; ISBN

77 Conference Contributions Conference Contributions 1. A Nanowire Core/Shell Thermoelectric/Photovoltaic Device Concept G. SCHIERNING (1), A. TCHEGHO, I. REGOLIN, A. BECKER (1), W. PROST, F.-J. TEGUDE, R. SCHMECHEL (1) (1) Dept. of Process- and Aerosol Measurement, University Duisburg-Essen Nanomaterials for Energy Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems T. WAHO (1), W. PROST (1) Dept. of Electrical and Electronics Eng., Sophia University, 7-1 Kioicho, Chiyoda-ku, Tokyo, Japan JST- DFG Workshop on Nanoelectronics, Bad Honnef, Germany, On the Temporal Behavior of DC and RF Characteristics of InAs Nanowire MISFET Y. OTSUHATA (1), T. WAHO (1), K. BLEKKER, W. PROST, F.-J. TEGUDE, T. MIZUTANI (1) Dept. of Electrical and Electronics Eng., Sophia University, 7-1 Kioicho, Chiyoda-ku, Tokyo, Japan JST- DFG Workshop on Nanoelectronics, Bad Honnef, Germany, Design of Low-Power RTD-based-VCOs for Ka-Band Application B. MÜNSTERMANN, K. BLEKKER, A. TCHEGHO, W. BROCKERHOFF, F.-J. TEGUDE German Microwave Conference 2010 (GeMic), Berlin, Germany, Ion Beam Induced Alignment of Semiconductor Nanowires C. BORSCHEL (1), S. SPINDLER (1), R. NIEPELT (1), S. GEBURT (1), C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (1) (1) Inst. for Solid-State Physics, University of Jena, Germany (2) II. Inst. of Physics, University of Goettingen, Germany DPG Spring Meeting, Regensburg, Germany, Axial pn-junctions in vapour-liquid-solid grown GaAs Nanowires by MOVPE using DEZn and TESn I. REGOLIN, C. GUTSCHE, A. LYSOV, M. OFFER (1), A. LORKE (1), W. PROST, F.-J. TEGUDE (1) Dept. of Experimental Physics, University Duisburg-Essen 15th Int. Conf. on Metalorganic Vapour Phase Epitaxy (MOVPE) (IC MOVPE), Lake Tahoe, USA, Growth and Doping of InP Nanowires A. LYSOV, C. GUTSCHE, I. REGOLIN, R. BLACHE, Z.-A. LI (1), M. SPASOVA (1), W. PROST, F.-J. TEGUDE (1) Dept. of Experimental Physics, University Duisburg-Essen 15th Int. Conf. on Metalorganic Vapour Phase Epitaxy (MOVPE) (IC MOVPE), Lake Tahoe, USA, Scalable High-Current Density RTDS With Low Series Resistance A. TCHEGHO, B. MÜNSTERMANN, C. GUTSCHE, A. POLOCZEK, K. BLEKKER, W. PROST, F.-J. TEGUDE IEEE Int. Conf. on InP and Related Materials (IPRM), Kagawa, Japan,

78 72 Annual Report Solid-State Electronics Department 9. Fabrication and RF performance of InAs Nanowire FET W. PROST, F.-J. TEGUDE Annual Device Research Conference (DRC), South Bend, IN, USA, Gold catalyst initiated growth of GaN Nanowires by MOCVD H. BEHMENBURG (1), J. P. AHL (1), C. GIESEN (1), I. REGOLIN, W. PROST, F.-J. TEGUDE, G. Z. RADNÓCZI (1), B. PÉCZ (1), H. KALISCH (1), R.H. JANSEN (1), M. HEUKEN (1) (1) AIXTRON AG, Herzogenrath, Germany (2) ITHE, RWTH Aachen, Germany (3) MTA, MFA, Budapest, Hungary International Workshop on Nitride semiconductors 2010 (IWN), Tampa, FL, USA, Circuit Implementation of InAs Nanowire FET W. PROST, K. BLEKKER, O. BENNER, F.-J. TEGUDE 2010 Int. Conf. on Solid State Devices and Materials (ssdm), Tokyo, Japan, III-V-Semiconductor Nanowires for Device Applications: Morphological, Electrical and Optical Properties C. GUTSCHE, A. LYSOV, I. REGOLIN, K. BLEKKER, W. PROST, F.-J. TEGUDE SFB 445 and CeNIDE Symposium Nanoparticles from the Gas Phase, San Servolo, Venice, Italy, Ga out-diffusion during annealing of Ge and Pd based contacts on n-gaas nanowires C. GUTSCHE, A. LYSOV, S. KÖPPEN, W. PROST, F.-J. TEGUDE Nanoelectronic Days 2010 (ND), Aachen, Germany, An InAs Nanowire-MISFET based Sample & Hold Circuit O. BENNER, K. BLEKKER, I. REGOLIN, A. LYSOV, W. PROST, F.-J. TEGUDE Nanoelectronic Days 2010 (ND), Aachen, Germany, III-V-Nanowire FET F.-J. TEGUDE Symposium on Opto- and Microelectronic Devices and Circuits 2010 (SODC), Berlin, Germany, Optical properties of single GaAs nanowire pn-diodes grown via VLS growth mechanism A. LYSOV, C. GUTSCHE, I. REGOLIN, M. OFFER (1), W. PROST, F.-J. TEGUDE (1) Dept. of Experimental Physics, University Duisburg-Essen 5th Nanowire Growth Workshop 2010 (NGW), Rom, Italy, Optical properties of single GaAs nanowire pn-diodes grown via VLS growth mechanism A. LYSOV, C. GUTSCHE, I. REGOLIN, M. OFFER, W. PROST, F.-J. TEGUDE (1) Dept. of Experimental Physics, University Duisburg-Essen CeNIDE Vollversammlung, Duisburg

79 Conference Contributions Axial and Radial GaAs Nanowire pn-junctions W. PROST Dutch Nanowire Meeting, Eindhoven, The Netherlands, Gold catalyst initiated growth of GaN Nanowires by MOCVD J. P. AHL (1), (2), H. BEHMENBURG (2), C. GIESEN (1), I. REGOLIN, W. PROST, F.-J. TEGUDE, G. Z. RADNÓCZI (3), B. PÉCZ (3), H. KALISCH (2), R.H. J ANSEN (2), M. HEUKEN (1), (2) (1) AIXTRON AG, Herzogenrath, Germany (2) ITHE, RWTH Aachen, Germany (3) MTA, MFA, Budapest, Hungary 25. DGKK Workshop 2010, Aachen, Germany, Optoelektronische Eigenschaften von MOVPE gewachsenen axialen GaAs Nanodraht pn- Dioden A. LYSOV, C. GUTSCHE, I. REGOLIN, M. OFFER (1), W. PROST, F.-J. TEGUDE (1) Center for Nanointegration Duisburg-Essen (CeNIDE), University Duisburg-Essen 25. DGKK Workshop 2010, Aachen, Germany,

80 74 Annual Report Solid-State Electronics Department 4.5 Publications 1. InP-based Unipolar Heterostructure Diode for Vertical Integration, Level Shifting and Small Signal Rectification W. PROST, B. MÜNSTERMANN, D. ZHANG, T. FELDENGUT (1), R. GEITMANN, A. POLOCZEK, F.-J. TEGUDE (1) Dept. of Electronic Devices and Circuits, University Duisburg-Essen IEICE Transactions on Electronics, Volume E93.C, Issue 8, pp (2010) 2. Tailoring the properties of semiconductor nanowires using ion beams C. RONNING (1), C. BORSCHEL (1), S. GEBURT (1), R. NIEPELT (1), S. MÜLLER (1), D. STICHTENOTH (1), J. -P. RICHTERS (1), A. DEV (1), T. VOSS (1), L. C HEN (1), W. HEIMBRODT (1), C. GUTSCHE, W. PROST (1) Inst. for Solid-State Physics, University of Jena, Germany (2) II. Inst. of Physics, University of Goettingen, Germany Phys. Status Solidi B 247, No. 10, (2010) 3. III-V-Nanowire FET F.-J. TEGUDE Proc. 'Symposium on Opto- and Microelectronic Devices and Circuits 2010 (SODC), Berlin, Germany, ' 4. Scalable High-Current Density RTDS With Low Series Resistance A. TCHEGHO, B. MÜNSTERMANN, C. GUTSCHE, A. POLOCZEK, K. BLEKKER, W. PROST, F.-J. TEGUDE Proc. 'IEEE Int. Conf. on InP and Related Materials (IPRM), Kagawa, Japan, ' 5. Design of Low-Power RTD-based-VCOs for Ka-Band Application B. MÜNSTERMANN, K. BLEKKER, A. TCHEGHO, W. BROCKERHOFF, F.-J. TEGUDE Proc. 'German Microwave Conference 2010 (GeMic), Berlin, Germany, ' 6. High Frequency Measurements on InAs Nanowire Field-Effect Transisotrs Using Coplanar Waverguide Contacts K. BLEKKER, B. MÜNSTERMANN, A. MATISS, Q.T. DO, I. REGOLIN, W. BROCKERHOFF, W. PROST, F.-J. TEGUDE IEEE Transactions on Nanotechnology, Vol. 9, No. 4, July 2010, pp

81 Research Projects Research Projects Nano Particles from the Gas Phase Sonderforschungsbereich 445 (SFB 445) supported by Deutsche Forschungsgemeinschaft (DFG) together with other departments at the University Duisburg-Essen Nano Wires and Nano Tubes supported by Deutsche Forschungsgemeinschaft (DFG) RTD/HBT-Kombinationsbauelemente für Oszillatoranwendungen für die Satellitenkommunikation im Ku- und Ka-Band supported by German Aerospace Center (DLR) Optoelektronische Digitalschaltungen auf der Basis von Resonanztunneldioden und Photodioden den-arrays supported by Deutsche Forschungsgemeinschaft (DFG) NaSoL - Halbleiter-Nanodrähte für Solarzellen und Leuchtdioden supported by European Union Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems supported by Deutsche Forschungsgemeinschaft (DFG)

82 76 Annual Report Solid-State Electronics Department 4.7 The Mobile Electronic School Lab (MESLAB) W. Brockerhoff Introduction The small number of pupils who actually decide to start academic studies of electronics becomes an increasing problem for the national economics. To increase the number of pupils interested in electrical and electronic subjects the Mobile Electronic School Lab (MESLAB) was initiated and carried out in cooperation with schools in Duisburg and the Niederrhein region as e.g.: Stiftsgymnasium Xanten Michael Ende Gymansium, Tönisvorst Josef-Albers Gymnasium, Bottrop In Workgroups with a maximum capacity of 20 participants the pupils get first experimental experiences with electronic devices. During the first part of the course, everyone of them has to assemble small electronic circuits to become acquainted with the functionality of simple electronic devices like resistances, capacitors and (photo) transistors, as well (fig. 1). Fig. 1 MESLAB at the Michael-Ende Gymnasium, Tönisvorst

83 Other Activities 77 For that purpose an experimental setup with all necessary devices and equipment was developed and collected in a portable box (fig. 2). Fig. 2 Box with the selection of electronic devices for experimental setups In the second part of this course, the participants has to realize an alarm system with e.g. a photoelectric barrier or a touch sensor as alarm sensor. The alarm is indicated by flash lights and/or a horn. In small groups of maximal three participants, the pupils have to design all necessary layouts and to assemble the electronic circuits. Fig. 3 The electronic course at the Stiftsgymnaisum, Xanten

84 78 Annual Report Solid-State Electronics Department At the end, they present their results and all modules are connected to proof the functionality of the complete system (fig. 3 and 4). This final presentation is combined with a visit of the clean room facilities of the center of solid-state electronics and optoelectronics (ZHO) (fig. 5). Fig. 4 Final presentation of the alarm system within the 'Junior-Ingenieur Akademie' Fig. 5 Visit of the clean room facilities of the ZHO This project is also part of the Schüler- Ingenieur-Akademie (SIA) as well as the Junior-Ingenieur-Akademie (JIA) which is organized by the Max-Planck Gymnasium, Duisburg, together with other departments of the faculty of engineering. This academy takes 2 years and is executed together with the Steinbart Gymnasium, Duisburg, as well as with the Franz-Haniel Gymnasium, Duisburg. At the beginning this academy was supported by the German Telekom Foundation and is now sponsored by the Förderverein Ingenieurwissenschaften.

85 Other Activities 79

86 80 Annual Report Solid-State Electronics Department Guide to the Solid-State Electronics Department (HLT) Z entrum für H albleitertechnik und O ptoelektronik Lotharstr. 55, D Duisburg, Gebäude LT Travel by car: The Solid-State Electronics Department (HLT) at the ZHO (Zentrum für Halbleitertechnik und Optoelektronik) can be reached by car via various highways: A3 from the South, A40 from the Netherlands and the East, A2/A3 from the North. Exit: Duisburg-Kaiserberg or Duisburg-Wedau (see map). Travel by plane: After arriving at the Düsseldorf Airport (the next airport to Duisburg) take one of the various trains (S, RE, RB) from Düsseldorf Airport Train Station to Duisburg Main Station (Hauptbahnhof (Hbf). For further information see: Travel by train: The Duisburg Main Station (Hauptbahnhof (Hbf)) is in 25 min walking distance from the Solid-State Electronics Department (HLT) and the ZHO (see map). Take the bus lines 933, 936 or 924 to Universität/Städtische Kliniken and get off at Universität(Uni-Nord) or take the subway line 901 to Mülheim and get off at Universität.