2. ADC Architectures and CMOS Circuits

Transcription

1 /56 2. Architectures and CMOS Circuits Francesc Serra Graells Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated Circuits and Systems IMB-CNM(CSIC)

2 2/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

3 3/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

4 4/56 Families Classification based on architecture approach: High speed Sub-ranging Analog signal Digital signal Parallel Interleaved Pipeline voltage/current amplitude Digital timebase code Algorithmic Predictive SAR Integrating Delta-Sigma Distinctive characteristics: Feedforward vs feedback control Single vs multiple stages Amplitude vs time domains...and many more! Typically mixed solutions... High dynamic range

5 5/56 Evolution EPSCO DATRAC, B.M. Gordon, 953 -bit 50KSps 500W SAR 0.5m x 0.4m x 0.65m, 70Kg Vacuum tube technology W. Kester, Analog-Digital Conversion archives/39-06/data_conversion_handbook.html

6 6/56 Evolution +60years Pipeline SAR Delta-Sigma Other State-of-art Solid-state technologies B. Murmann, Performance Survey EPSCO DATRAC, B.M. Gordon, 953 -bit 50KSps 500W SAR 0.5m x 0.4m x 0.65m, 70Kg Vacuum tube technology W. Kester, Analog-Digital Conversion archives/39-06/data_conversion_handbook.html P/f s [J] fJ/conv-step 70dB SNDR [db] -bit

7 7/56 Evolution Performance enhancement: Architecture strategy Circuit design Integration technology State-of-art Solid-state technologies Still room for further improvement? Pipeline SAR Delta-Sigma Other B. Murmann, Performance Survey P/f s [J] SNDR [db]

8 8/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

9 9/56 Basic Architecture Building blocks: Threshold generator Latched comparator array e.g. single-ended 3-bit flash thermometer code natural binary code Digital encoder combinational only logic

10 0/56 Basic Architecture Building blocks: e.g. single-ended 3-bit flash Threshold generator Latched comparator array thermometer code clock cycle conversion time natural binary code Digital encoder Area and power scaling by 2 ENOB Distortion due to technology mismatching combinational only logic

11 /56 Latched Comparator Design Compact CMOS circuit: clock M3 M4 Non-overlapped clock phases M M2

12 2/56 Latched Comparator Design Compact CMOS circuit: clock M3 M4 High-speed operation Non-overlapped clock phases Each comparator crosses at different threshold V thk M M2 Threshold voltage offset? Pre-charging phase Decision phase M3 M4 0 0 M3 M4 Positive feedback to speed-up comparison Symmetrical loading M M2 M M2

13 3/56 Comparator Optimization By attaching an array of level shifters: clock single-ended version Ck C2k signal baseline Ck C2k Ck C2k

14 4/56 Comparator Optimization By attaching an array of level shifters: clock Ck C2k single-ended version All comparators latch at the same level (V ref ) Single comparator design Low quiescent power (resistor-less thresholds) Capacitor area overhead Input capacitance increased Slower operation signal baseline Ck C2k Ck C2k effective signal effective k-threshold

15 5/56 Comparator Optimization By attaching an array of level shifters: clock Ckp C2kp fully-differential version Interference rejection Full-scale extension (+6dB) SNR enhancement (+3dB) Distortion cancellation (even harmonics) Ckn C2kn Area and power overheads (x2) Higher symmetry requirements Time

16 6/56 Comparators Offset Distortion due to DNL MOSFET V TH mismatching effects: M3 M4 M M2 CMOS technology Pelgrom's Law

17 7/56 Comparators Offset Thermometer code bubbles! Error propagation at encoding... Bubble 0 0 Latched comparator array 0 Digital encoder Gaussian probability distribution Large device area (WL) and input capacitance penalties

18 8/56 Comparators Offset Thermometer code bubbles! Digitally assisted analog design: Latched comparator array Bubble Bubble error correction (BEC) Digital encoder?

19 9/56 Comparators Offset Thermometer code bubbles! Digitally assisted analog design: Latched comparator array Bubble Bubble error correction (BEC) Digital encoder (WL) large enough to limit bubble distance to code: 0 X X 0 X 0 () X

20 20/56 Comparators Offset More on digitally assisted analog design: an stochastic flash Digital inverse Gaussian integral e.g. 63 comparators Digital full-adders S. Weaver, B. Hershberg and Un-Ku Moon, Digitally Synthesized Stochastic Using Only Standard Digital Cells, IEEE Transactions on Circuits and Systems I, 6():84-9, Jan 204

21 2/56 Comparators Offset More on digitally assisted analog design: an stochastic flash Almost digital Compact area Digital inverse Gaussian integral Non-linearity compensation required Power consumption e.g. 63 comparators Digital full-adders S. Weaver, B. Hershberg and Un-Ku Moon, Digitally Synthesized Stochastic Using Only Standard Digital Cells, IEEE Transactions on Circuits and Systems I, 6():84-9, Jan 204

22 22/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

23 23/56 Sub-Range Building blocks: Fine stage S/H DAC ENOB/2 bit ENOB/2 bit ENOB/2 bit Coarse stage MSB Encoder LSB Two-step coarse-fine data conversion scheme ENOB splitting can be chosen asymmetric depending on circuits...

24 24/56 Sub-Range Building blocks: Fine stage S/H Coarse stage ENOB/2 bit DAC ENOB/2 bit MSB Encoder ENOB/2 bit LSB Speed reduction (x2) Non-linearity caused by mismatching between coarse -DAC, and between coarse-fine Two-step coarse-fine data conversion scheme ENOB splitting can be chosen asymmetric depending on circuits... Better ENOB scaling of comparators and passive components! e.g. Number of comparators for 8-bit flash : single-stage two-stage

25 25/56 Sub-Range Circuit implementation: S/H Fine stage Non-linearity cuased by non-unitary gain in MSB substraction Compact SC implementation: ENOB/2 bit DAC ENOB/2 bit ENOB/2 bit to coarse flash C single-ended version Coarse stage MSBs Encoder LSBs C C coarse fine signal baseline C/2 to fine flash clock from coarse flash C/4

26 26/56 Time-Interleaved Two-step CMOS comparator: sampling + auto-zero C single-ended version M2 M clock S Q C M2 M substraction + quantization C M2 M Offset insensitive! Compact area analog inverter-based Poor power supply rejection ratio (PSRR)

27 27/56 Time-Interleaved Counter-phase two-step CMOS comparator: Offset insensitive! clock S Q Q S CA M2A MA Compact area Higher speed (x2) 0 CB M2B MB Poor power supply rejection ratio (PSRR) Higher jitter sensitivity (both clock edges)

28 28/56 Time-Interleaved Extending the same idea to multiple time-interleaving: clock S Q S S S Q Q Q Q S e.g. N=4 Overall equivalent high-speed conversion Each flash operates at low-speed (/N) Q Q Q S S S Large area (xn) High latency (xn) Complex synchronization

29 29/56 Pipeline Combination of cascaded sub-ranging and time-interleaving: clock Stage Stage 2 Stage M stage stage 2 p-bit q-bit r-bit stage M MSB Time Alignment LSB Time Alignment S/H Sub-converter functions: DAC residue same i/o full-scale Sampling and hold (S/H) Sub-range quantization p-bit p-bit Residue computation and scaling Sub-converter

30 30/56 Pipeline Combination of cascaded sub-ranging and time-interleaving: clock Stage Stage 2 Stage M stage stage 2 p-bit q-bit r-bit stage M MSB Time Alignment LSB Time Alignment Simpler flash sub-s S/H Performance depends on first-stage only p-bit DAC p-bit residue same i/o full-scale No speed reduction High latency (xm) Sub-converter

31 3/56 Pipeline Simple -bit stage case study: Stage Stage 2 Stage M Time Alignment M SC implementation of each stage: single-ended version signal baseline

32 32/56 Pipeline clock Simple -bit stage case study: Stage Stage 2 Stage M sampling + quantization () Time Alignment M SC implementation of each stage: single-ended version residue (>0) + scaling signal baseline

33 33/56 Pipeline Simple -bit stage case study: Stage Stage 2 Stage M Time Alignment M SC implementation of each stage: single-ended version Simplest flash sub-s Inherently linear single bit quantization signal baseline Noise contributions from stage 2 multi-bit first stage Offset sensitivity

34 34/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

35 35/56 Successive Approximation Building blocks: residue S/H digital state-machine (algorithm) approximation DAC N-bit Successive Approximation Register (SAR) N

36 36/56 Successive Approximation Building blocks: residue e.g. 4-bit SAR S/H digital state-machine (algorithm) Successive Approximation Register (SAR) approximation DAC N time N-bit MSB LSB time Analog minimalist Very low-power consumption Speed requirements (xn) Performance limited by flash DAC

37 37/56 Successive Approximation Circuit implementation: clock S/H DAC N-bit Successive Approximation Register (SAR) N single-ended version to SAR from SAR signal baseline

38 38/56 Successive Approximation Circuit implementation: clock S/H DAC N-bit Successive Approximation Register (SAR) N single-ended version to SAR from SAR signal baseline

39 39/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

40 40/56 Single-Slope Building blocks: S/H enable reset Digital counter N pulse-width modulation (PWM) clock 0 time

41 4/56 Single-Slope Building blocks: S/H enable reset Digital counter N pulse-width modulation (PWM) clock Analog minimalist Very low-power Speed requirements (x2 N ) Technological sensitivity (RC) 0 time

42 42/56 Dual-Slope Building blocks: S/H control reset Dual counter N clock Analog minimalist Very low-power Speed requirements (x2 N ) Technology independence (RC) 0 time

43 43/56 Integrate-and-Fire Building blocks: reset Asynchronous counter N pulse-density modulation (PDM) Current-mode sensors (e.g. imagers) Very low-power Speed requirements adapted to signal Technology sensitivity (C) 0 time

44 44/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

45 45/56 Delta-Sigma Modulator General single-loop DSM architecture: noise-shaper (predictor) quantizer error DSM digital output S/H DAC digital decimator (down sampler) prediction feedback DAC

46 46/56 Delta-Sigma Modulator General single-loop DSM architecture: S/H noise-shaper (predictor) quantizer error prediction DAC feedback DAC DSM digital output digital decimator (down sampler) Noise-shaper filter: In-band high-gain Either continuous- H(s) or discrete-time H(z) and DAC blocks can be relaxed! DSM signal vs quantization noise behavior? signal quantization noise output

47 47/56 Delta-Sigma Noise Shaping Simplest architecture: first-order (N=) -bit (B=) single-loop DSM S/H integrator comparator Single-bit feedback DAC is intrinsically linear time

48 48/56 Delta-Sigma Noise Shaping Simplest architecture: first-order (N=) -bit (B=) single-loop DSM S/H integrator comparator Single-bit feedback DAC is intrinsically linear Oversampling is needed all-pass (delay) (differentiator) log(power) signal 20dB/dec out-band noise high-pass shaping log(frequency)

49 49/56 Delta-Sigma Noise Shaping Simplest architecture: first-order (N=) -bit (B=) single-loop DSM S/H integrator comparator Single-bit feedback DAC is intrinsically linear Oversampling is needed Higher order (N>) shaping to avoid signal to quantization noise correlation (harmonics) log(power) all-pass (delay) signal in-band harmonics (differentiator) high-pass shaping log(frequency)

50 50/56 Delta-Sigma Noise Shaping Higher-order (N) noise shaping: first integrator second integrator S/H gain coefficients Sharper noise shaping log(power) Signal to quantization noise uncorrelation (continuous spectra) 40dB/dec Possibility of loop instability for N>2 Coefficients optimization! log(frequency)

51 5/56 DSM Design N-order B-bit single loop architecture: S/H multi-bit (B) quantization Multi-bit quantization: Resolution added to overall DR Internal full-scale reduction Feedback DAC not intrinsically linear High-order filtering: Sharper noise shaping Stability issues Ideal dynamic range: shaping order oversampling only log(power) signal (N+0.5)-bit/oct(OSR) 20N db/dec 6N db/oct direct improvement log(frequency)

52 52/56 DSM Design Feedfoward cancellation: Internal full scale low occupancy Additional adder stage in front of quantizer S/H Resonator attenuation: Extra noise shaping at band edge Zero sensitivity to coefficient matching log(power) S/H log(frequency)

53 53/56 DSM SC Circuits clock S X Fully-differential 2nd-order single-bit example: input sampler reuse for DAC feedback common mode integrator initialization passive adder

54 54/56 Classification Techniques Sub-Ranging, Time-Interleaving and Pipelining Techniques Successive-Approximation Techniques Integrating Techniques Delta-Sigma Modulation Techniques Time-Domain Techniques

55 55/56 Voltage-to-Frequency Building blocks: voltage-controlled oscillator (VCO) reset Coarse counter S/H MSB Fine register Encoder LSB N S Q

56 56/56 Voltage-to-Frequency Building blocks: voltage-controlled oscillator (VCO) reset Coarse counter S/H MSB Fine register Encoder LSB N All-MOS circuit implementation Non-linearity V in -I bias and I bias -f VCO S Q Low-voltage operation Technology sensitivity