1 Two-Channel Analog Front End MCP3901 Features Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture 91 db SINAD, -104 dbc Total Harmonic Distortion (THD) (up to 35 th harmonic), 109 db Spurious-free Dynamic Range (SFDR) for Each Channel Programmable Data Rate up to 64 ksps Ultra Low-Power Shutdown mode with <2 µa -133 db Crosstalk Between the Two Channels Low Drift Internal Voltage Reference: 12 ppm/ C Differential Voltage Reference Input Pins High Gain PGA on Each Channel (up to 32 V/V) Phase Delay Compensation Between the Two Channels with 1 µs time Resolution Separate Modulator Outputs for Each Channel High-Speed, Addressable 20 MHz SPI Interface with Mode 0,0 and 1,1 Compatibility Independent Analog and Digital Power Supplies: 4.5V-5.5V AV DD, 2.7V-5.5V DV DD Low-Power Consumption: (14 mw typical at 5V) Available in Small 20-lead SSOP and QFN Packages Industrial Temperature Ranges: - Industrial: -40 C to +85 C - Extended: -40 C to +125 C Applications Energy Metering and Power Measurement Automotive Portable Instrumentation Medical and Power Monitoring Description The MCP3901 is a dual channel Analog Front End (AFE) containing two synchronous sampling Delta- Sigma Analog-to-Digital Converters (ADC), two PGAs, phase delay compensation block internal voltage reference, modulator output block, and high-speed 20 MHz SPI compatible serial interface. The converters contain a proprietary dithering algorithm for reduced Idle tones and improved THD. The internal register map contains 24-bit wide ADC data words, a modulator output byte, as well as six writable control registers to program gain, oversampling ratio, phase, resolution, dithering, shutdown, Reset and several communication features. The communication is largely simplified with various Continuous Read modes that can be accessed by the Direct Memory Access (DMA) of an MCU and with a separate data ready pin that can be connected directly to an Interrupt Request (IRQ) input of an MCU. The MCP3901 is capable of interfacing to a large variety of voltage and current sensors, including shunts, current transformers, Rogowski coils and Halleffect sensors. Package Type 20-Lead SSOP RESET 20-Lead QFN AV DD DV DD RESET EP 21 SDI SDI SDO SCK CS OSC2 OSC1/CLKI DR MDAT0 MDAT1 DGND SDO SCK 14 CS 13 OSC2 12 OSC1/CLKI DR DV DD AV DD CH0+ CH0- CH1- CH1+ AGND REFIN/OUT+ REFIN- CH0+ CH0- CH1- CH1+ AGND REFIN/OUT+ REFIN- DGND MDAT1 MDAT0 * Includes Exposed Thermal Pad (EP); see Table Microchip Technology Inc. DS22192D-page 1
2 Functional Block Diagram REFIN/OUT+ REFIN - CH0+ CH0- CH1+ CH1- AV DD DV DD Voltage VREFEXT Reference + V REF - V REF - V REF + ANALOG DIGITAL POR AV DD Monitoring + - PGA + - PGA Δ -Σ Modulator Δ -Σ Modulator SINC 3 SINC 3 Phase Shifter DUAL DS ADC SDN<1:0>, RESET<1:0>, GAIN<7:0> Φ MOD<7:0> POR AMCLK DMCLK/DRCLK DATA_CH0<23:0> PHASE <7:0> DATA_CH1<23:0> Clock Generation DMCLK Digital SPI Interface Modulator Output Block OSR<1:0> PRE<1:0> MODOUT<1:0> Xtal Oscillator MCLK OSC1 OSC2 DR SDO RESET SDI SCK CS MDAT0 MDAT1 AGND DGND DS22192D-page Microchip Technology Inc.
3 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings V DD...7.0V Digital inputs and outputs w.r.t. A GND V to V DD +0.6V Analog input w.r.t. A GND V to +6V V REF input w.r.t. A GND V to V DD +0.6V Storage temperature C to +150 C Ambient temp. with power applied C to +125 C Soldering temperature of leads (10 seconds) C ESD on the analog inputs (HBM,MM) kv, 400V ESD on all other pins (HBM,MM) kv, 400V Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, AV DD = 4.5 to 5.5V, DV DD = 2.7 to 5.5V; -40 C < T A < +85 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = -0.5 dbfs = 333 mv 50/60 Hz Parameters Symbol Min Typical Max Units Conditions Internal Voltage Reference Internal Voltage Reference V REF -2% % V VREFEXT = 0 Tolerance Temperature Coefficient TC REF 12 ppm/ C VREFEXT = 0 Output Impedance ZOUT REF 7 kω AV DD = 5V, VREFEXT = 0 Voltage Reference Input Input Capacitance 10 pf Differential Input Voltage Range (V REF+ V REF- ) V REF V V REF = (V REF+ V REF- ), VREFEXT = 1 Absolute Voltage on REFIN+ Pin V REF V VREFEXT = 1 Absolute Voltage on REFIN- Pin V REF V ADC Performance Resolution (No Missing Codes) 24 bits OSR = 256 (See Table 5-3) Sampling Frequency f S See Table 4-2 khz f S = DMCLK = MCLK/ (4 x PRESCALE) Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic performance is specified at -0.5 db below the maximum signal range, V IN = /60 Hz = 353 mv RMS, V REF = 2.4V. 2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00, VREFEXT = 0, CLKEXT = 0. 5: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11, VREFEXT = 1, CLKEXT = 1. 6: Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values). 7: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied continuously to the part with no risk for damage. 8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to MHz, AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to Microchip Technology Inc. DS22192D-page 3
4 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, AV DD = 4.5 to 5.5V, DV DD = 2.7 to 5.5V; -40 C < T A < +85 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = -0.5 dbfs = 333 mv 50/60 Hz Parameters Symbol Min Typical Max Units Conditions Output Data Rate f D See Table 4-2 ksps f D = DRCLK = DMCLK/ OSR = MCLK/ (4 x PRESCALE x OSR) Analog Input Absolute Voltage on CH0+, CH0-, CH1+, CH1- Pins CHn V All analog input channels, measured to AGND (Note 7) Analog Input Leakage Current A IN 1 na (Note 4) 2 na -40 C < T A < 125 C Differential Input Voltage Range (CHn+ CHn-) 500/GAIN mv (Note 1) Offset Error (Note 2) V OS mv (Note 6) Offset Error Drift 3 µv/ C From -40 C to +125 C Gain Error (Note 2) GE -0.4 % G = % All Gains Gain Error Drift 1 ppm/ C From -40 C to +125 C Integral Nonlinearity (Note 2) INL 15 ppm GAIN = 1, DITHER = On Input Impedance Z IN 350 kω Proportional to 1/AMCLK Signal-to-Noise and Distortion Ratio (Notes 2, 3) Total Harmonic Distortion (Notes 2, 3) Signal-to-Noise Ratio (Notes 2, 3) Spurious Free Dynamic Range (Note 2) SINAD db OSR = 256, DITHER = On db THD db OSR = 256, DITHER = On db SNR db OSR = 256, DITHER = On db SFDR 109 db OSR = 256, DITHER = On 87 db Crosstalk (50/60 Hz) (Note 2) CTALK -133 db OSR = 256, DITHER = On Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic performance is specified at -0.5 db below the maximum signal range, V IN = /60 Hz = 353 mv RMS, V REF = 2.4V. 2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00, VREFEXT = 0, CLKEXT = 0. 5: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11, VREFEXT = 1, CLKEXT = 1. 6: Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values). 7: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied continuously to the part with no risk for damage. 8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to MHz, AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to 0. DS22192D-page Microchip Technology Inc.
5 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, AV DD = 4.5 to 5.5V, DV DD = 2.7 to 5.5V; -40 C < T A < +85 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = -0.5 dbfs = 333 mv 50/60 Hz Parameters Symbol Min Typical Max Units Conditions AC Power Supply Rejection AC PSRR -77 db AV DD and DV DD = 5V + 1V 50/60 Hz DC Power Supply Rejection DC PSRR -77 db AV DD and DV DD = 4.5 to 5.5V DC Common-Mode Rejection Ratio (Note 2) Oscillator Input CMRR -72 db V CM varies from -1V to +1V Master Clock Frequency Range MCLK MHz (Note 8) Power Specifications Operating Voltage, Analog AV DD V Operating Voltage, Digital DV DD V Power On Reset Threshold POR 4.2 V (Note 3) C < T A < 125 C, (Note 3) Operating Current, Analog (Note 4) AI DD ma BOOST<1:0> = ma -40 C < T A < 125 C, BOOST<1:0> = ma BOOST<1:0> = ma -40 C < T A < 125 C, BOOST<1:0> = 11 Operating Current, Digital DI DD ma DV DD = 5V, MCLK = 4 MHz ma DV DD = 2.7V, MCLK = 4 MHz ma DV DD = 5V, MCLK = MHz Shutdown Current, Analog I DDS,A 1 µa AV DD pin only (Note 5) Shutdown Current, Digital I DDS,D 1 µa DV DD pin only (Note 5) Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic performance is specified at -0.5 db below the maximum signal range, V IN = /60 Hz = 353 mv RMS, V REF = 2.4V. 2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00, VREFEXT = 0, CLKEXT = 0. 5: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11, VREFEXT = 1, CLKEXT = 1. 6: Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values). 7: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied continuously to the part with no risk for damage. 8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to MHz, AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to Microchip Technology Inc. DS22192D-page 5
6 SERIAL INTERFACE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply: AV DD = 4.5 to 5.5V, DV DD = 2.7 to 5.5V, -40 C < T A < +85 C, C LOAD = 30 pf Parameters Sym Min Typ Max Units Conditions Serial Clock Frequency f SCK MHz MHz 4.5 DV DD DV DD < 5.5 CS Setup Time t CSS ns ns 4.5 DV DD DV DD 5.5 CS Hold Time t CSH ns ns 4.5 DV DD DV DD < 5.5 CS Disable Time t CSD 50 ns Data Setup Time t SU 5 10 Data Hold Time t HD Serial Clock High Time t HI Serial Clock Low Time t LO ns ns ns ns ns ns ns ns 4.5 DV DD DV DD < DV DD DV DD < DV DD DV DD < DV DD DV DD < 5.5 Serial Clock Delay Time t CLD 50 ns Serial Clock Enable Time t CLE 50 ns Output Valid from SCK Low t DO 50 ns 2.7 DV DD < 5.5 Modulator Output Valid from AMCLK t DOMDAT 1/2 * AMCLK s High Output Hold Time t HO 0 ns (Note 1) Output Disable Time t DIS ns ns 4.5 DV DD DV DD < 5.5 (Note 1) Reset Pulse Width (RESET) t MCLR 100 ns 2.7 DV DD < 5.5 Data Transfer Time to DR (data ready) t DODR 50 ns 2.7 DV DD < 5.5 Data Ready Pulse Low Time t DRP 1/DMCLK µs 2.7 DV DD < 5.5 Schmitt Trigger High-Level Input Voltage V IH1.7 DV DD DV DD + 1 V Schmitt Trigger Low-Level Input Voltage V IL DV DD V Hysteresis of Schmitt Trigger Inputs (all digital inputs) V HYS 300 mv Low-Level Output Voltage, SDO Pin V OL 0.4 V SDO pin only, I OL = +2.0 ma, V DD = 5.0V Low-level output voltage, DR and MDAT Pins V OL 0.4 V DR and MDAT pins only, I OL = +800 ma, V DD = 5.0V High-level output voltage, SDO pin V OH DV DD 0.5 V SDO pin only, I OH = -2.0 ma, V DD = 5.0V High-level output voltage, DR and MDAT pins V OH DV DD 0.5 V DR and MDAT pins only, I OH = -800 µa, V DD = 5.0V Input leakage current I LI ±1 µa CS = DV DD, V IN = DGND or DV DD Output leakage current I LO ±1 µa CS = DV DD, V OUT = DGND or DV DD Internal capacitance (all inputs and outputs) Note 1: This parameter is periodically sampled and not 100% tested. C INT 7 pf T A = 25 C, SCK = 1.0 MHz, DV DD = 5.0V (Note 1) DS22192D-page Microchip Technology Inc.
7 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AV DD = 4.5 to 5.5V, DV DD = 2.7 to 5.5V Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T A C (Note 1) Storage Temperature Range T A C Thermal Package Resistances Thermal Resistance, 20L SSOP θ JA 89.3 C/W Thermal Resistance, 20L QFN θ JA 43 C/W Note 1: The internal junction temperature (T J ) must not exceed the absolute maximum specification of +150 C. CS t HI f SCK t LO t CSH Mode 1,1 SCK Mode 0,0 t DO t HO t DIS SDO MSB Out LSB Out SDI Don t Care FIGURE 1-1: Serial Output Timing Diagram. t CSD CS t CLE t CSS Mode 1,1 f SCK t HI t LO t CSH t CLD SCK Mode 0,0 t SU t HD SDI MSB In LSB In SDO HI-Z FIGURE 1-2: Serial Input Timing Diagram Microchip Technology Inc. DS22192D-page 7
8 1/DRCLK DR t DODR t DRP SCK SDO FIGURE 1-3: Data Ready Pulse Timing Diagram. H Timing Waveform for t DO Timing Waveform for t DIS SCK CS V IH t DO 90% SDO SDO t DIS HI-Z 10% Timing Waveform for MDAT0/1 Modulator Output OSC1/CLKI t DOMDAT MDAT0/1 FIGURE 1-4: Specific Timing Diagrams. CLKEXT PRESCALE<1:0> OSR<1:0> OSC1 OSC2 Digital Buffer Crystal Oscillator 1 0 1/ 1/Prescale MCLK AMCLK 1/4 f S ADC Sampling Rate DMCLK 1/OSR Multiplexer Clock Divider Clock Divider Clock Divider f D ADC Output Data Rate DRCLK FIGURE 1-5: MCP3901 Clock Detail. DS22192D-page Microchip Technology Inc.
9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Note: Unless otherwise indicated, AV DD = 5.0V, DV DD = 5.0V; T A = +25 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = Hz. Amplitude (db) f IN = 60 Hz f D = 3.9 ksps Point FFT OSR = 256 Dithering ON Frequency (Hz) Amplitude (db) f IN = 60 Hz fd = 3.9 ksps Point FFT OSR = 256 Dithering OFF Frequency (Hz) FIGURE 2-1: Spectral Response. FIGURE 2-4: Spectral Response. Amplitude (db) f IN = 60 Hz f D = 3.9 ksps Point FFT OSR = 256 Dithering ON Frequency (Hz) Amplitude (db) f IN = 60 Hz f D = 15.6 ksps Point FFT OSR = 64 Dithering OFF Frequency (Hz) FIGURE 2-2: Spectral Response. FIGURE 2-5: Spectral Response. Amplitude (db) f IN = 60 Hz fd = 3.9 ksps OSR = points Dithering OFF Frequency (Hz) Amplitude (db) 0-20 f IN = 60 Hz f D = 15.6 ksps Point FFT OSR = Dithering OFF Frequency (Hz) FIGURE 2-3: Spectral Response. FIGURE 2-6: Spectral Response Microchip Technology Inc. DS22192D-page 9
10 MCP3901 Note: Unless otherwise indicated, AV DD = 5.0V, DV DD = 5.0V; T A = +25 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = Hz. Amplitude (db) 0-20 f IN = 60 Hz fd = 15.6 ksps Point FFT -60 OSR = 64 Dithering ON Frequency (Hz) Spurious Free Dynamic Range (db) Dithering ON Dithering OFF Oversampling Ratio (OSR) FIGURE 2-7: Spectral Response. FIGURE 2-10: Spurious Free Dynamic Range vs. Oversampling Ratio. Amplitude (db) f IN = 60 Hz f D = 15.6 ksps Point FFT OSR = 64 Dithering ON Frequency (Hz) SINAD (db) Dithering OFF Dithering ON Oversampling Ratio (OSR) Effective Number of Bits FIGURE 2-8: Spectral Response. FIGURE 2-11: Signal-to-Noise and Distortion and Effective Number of Bits vs. Oversampling Ratio. Frequency of Occurance f IN = 60 Hz MCLK = 4 MHz OSR = 256 Dithering On Spurious Free Dynamic Range (db) SINAD (db) OSR = 256 (Dithering ON) OSR = 128 (Dithering ON) OSR = 32 OSR = Gain (V/V) FIGURE 2-9: Range Histogram. Spurious Free Dynamic FIGURE 2-12: Distortion vs. Gain. Signal-to-Noise and DS22192D-page Microchip Technology Inc.
11 Note: Unless otherwise indicated, AV DD = 5.0V, DV DD = 5.0V; T A = +25 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = Hz. SINAD (db) OSR = 256 OSR = 128 OSR = 64 OSR = Gain (V/V) Frequency of Occurance f IN = 60 Hz MCLK = 4 MHz OSR = 256 Dithering On Total Harmonic Distortion (dbc) FIGURE 2-13: Signal-to-Noise and Distortion vs. Gain (Dithering On). FIGURE 2-16: Total Harmonic Distortion Histogram (Dithering On). Total Harmonic Distortion (dbc) Dithering OFF Dithering ON Oversampling Ratio (OSR) Total Harmonic Distortion (dbc) Temperature (ºC) FIGURE 2-14: Total Harmonic Distortion vs. Oversampling Ratio. FIGURE 2-17: vs. Temperature. Total Harmonic Distortion Total Harmonic Distortion (dbc) f D = ksps SINC filter notch at Hz Input Signal Frequency (Hz) FIGURE 2-15: Total Harmonic Distortion vs. Input Signal Frequency. SINAD (db) 90 f D = ksps SINC filter notch at Hz Input Signal Frequency (Hz) FIGURE 2-18: Signal-to-Noise and Distortion vs. Input Frequency Microchip Technology Inc. DS22192D-page 11
12 MCP3901 Note: Unless otherwise indicated, AV DD = 5.0V, DV DD = 5.0V; T A = +25 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = Hz. Frequency of Occurance f IN = 60 Hz MCLK = 4 MHz OSR = 64 Dithering OFF SINAD (db) Offset Error (mv) G=8 G=16 G=1 G=32 G=2 G= Temperature (ºC) FIGURE 2-19: Signal-to-Noise and Distortion Histogram. FIGURE 2-22: Temperature. Channel 0 Offset vs. SINAD (db) Temperature (ºC) Offset Error (mv) G= G=1 0.1 G=16 0 G= G=2-0.2 G= Temperature ( C) FIGURE 2-20: Signal-to-Noise and Distortion vs. Temperature. FIGURE 2-23: Temperature. Channel 1 Offset vs. SINAD (db) Input Amplitude (dbfs) FIGURE 2-21: Signal-to-Noise and Distortion vs. Input Signal Amplitude. Offset Error (mv) Channel Channel Temperature ( C) FIGURE 2-24: Channel-to-Channel Offset Match vs. Temperature. DS22192D-page Microchip Technology Inc.
13 Note: Unless otherwise indicated, AV DD = 5.0V, DV DD = 5.0V; T A = +25 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = Hz. Positive Gain Error (% FS) G=1 G=2 G=8 G=16 G=4 G= Temperature ( C) Int. Voltage Reference (V) Power Supply (V) FIGURE 2-25: Temperature. Positive Gain Error vs. FIGURE 2-28: vs. Supply Voltage. Internal Voltage Reference Negative Gain Error (% FS) G=1 G=2 G=8 G=16 G=4 G= Temperature ( C) SINAD (db) MCLK Frequency (MHz) FIGURE 2-26: Temperature Negative Gain Error vs. FIGURE 2-29: Signal-to-Noise and Distortion vs. Master Clock (MCLK), BOOST ON. Int. Voltage Reference (V) Temperature ( C) Frequency of Occurence 8000 Channel VIN = 0V 6000 T A = +25 C Consecutive 5000 Readings bit Mode Output Code (LSB) FIGURE 2-27: vs. Temperature. Internal Voltage Reference FIGURE 2-30: Noise Histogram Microchip Technology Inc. DS22192D-page 13
14 Note: Unless otherwise indicated, AV DD = 5.0V, DV DD = 5.0 V; T A = 25 C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V IN = Hz. INL (ppm) Channel 1 OSR = 256 Dithering OFF SCK = 8 MHz Channel Input Voltage (V) I DD (ma) AI DD BOOST OFF DI DD MCLK (MHz) FIGURE 2-31: (Dithering Off). Integral Nonlinearity FIGURE 2-33: Operating Current vs. Master Clock (MCLK). INL (ppm) Channel 1 Channel 0 OSR = 256 Dithering ON SCK = 8 MHz Input Voltage (V) FIGURE 2-32: (Dithering On). Integral Nonlinearity DS22192D-page Microchip Technology Inc.
15 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Symbol PIN FUNCTION TABLE Pin No. SSOP QFN Function RESET 1 18 Master Reset Logic Input Pin DV DD 2 19 Digital Power Supply Pin AV DD 3 20 Analog Power Supply Pin CH Non-Inverting Analog Input Pin for Channel 0 CH0-5 2 Inverting Analog Input Pin for Channel 0 CH1-6 3 Inverting Analog Input Pin for Channel 1 CH Non-Inverting Analog Input Pin for Channel 1 A GND 8 5 Analog Ground Pin, Return Path for Internal Analog Circuitry REFIN+/OUT 9 6 Non-Inverting Voltage Reference Input and Internal Reference Output Pin REFIN Inverting Voltage Reference Input Pin D GND 11 8 Digital Ground Pin, Return Path for Internal Digital Circuitry MDAT Modulator Data Output Pin for Channel 1 MDAT Modulator Data Output Pin for Channel 0 DR Data Ready Signal Output Pin OSC1/CLKI Oscillator Crystal Connection Pin or External Clock Input Pin OSC Oscillator Crystal Connection Pin CS Serial Interface Chip Select Pin SCK Serial Interface Clock Pin SDO Serial Interface Data Output Pin SDI Serial Interface Data Input Pin EP 21 Exposed Thermal Pad. Must be connected to AGND. 3.1 RESET This pin is active low and places the entire chip in a Reset state when active. When RESET = 0, all registers are reset to their default value, no communication can take place and no clock is distributed inside the part. This state is equivalent to a POR state. Since the default state of the ADCs is on, the analog power consumption when RESET = 0 is equivalent to when RESET = 1. Only the digital power consumption is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. All the analog biases are enabled during a Reset so that the part is fully operational just after a RESET rising edge. This input is Schmitt triggered. 3.2 Digital V DD (DV DD ) DV DD is the power supply pin for the digital circuitry within the MCP3901. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 5.5V for specified operation. 3.3 Analog V DD (AV DD ) AV DD is the power supply pin for the analog circuitry within the MCP3901. This pin requires appropriate bypass capacitors and should be maintained to 5V ±10% for specified operation Microchip Technology Inc. DS22192D-page 15
16 3.4 ADC Differential Analog inputs (CHn+/CHn-) CH0- and CH0+, and CH1- and CH1+, are the two fully differential analog voltage inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±500 mv/gain with V REF = 2.4V. The maximum absolute voltage, with respect to AGND, for each CHn+/- input pin is ±1V with no distortion and ±6V with no breaking after continuous voltage. 3.5 Analog Ground (AGND) AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). To ensure accuracy and noise cancellation, this pin must be connected to the same ground as DGND, preferably with a star connection. If an analog ground plane is available, it is recommended that this pin be tied to this plane of the PCB. This plane should also reference all other analog circuitry in the system. 3.6 Non-Inverting Reference Input, Internal Reference Output (REFIN+/OUT) This pin is the non-inverting side of the differential voltage reference input for both ADCs or the internal voltage reference output. When VREFEXT = 1, and an external voltage reference source can be used, the internal voltage reference is disabled. When using an external differential voltage reference, it should be connected to its V REF + pin. When using an external single-ended reference, it should be connected to this pin. When VREFEXT = 0, the internal voltage reference is enabled and connected to this pin through a switch. This voltage reference has minimal drive capability, and thus, needs proper buffering and bypass capacitances (10 µf tantalum in parallel with 0.1 µf ceramic) if used as a voltage source. For optimal performance, bypass capacitances should be connected between this pin and AGND at all times, even when the internal voltage reference is used. However, these capacitors are not mandatory to ensure proper operation. 3.7 Inverting Reference Input (REFIN-) This pin is the inverting side of the differential voltage reference input for both ADCs. When using an external differential voltage reference, it should be connected to its V REF- pin. When using an external, single-ended voltage reference, or when VREFEXT = 0 (default) and using the internal voltage reference, this pin should be directly connected to AGND. 3.8 Digital Ground Connection (DGND) DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). To ensure accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection. If a digital ground plane is available, it is recommended that this pin be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other digital circuitry in the system. 3.9 Modulator Data Output Pin for Channel 1 and Channel 0 (MDAT1/MDAT0) MDAT0 and MDAT1 are the output pins for the modulator serial bitstreams of ADC Channels 0 and 1, respectively. These pins are high-impedance by default. When the MODOUT<1:0> are enabled, the modulator bitstream of the corresponding channel is present on the pin and updated at the AMCLK frequency. (See Section 5.4 Modulator Output Block for a complete description of the modulator outputs.) These pins can be directly connected to a MCU or DSP when a specific digital filtering is needed DR (Data Ready Pin) The data ready pin indicates if a new conversion result is ready to be read. The default state of this pin is high when DR_HIZN = 1 and is high-impedance when DR_HIZN = 0 (default). After each conversion is finished, a low pulse will take place on the data ready pin to indicate the conversion result is ready as an interrupt. This pulse is synchronous with the master clock and has a defined and constant width. The data ready pin is independent of the SPI interface and acts like an interrupt output. The data ready pin state is not latched and the pulse width (and period) are both determined by the MCLK frequency, over-sampling rate and internal clock prescale settings. The DR pulse width is equal to one DMCLK period and the frequency of the pulses is equal to DRCLK (see Figure 1-3). Note: This pin should not be left floating when the DR_HIZN bit is low; a 100 kω pull-up resistor connected to D VDD is recommended. DS22192D-page Microchip Technology Inc.
17 3.11 Oscillator and Master Clock Input Pins (OSC1/CLKI, OSC2) OSC1/CLKI and OSC2 provide the master clock for the device. When CLKEXT = 0 (default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. However, the clock frequency can be 1 MHz to 5 MHz without disturbing ADC accuracy. With the current boost circuit enabled, the master clock can be used up to MHz without disturbing ADC accuracy. Appropriate load capacitance should be connected to these pins for proper operation. Note: When CLKEXT = 1, the crystal oscillator is disabled, as well as the OSC2 input. The OSC1 becomes the master clock input, CLKI, the direct path for an external clock source; for example, a clock source generated by an MCU CS (Chip Select) This pin is the SPI chip select that enables the serial communication. When this pin is high, no communication can take place. A chip select falling edge initiates the serial communication and a chip select rising edge terminates the communication. No communication can take place, even when CS is low and when RESET is low. This input is Schmitt triggered SDO (Serial Data Output) This is the SPI data output pin. Data is clocked out of the device on the falling edge of SCK. This pin stays high-impedance during the first command byte. It also stays high-impedance during the whole communication for write commands, and when the CS pin is high or when the RESET pin is low. This pin is active only when a read command is processed. Each read is processed by a packet of 8 bits SDI (Serial Data Input) This is the SPI data input pin. Data is clocked into the device on the rising edge of SCK. When CS is low, this pin is used to communicate with a series of 8-bit commands. The interface is half-duplex (inputs and outputs do not happen at the same time). Each communication starts with a chip select falling edge, followed by an 8-bit command word entered through the SDI pin. Each command is either a read or a write command. Toggling SDI during a read command has no effect. This input is Schmitt triggered SCK (Serial Data Clock) This is the serial clock pin for SPI communication. Data is clocked into the device on the rising edge of SCK. Data is clocked out of the device on the falling edge of SCK. The MCP3901 interface is compatible with both SPI 0,0 and 1,1 modes. SPI modes can only be changed during a Reset. The maximum clock speed specified is 20 MHz when DV DD > 4.5V and 10 MHz otherwise. This input is Schmitt triggered Microchip Technology Inc. DS22192D-page 17
18 NOTES: DS22192D-page Microchip Technology Inc.
19 4.0 TERMINOLOGY AND FORMULAS This section defines the terms and formulas used throughout this data sheet. The following terms are defined: MCLK Master Clock AMCLK Analog Master Clock DMCLK Digital Master Clock DRCLK Data Rate Clock Oversampling Ratio (OSR) Offset Error Gain Error Integral Nonlinearity Error Signal-to-Noise Ratio (SNR) Signal-to-Noise Ratio And Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3901 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hardware Reset Mode (RESET = 0) ADC Shutdown Mode Full Shutdown Mode 4.1 MCLK Master Clock This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1 (see Figure 1-5). 4.2 AMCLK Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG1 PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two Sigma-Delta modulators. EQUATION 4-1: TABLE 4-1: Config PRE<1:0> 4.3 DMCLK Digital Master Clock This is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. This is also the sampling frequency, which is the rate when the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output (see Figure 1-5). EQUATION 4-2: AMCLK = MCLK PRESCALE MCP3901 OVERSAMPLING RATIO SETTINGS Analog Master Clock Prescale 0 0 AMCLK = MCLK/1 (default) 0 1 AMCLK = MCLK/2 1 0 AMCLK = MCLK/4 1 1 AMCLK = MCLK/8 AMCLK DMCLK = = 4 MCLK PRESCALE 4.4 DRCLK Data Rate Clock This is the output data rate (i.e., the rate at which the ADCs output new data). Each new data is signaled by a Data Ready pulse on the DR pin. This data rate is depending on the OSR and the prescaler with the following formula: EQUATION 4-3: DMCLK AMCLK MCLK DRCLK = = = OSR 4 OSR 4 OSR PRESCALE 2011 Microchip Technology Inc. DS22192D-page 19
20 Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. The following table describes the various combinations of OSR and PRESCALE, and their associated AMCLK, DMCLK and DRCLK rates. TABLE 4-2: PRE <1:0> DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE OSR <1:0> OSR AMCLK DMCLK DRCLK DRCLK (ksps) SINAD (db) ENOB (bits) MCLK/8 MCLK/32 MCLK/ MCLK/8 MCLK/32 MCLK/ MCLK/8 MCLK/32 MCLK/ MCLK/8 MCLK/32 MCLK/ MCLK/4 MCLK/16 MCLK/ MCLK/4 MCLK/16 MCLK/ MCLK/4 MCLK/16 MCLK/ MCLK/4 MCLK/16 MCLK/ MCLK/2 MCLK/8 MCLK/ MCLK/2 MCLK/8 MCLK/ MCLK/2 MCLK/8 MCLK/ MCLK/2 MCLK/8 MCLK/ MCLK MCLK/4 MCLK/ MCLK MCLK/4 MCLK/ MCLK MCLK/4 MCLK/ MCLK MCLK/4 MCLK/ Note: For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = Oversampling Ratio (OSR) The ratio of the sampling frequency to the output data rate is OSR = DMCLK/DRCLK. The default OSR is 64 or with MCLK = 4 MHz and PRESCALE = 1, AMCLK = 4 MHz, f S = 1 MHz, f D = ksps. The following bits in the CONFIG1 register are used to change the Oversampling Ratio (OSR). TABLE 4-3: CONFIG OSR<1:0> MCP3901 OVERSAMPLING RATIO SETTINGS OVERSAMPLING RATIO OSR (default) Offset Error This is the error induced by the ADC when the inputs are shorted together (V IN = 0V). The specification incorporates both PGA and ADC offset contributions. This error varies with PGA and OSR settings. The offset is different on each channel and varies from chip to chip. This offset error can easily be calibrated out by a MCU with a subtraction. The offset is specified in mv. The offset on the MCP3901 has a low temperature coefficient; see Section 2.0 Typical Performance Curves. 4.7 Gain Error This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in percent (%) compared to the ideal transfer function defined by Equation 5-3. The specification incorporates both PGA and ADC gain error contributions, but not the V REF contribution (it is measured with an external V REF ). This error varies with PGA and OSR settings. The gain error on the MCP3901 has a low temperature coefficient; see the typical performance curves for more information, Figure 2-24 and Figure DS22192D-page Microchip Technology Inc.
Two Channel Analog Front End MCP3901 Features Two synchronous sampling 16/24-bit resolution Delta-Sigma A/D Converters with proprietary multi-bit architecture 91 db SINAD, -104 dbc THD (up to 35 th harmonic),
Energy Metering IC with SPI Interface and Active Power Pulse Output Features Supports IEC 6253 International Energy Metering Specification Digital Waveform Data Access Through SPI Interface - 16-bit Dual
Atmel 8-bit and 32-bit Microcontrollers AVR127: Understanding ADC Parameters APPLICATION NOTE Introduction This application note explains the basic concepts of analog-to-digital converter (ADC) and the
TYPICAL APPLICATION V IN Multiplying DAC Has Easy -Wire Serial Interface 5V Integral Nonlinearity over Temperature.0 CLOCK DATA LOAD 5 5 6 V DD R FB STB LTC5 LTC8 LD DGND AGND pf + LT 09 V OT 5/8 TA0 INTEGRAL
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. LF411 Low Offset, Low Drift JFET Input Operational Amplifier General Description
FEATURES Charge-Balancing ADC 24 Bits, No Missing Codes 0.0015% Nonlinearity 2-Channel Programmable Gain Front End Gains from 1 to 128 1 Differential Input 1 Single-Ended Input Low-Pass Filter with Programmable
19-2235; Rev 1; 3/02 Cold-Junction-Compensated K-Thermocoupleto-Digital General Description The performs cold-junction compensation and digitizes the signal from a type-k thermocouple. The data is output
INTEGRATED CIRCUITS DATA SHEET File under Integrated Circuits, IC01 February 1991 FEATURES Low distortion 16-bit dynamic range 4 oversampling possible Single 5 V power supply No external components required
LM118/LM218/LM318 Operational Amplifiers General Description The LM118 series are precision high speed operational amplifiers designed for applications requiring wide bandwidth and high slew rate. They
16-Bit Analog-to-Digital Converter with I 2 C Interface and On-Board Reference Features 16-bit ΔΣ ADC in a SOT-23-6 package Differential Input Operation Self Calibration of Internal Offset and Gain per
For most current data sheet and other product information, visit www.burr-brown.com 12-Bit, 4-Channel Parallel Output Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES SINGLE SUPPLY: 2.7V to 5V 4-CHANNEL INPUT
The counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive approximation converter. 1 2 The idea of sampling is fully covered
www.maxim-ic.com FEATURES Temperature measurements require no external components Measures temperatures from -55 C to +125 C in 0.5 C increments. Fahrenheit equivalent is -67 F to 257 F in 0.9 F increments
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
May 2009 TLI4946 High Precision Hall Effect Latches for Industrial and Consumer Applications TLI4946K, TLI4946-2K, TLI4946-2L Datasheet Rev. 1.0 Sense and Control Edition 2009-05-04 Published by Infineon
Stereo Audio DIGITAL-TO-ANALOG CONVERTER 16 Bits, khz Sampling TM FEATURES COMPLETE STEREO DAC: Includes Digital Filter and Output Amp DYNAMIC RANGE: db MULTIPLE SAMPLING FREQUENCIES: 16kHz to khz 8X OVERSAMPLING
CONVERTERS Filters Introduction to Digitization Digital-to-Analog Converters Analog-to-Digital Converters Filters Filters are used to remove unwanted bandwidths from a signal Filter classification according
1.17 EXPERIMENT 1.2 CHARACTERIZATION OF OPAMP 1.2.1 OBJECTIVE 1. To sketch and briefly explain an operational amplifier circuit symbol and identify all terminals 2. To list the amplifier stages in a typical
Unity Power Factor LED Lamp Driver Initial Release Features Constant Output Current Large Step-Down Ratio Unity Power Factor Low Input Current Harmonic Distortion Fixed Frequency or Fixed Off-Time Operation
Analog to Digital, A/D, Digital to Analog, D/A Converters An electronic circuit to convert the analog voltage to a digital computer value Best understood by understanding Digital to Analog first. A fundamental
Programmable Single-/Dual-/Triple- Tone Gong Preliminary Data SAE 800 Bipolar IC Features Supply voltage range 2.8 V to 18 V Few external components (no electrolytic capacitor) 1 tone, 2 tones, 3 tones
High Sensitivity Receiver Applications Benefit from Unique Features in 16-bit 130Msps ADC RF IN RF BPF IF BPF LTC2208 ADC DDC/DSP LO1 ADC Driver Wireless receiver design requires extreme care in dealing
HOW TO GET 23 BITS OF EFFECTIVE RESOLUTION FROM YOUR 24-BIT CONVERTER The ADS20 and ADS2 are precision, wide dynamic range, Σ A/D converters that have 24 bits of no missing code and up to 23 bits rms of
9-; Rev ; /97 General Description The is a CMOS, -bit digital-to-analog converter (DAC) that interfaces directly with most microprocessors. On-chip input latches make the DAC load cycle interface similar
SG3524 REGULATING PULSE WIDTH MODULATORS COMPLETE PWM POWER CONTROL CIR- CUITRY UNCOMMITTED OUTPUTS FOR SINGLE- ENDED OR PUSH PULL APPLICATIONS LOW STANDBY CURRENT 8mA TYPICAL OPERATION UP TO 300KHz 1%
49% FPO PCM181 PCM181 For most current data sheet and other product information, visit www.burr-brown.com 16-Bit, Stereo, Audio ANALOG-TO-DIGITAL CONVERTER FEATURES DUAL 16-BIT MONOLITHIC Σ ADC SINGLE-ENDED
Operational Amplifiers: Part 2 Non-ideal Behavior of Feedback Amplifiers DC Errors and Large-Signal Operation by Tim J. Sobering Analog Design Engineer & Op Amp Addict Summary of Ideal Op Amp Assumptions
DS1807 Addressable Dual Audio Taper Potentiometer FEATURES Operates from 3V or 5V Power Supplies PIN ASSIGNMENT GND 1 14 V CC Ultra low power consumption A2 2 13 SCL Two digitally controlled, 65 position
16-Bit, Multi-Channel ΔΣ Analog-to-Digital Converter with I 2 C Interface and On-Board Reference Features 16-bit ΔΣ ADC with Differential Inputs: - 2 channels: MCP3426 and MCP3427-4 channels: MCP3428 Differential
FEATURES APPLICATIO S U -/6-Channel Single-Ended or 4-/-Channel Differential Inputs (LTC44/LTC4) Low Supply Current (µa, 4µA in Autosleep) Differential Input and Differential Reference with GND to Common
An9931 Unity Power Factor LED Lamp Driver Features Constant output current Large step-down ratio Unity power factor Low input current harmonic distortion Fixed frequency or fixed off-time operation Internal
Quad PLL with VCXO Quick Turn Clock Description The ICS379 QTClock TM generates up to 9 high quality, high frequency clock outputs including a reference from a low frequency pullable crystal. It is designed
CMOS Analog IC Design Page 10.5-4 NYQUIST FREQUENCY ANALOG-DIGITAL CONVERTERS The sampled nature of the ADC places a practical limit on the bandwidth of the input signal. If the sampling frequency is f
DATASHEET ICS650-44 Description The ICS650-44 is a spread spectrum clock synthesizer intended for video projector and digital TV applications. It generates three copies of an EMI optimized 50 MHz clock
DATASHEET ICS670-03 Description The ICS670-03 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. It is identical
Features Stereo Digital Volume Control Complete Digital Volume Control 2 Independent Channels Serial Control 0.5 db Step Size Wide Adjustable Range -95.5 db Attenuation +31.5 db Gain Low Distortion & Noise
DTMF Receiver Features Operating voltage: 2.5V~5.5V Minimal external components No external filter is required Low standby current (on power down mode) General Description The HT9170 series are Dual Tone
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
INTEGRATED CIRCUITS DATA SHEET power amplifier with diagnostic facility Supersedes data of March 1994 File under Integrated Circuits, IC01 1996 Jan 08 FEATURES Requires very few external components High
Specifications Document Revision 1.2, February, 2010 Copyright 2010, Measurement Computing Corporation Typical for 25 C unless otherwise specified. Specifications in italic text are guaranteed by design.
DATASHEET ICS514 Description The ICS514 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a 14.31818 MHz crystal or clock input. The name LOCO stands for
a FEATURES 10-Bit ADC with 15 s and 30 s Conversion Times Single and Four Single-Ended Analog Input Channels On-Chip Temperature Sensor: 55 C to +125 C On-Chip Track/Hold Over-Temperature Indicator Automatic
Application Note August 999 A Collection of Differential to Single-Ended Signal Conditioning Circuits for Use with the LTC00, a -Bit No Latency Σ ADC in an SO- By Kevin R. Hoskins and Derek V. Redmayne
Performance of an IF sampling ADC in receiver applications David Buchanan Staff Applications Engineer Analog Devices, Inc. Introduction The concept of direct intermediate frequency (IF) sampling is not
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. MCP411/2/3/4 Low-Cost 64-Step Volatile Digital POT Features Volatile Digital
inc. High Speed, Four Channel MOSFET Driver with Non-Inverting Outputs Features Non-inverting, four channel MOSFET driver.0ns rise and fall time 2.0A peak output source/sink current 1. to 5.0V input CMOS
LM1036 Dual DC Operated Tone/Volume/Balance Circuit General Description The LM1036 is a DC controlled tone (bass/treble), volume and balance circuit for stereo applications in car radio, TV and audio systems.
DATASHEET ICS571 Description The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques.
DATASHEET ICS680-01 Description The ICS680-01 generates four high-frequency clock outputs and a reference from a 25 MHz crystal or clock input. The device includes a low-skew, single input to four output
SG2525A SG3525A REGULATING PULSE WIDTH MODULATORS 8 TO 35 V OPERATION 5.1 V REFERENCE TRIMMED TO ± 1 % 100 Hz TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL
8-Bit Analog-to-igital Converter with I 2 C Interface and On-Board Reference Features 8-bit ΔΣ AC in a SOT-23-6 package ifferential Input Operation Self Calibration of Internal Offset and Gain Per Each
19-013; Rev 1; 10/11 0MHz to 13MHz Spread-Spectrum General Description The is a spread-spectrum clock modulator IC that reduces EMI in high clock-frequency-based, digital electronic equipment. Using an
Application Report SLAA323 JULY 2006 Oversampling the ADC12 for Higher Resolution Harman Grewal... ABSTRACT This application report describes the theory of oversampling to achieve resolutions greater than
19-652; Rev 1; 8/12 EVALUATION KIT AVAILABLE MAX1476// General Description The MAX1476// analog switches are capable of passing bipolar signals that are beyond their supply rails. These devices operate
a FEATURES Four 8-Bit DACs with Output Amplifiers Skinny 20-Pin DIP, SOIC and 20-Terminal Surface Mount Packages Microprocessor Compatible TTL/CMOS Compatible No User Trims Extended Temperature Range Operation
Precision Gain = DIFFERENTIAL AMPLIFIER FEATURES ACCURATE GAIN: ±.% max HIGH COMMON-MODE REJECTION: 8dB min NONLINEARITY:.% max EASY TO USE PLASTIC 8-PIN DIP, SO-8 SOIC PACKAGES APPLICATIONS G = DIFFERENTIAL
DATASHEET ICS7152 Description The ICS7152-01, -02, -11, and -12 are clock generators for EMI (Electro Magnetic Interference) reduction (see below for frequency ranges and multiplier ratios). Spectral peaks
Section 3 Sensor to ADC Design Example 3-1 This section describes the design of a sensor to ADC system. The sensor measures temperature, and the measurement is interfaced into an ADC selected by the systems
CA73, CA73C Data Sheet April 1999 File Number 788. Voltage Regulators Adjustable from V to 37V at Output Currents Up to 1mA without External Pass Transistors The CA73 and CA73C are silicon monolithic integrated
18 CHANNELS LED DRIVER GENERAL DESCRIPTION IS31FL3218 is comprised of 18 constant current channels each with independent PWM control, designed for driving LEDs. The output current of each channel can be
Features Inputs/Outputs Accepts two differential or single-ended inputs LVPECL, LVDS, CML, HCSL, LVCMOS Glitch-free switching of references On-chip input termination and biasing for AC coupled inputs Six
Rev 1; 3/0 Spread-Spectrum Crystal Multiplier General Description The is a low-jitter, crystal-based clock generator with an integrated phase-locked loop (PLL) to generate spread-spectrum clock outputs
19-2219; Rev 0; 2/02 Thermistor-to-Digital Converter General Description The converts an external thermistor s temperature-dependent resistance directly into digital form. The thermistor and an external
CMOS Phase Lock Loop General Description The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and
FAN3850T Microphone Pre-Amplifier with Temperature Compensation and Digital Output Features Optimized for Mobile Handset and Notebook PC Microphone Applications Accepts Input from Electret Condenser Microphones
A B LOW NOISE JFET QUAD OPERATIONAL AMPLIFIERS WIDE COMMONMODE (UP TO V + CC ) AND DIFFERENTIAL VOLTAGE RANGE LOW INPUT BIAS AND OFFSET CURRENT LOW NOISE e n = 15nV/ Hz (typ) OUTPUT SHORTCIRCUIT PROTECTION
AUDIO MODULATED MATRIX LED DRIVER GENERAL DESCRIPTION FEATURES December 2011 IS31FL3728 is a general purpose 8 8 LED matrix driver which features an audio frequency equalizer (EQ) mode or a general LED
LMS5214 80mA, Low Dropout Voltage Regulator with Auto Discharge Function in SC70 General Description Features The LMS5214 is a µcap, low dropout voltage regulator with very low quiescent current, 110µA
1 CIRCUIT DESIGN If not using one of First Sensors ZBXYA interface boards for sensor control and conditioning, this section describes the basic building blocks required to create an interface circuit Before
Quad, High Voltage, Amplifier Array Features Four independent high voltage amplifiers 190V output swing 9.0V/µs typical output slew rate Fixed gain of 66.7V/V High value internal feedback resistors Very
SIM Power Supply and Level Translator FEATURES n SIM Power Supply: 1.8V/3V at 50mA n Input Voltage Range: 3V to 6V n Controller Voltage Range: 1.2V to 4.4V n 14kV ESD On All SIM Contact Pins n Meets All
DESCRIPTION PT8211 is a dual channel, 16 bit Digital-to-Analog Converter IC utilizing CMOS technology specially designed for the digital audio applications. The internal conversion architecture is based
CMOS Analog IC Design - Chapter 10 Page 10.0-5 BLOCK DIAGRAM OF A DIGITAL-ANALOG CONVERTER b 1 is the most significant bit (MSB) The MSB is the bit that has the most (largest) influence on the analog output
12-Bit, 8-Channel Sampling ANALOG-TO-DIGITAL CONVERTER with I 2 C Interface NOVEMBER 2001 FEATURES EIGHT CHANNEL MULTIPLEXER 50kHz SAMPLING RATE NO MISSING CODES 2.7V TO 5V OPERATION INTERNAL 2.5V REFERENCE
Data Sheet FEATURES Fast throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low power at maximum throughput rates 5.4 mw maximum at 870 ksps with 3 V supplies 12.5 mw maximum at 1 MSPS with 5
End of Life. Last Available Purchase Date is 31-Dec-2014 Si9120 Universal Input Switchmode Controller FEATURES 10- to 450-V Input Range Current-Mode Control 125-mA Output Drive Internal Start-Up Circuit
LF412 Low Offset Low Drift Dual JFET Input Operational Amplifier General Description These devices are low cost high speed JFET input operational amplifiers with very low input offset voltage and guaranteed
DATASHEET 1 TO 4 CLOCK BUFFER ICS551 Description The ICS551 is a low cost, high-speed single input to four output clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest cost, small clock
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier General Description These devices are low cost high speed dual JFET input operational amplifiers with an internally trimmed input offset voltage
Use and Application of Output Limiting Amplifiers (HFA111, HFA110, HFA11) Application Note November 1996 AN96 Introduction Amplifiers with internal voltage clamps, also known as limiting amplifiers, have