Timing Errors and Jitter

 To view this video please enable JavaScript, and consider upgrading to a web browser that supports HTML5 video
Save this PDF as:

Size: px
Start display at page:

Transcription

1 Timing Errors and Jitter Background Mike Story In a sampled (digital) system, samples have to be accurate in level and time. The digital system uses the two bits of information the signal was this big at this instant and does subsequent maths on it. In most digital systems, the assumption is that samples are taken on a regular basis, controlled by a clock. They are exactly equally spaced in time. This is reflected in the maths, which is written in terms of z 0, z -, z -2, etc with z representing a sample period. To do DSP, we do not need all samples evenly spaced but the maths is best left to someone else if they are not. In any case, modern ADCs are best suited to producing a regular stream of evenly spaced samples. As in all things where we want perfection there are sources of error. There are small variations in timing for the reference points at which the samples are supposedly taken, and there are in addition much larger (although less important) errors in the timing of when the samples, or subsequently processed samples, are presented to the outside world. The names for these things are not all well established in DSP literature, so the terms used here are given below. In some literature, the terms jitter is used to cover all these effects but this should be treated with caution. The errors in the reference point are either (a) random (like noise) or (b) related to the signal. The latter are not often referred to in the literature, but are probably the single most performance limiting aspect of ADCs and DACs as the frequency goes up. Their effect shows up in non-linearity measurements. The third effect (c) is a variation in when a data bit becomes valid, and is mainly of concern to digital designers. It can be a problem for conversion of the digital signal back to analogue. We (dcs) refer to these types of timing variations as: (a) Jitter (b) Signal related timing error (SRTE) (c) Data jitter Jitter is often quoted as being the cause of some audible problem when no other explanation is clearly forthcoming. In the author s view, this is not always correct. Jitter certainly causes measurable effects, and these are as audible as the measurement would suggest. It also would appear to cause some effects that are rather hard to explain 2 but it is probably not the cause of all the problems ascribed to it. There are a number of methods of measuring jitter. Because we are often looking in the psec region, this is not easy to see on a scope, so test methods that measure it by implication are sometimes used. The user should be careful to check that these methods really are measuring jitter, and not something else. Scale of the Problem Jitter causes a problem when analogue source material is first converted to digital because for one reason or another the sample is taken at slightly the wrong instant. It can also cause a problem when a digital signal is turned back to analogue, because the assumption that the signal was this big for one sample period breaks down (the DAC gets this big right but it gets the sample period wrong). In between, as long as the equipments are synchronous, data jitter is only a problem if it causes the receiving bit of equipment to make an error and 2 with dcs Ltd, Mull House, Great Chesterford Court, Great Chesterford, Saffron Walden, UK for example, in one demonstration using the same analogue source material, the same ADC and the same DAC, but changing just the digital interface used between them, one particular backing vocal dramatically changed in prominence Page of 6 Issue 2

2 if it causes build up of low frequency jitter such that it cannot be removed by the final DAC. Such a build up can be completely eliminated by the distribution and use of a master clock. For asynchronous links (with asynchronous sample rate converters on the input of the receiving equipment), data jitter causes additional jitter to be processed into the data domain, irrevocably. Asynchronous interfacing should be used with care. For both (a) and (b) a small timing error δt causes a problem only when a signal is slewing. For an ADC, with an input signal slewing at δv/δt then the error will be δv. For a DAC, which puts out digital values, the error will be related to the difference between two consecutive samples as: δt/t s (A n -A n- ) where t s is the sample period. In both cases, the effect of the jitter δt increases as the signal frequency and the signal amplitude increases. For random jitter (a), a khz sine wave with nsec rms of jitter will cause an amplitude modulated noise signal with rms in the big bits of at 04dB relative to the khz. The overall rms (taking into account the peaks and troughs of the envelope) is approximately 08dB relative to the khz sine. See figure for an exaggerated example. Random Jitter.5 Signal Output with Jitter Error rms effect in noise measurement Signal Amplitude Jitter Amplitude (expanded) Time in usecs Figure For (b), SRTE, where the timing variation is related to the signal, and synchronous to it, the effect is distortion. Figure 2 shows khz sine wave with a large SRTE that is proportional to slew rate (the commonest sort). Note that the peak amplitude of the signal is not affected, but that the shape is the distortion is phase distortion, rather than amplitude distortion. In reality, SRTE with a peak value of nsec, and whose value is proportional to slew rate, will produce a 2 nd harmonic at 0dB relative to a khz sine, and 90dB relative to a 0 khz sine. For any circuitry using a sample/hold (residue converters or switched capacitor oversampling converters) this effect is important. Although not strictly of relevance to audio, for fast circuitry the state of the art for this parameter is about psec, and this limits the accuracy with which a 300 MHz signal can be digitised to about 60dB. Page 2 of 6 Issue 2

3 Signal Related Timing Error (SRTE).5 Signal Output with SRTE SRTE Error Signal Amplitude SRTE Amplitude (expanded) Time in usecs Figure 2 SRTE proportional to slew rate Data jitter (c) depends on the hardware used, and is a function of both the source hardware and the interconnect (cabling). The effect can be minimised at source by re-clocking output data just before the output drivers, and making the output drivers high bandwidth. After this, the interconnect bandwidth must not degrade the waveforms. In practice, degradation of waveforms by long cable runs is probably the most important effect. Figure 3 shows the effect of 20m of twisted pair cabling on a double speed AES3 signal for 96 ks/s use, with the top trace the waveform at source prior to balanced pair transmission, and the bottom trace the waveform after the differential receiver at the end of the cable run. The scope is triggered from the transmitted data, and due to cable delays, the transitions are not the same. Data jitter is nearly 5 nsecs p-p. Figure 3 Data Jitter due to cabling see text Page 3 of 6 Issue 2

4 Where Does Jitter Come From? (Random) jitter originates in clock circuitry. Crystal based clocks (XCO s, VCXO s) generally have the lowest jitter but they still have some. Manufacturers plot the spectrum of crystal oscillators in terms of offset from the nominal frequency, as in figure 4 (solid line). They generally refer to this as the phase noise plot. We can turn this information into jitter as follows 3 : (a) Assume that half the power in the area of the spectrum away from the nominal frequency is due to phase noise (phase errors, rather than amplitude errors) in the oscillator output. (b) RMS up the phase errors, as one does for ordinary noise, to get rms radians error (for example, the error sums up to radians rms from 0Hz to MHz offset) (c) Use the oscillator centre frequency to turn radians into secs (for example, for a MHz oscillator radian 6.48 nsecs, so our example has 3 psecs rms jitter from Hz to MHz offset. Phase Noise from Good VCXO psecs Phase Noise rel Fundamental in Hz psecs Offset Noise in Hz jitter for decade 0.3 psecs 0 0. Integrated Jitter, for decade, in psecs psecs Offset from Fundamental Figure 4 Figure 4 also shows what parts of the phase noise spectrum contribute to jitter. It shows some interesting points: The phase noise in the oscillator close to the nominal frequency (close to carrier phase noise) makes a big contribution to the jitter. It is likely that this jitter does not have much perceived effect on audio, because to detect it, our ears would have to have higher Q detection mechanisms than a crystal. In fact, the ears frequency discriminating mechanism has a Q of less than 0, whereas crystals have a Q of 0,000 upwards. By khz, there is very little contribution being made However, above this as we approach the thermal noise floor of around 50dBc to -60dBc, the effect builds up again by the time noise is integrated up over many MHz. Clock circuitry in digital equipment in inherently quite wide bandwidth, and we must allow for this in our integration. There are other sources of jitter inside equipment, that may contribute substantially more than the VCXO. Typically, these might be power supply noise causing variation in logic level See, for example, Phase-Locked Loop Circuit Design Dan H.Wolaver, published by Prentice-Hall Inc, 99. ISBN Page 4 of 6 Issue 2

5 switch points. With a slow edge speed, the variation will cause small timing variations in the apparent switching instant - jitter. Data Jitter and Clock Recovery In the absence of a distributed master clock, items in a digital audio chain have to recover their clocks from the data stream they are fed. They will generally do this by locking a local phase locked loop (PLL) to the incoming data stream, and to keep data transfers inside the equipment synchronous, this locked clock is then used internally. The PLL usually locks to the edges in the incoming data stream, because these are convenient timing points. The incoming edges will have jitter from their controlling oscillator (psecs) and additional data jitter the latter often of several nsecs. The PLL has to filter this out, which it does by effectively averaging over many incoming edges. The averaging is performed by making the bandwidth of the oscillator control loop small. For example, a control loop bandwidth of Hz effectively averages over a period of /2π seconds. For a PLL locking to a 48kS/s AES3 data stream, and looking for sync codes (these occur at 96kHz) averaging is effectively over about 5,000 edges, which will reduce the data jitter by 5,000 times (about 24 times) if the spectrum of the jitter is flat. AES3 at 48 ks/s allows a peak to peak jitter of 80 nsecs on a data edge (it is usually better than this) which is equivalent to about 3 nsecs rms jitter. Reducing this by 24 times (above) will drop it to around 0 psecs rms. In practice, things are better than this: the spectrum of the jitter is not flat, but is slightly noise shaped, so the averaging works better than expected, and the data jitter is not usually as bad as the spec allows, although long cable runs will make it bad again. Use of a FIFO to store incoming data works in exactly the same way, by allowing a very low bandwidth in the control loop of the PLL used. It does not eliminate jitter it is just easier to achieve low control loop bandwidths. Note that for this to offer lower bandwidths than a conventional analogue PLL, and for the FIFO to operate half full, FIFO depths of 64K or more are needed. If this method of synchronising items in a digital audio chain is used (locking to the previous equipment rather than a distributed master clock), then it becomes important to avoid jitter build up in the area of a few Hz around the centre frequencies of the various oscillators used in the chain. Data Jitter and Asynchronous Sample Rate Converters Asynchronous sample rate converters can respond to data jitter and process it into the signal, irrevocably. For this reason they should be used with care, and if they have to be used, should be used with low data jitter sources with short cable runs. Optical Interfaces Optical interfaces are sometimes thought to have desirable properties, and occasionally one sees this extended to having some low jitter property. Optical interfaces certainly do offer very good immunity to electrical interference, and also very wide bandwidth to an optical signal that has been injected into them. However, the problem is usually that: the optical power that can be injected into them is limited, the bandwidth with which the signal can be injected is limited, or the transmitter is expensive and losses at connectors build up rapidly, so that the optical signal reaching the far end is small if more than a few connectors are involved Page 5 of 6 Issue 2

6 The signal reaching the far end is usually sufficiently small that the receiver has to carefully control (minimise) its bandwidth to get adequate signal/noise ratio. Minimising bandwidth is just the mechanism that increases data jitter, because it reduces the slew rate associated with a logic transition. The position can be improved if laser diodes (rather than the more common LEDs) are used to inject signal into the link, because more signal can be injected into the link but laser diodes are very expensive. Optical links are fine for telecomms applications, where links cover large distances uninterrupted (no connector losses) and expensive transmitters can be used. They are also of value where the high bandwidth of the link makes the cost of a high bandwidth driver (and receiver) economic for example, some multi-channel applications. For the relatively short links used in two channel audio, the benefits are less clear. If low jitter is sought, we recommend that optical interfaces should be minimised or avoided. Page 6 of 6 Issue 2

CLOCK AND SYNCHRONIZATION IN SYSTEM 6000

By Christian G. Frandsen Introduction This document will discuss the clock, synchronization and interface design of TC System 6000 and deal with several of the factors that must be considered when using

Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D.

Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D. Abstract: The definition of a bit period, or unit interval, is much more complicated than it looks. If it were just the reciprocal of the data

GSM/EDGE Output RF Spectrum on the V93000 Joe Kelly and Max Seminario, Verigy

GSM/EDGE Output RF Spectrum on the V93000 Joe Kelly and Max Seminario, Verigy Introduction A key transmitter measurement for GSM and EDGE is the Output RF Spectrum, or ORFS. The basis of this measurement

Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP

Department of Electrical and Computer Engineering Ben-Gurion University of the Negev LAB 1 - Introduction to USRP - 1-1 Introduction In this lab you will use software reconfigurable RF hardware from National

Frequency Shift Dither for Analogue to Digital Converters

Frequency Shift Dither for Analogue to Digital Converters Authors: Cornelis Jan Kikkert Associate Professor Head of Electrical and Computer Engineering Townsville, Queensland, 4811 Phone 07-47814259 Fax

The counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive

The counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive approximation converter. 1 2 The idea of sampling is fully covered

DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS

DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS U. Pogliano, B. Trinchera, G.C. Bosco and D. Serazio INRIM Istituto Nazionale di Ricerca Metrologica Torino (Italia)

QAM Demodulation. Performance Conclusion. o o o o o. (Nyquist shaping, Clock & Carrier Recovery, AGC, Adaptive Equaliser) o o. Wireless Communications

0 QAM Demodulation o o o o o Application area What is QAM? What are QAM Demodulation Functions? General block diagram of QAM demodulator Explanation of the main function (Nyquist shaping, Clock & Carrier

Basics of Digital Recording

Basics of Digital Recording CONVERTING SOUND INTO NUMBERS In a digital recording system, sound is stored and manipulated as a stream of discrete numbers, each number representing the air pressure at a

RF Network Analyzer Basics

RF Network Analyzer Basics A tutorial, information and overview about the basics of the RF Network Analyzer. What is a Network Analyzer and how to use them, to include the Scalar Network Analyzer (SNA),

Non-Data Aided Carrier Offset Compensation for SDR Implementation

Non-Data Aided Carrier Offset Compensation for SDR Implementation Anders Riis Jensen 1, Niels Terp Kjeldgaard Jørgensen 1 Kim Laugesen 1, Yannick Le Moullec 1,2 1 Department of Electronic Systems, 2 Center

CTA300. Communication Trainer Analog RELATED PRODUCTS. Communication Trainer kit

Communication Trainer kit Communication Trainer RELATED PRODUCTS v Digital Communication Trainers v Optical Fibers Communication Trainers v Digital and Communication Trainers v Communication Electronic

University of Pennsylvania Department of Electrical and Systems Engineering ESE06: Electrical Circuits and Systems II Lab Amplitude Modulated Radio Frequency Transmission System Mini-Project Part : Receiver

VCO Phase noise. Characterizing Phase Noise

VCO Phase noise Characterizing Phase Noise The term phase noise is widely used for describing short term random frequency fluctuations of a signal. Frequency stability is a measure of the degree to which

Loop Bandwidth and Clock Data Recovery (CDR) in Oscilloscope Measurements. Application Note 1304-6

Loop Bandwidth and Clock Data Recovery (CDR) in Oscilloscope Measurements Application Note 1304-6 Abstract Time domain measurements are only as accurate as the trigger signal used to acquire them. Often

Application Note Noise Frequently Asked Questions

: What is? is a random signal inherent in all physical components. It directly limits the detection and processing of all information. The common form of noise is white Gaussian due to the many random

Introduction 1 Block diagram 1

Electric Druid VCLFO Introduction 1 Block diagram 1 Features 2 Fastest LFO frequency of around 12.8Hz 2 Slowest LFO frequency of around 0.05Hz 2 10-bit LFO output resolution 2 19.5KHz sample output rate

Optimizing VCO PLL Evaluations & PLL Synthesizer Designs

Optimizing VCO PLL Evaluations & PLL Synthesizer Designs Today s mobile communications systems demand higher communication quality, higher data rates, higher operation, and more channels per unit bandwidth.

Introduction to Digital Audio

Introduction to Digital Audio Before the development of high-speed, low-cost digital computers and analog-to-digital conversion circuits, all recording and manipulation of sound was done using analog techniques.

The Phase Modulator In NBFM Voice Communication Systems

The Phase Modulator In NBFM Voice Communication Systems Virgil Leenerts 8 March 5 The phase modulator has been a point of discussion as to why it is used and not a frequency modulator in what are called

Modification Details.

Front end receiver modification for DRM: AKD Target Communications receiver. Model HF3. Summary. The receiver was modified and capable of receiving DRM, but performance was limited by the phase noise from

PCM Encoding and Decoding:

PCM Encoding and Decoding: Aim: Introduction to PCM encoding and decoding. Introduction: PCM Encoding: The input to the PCM ENCODER module is an analog message. This must be constrained to a defined bandwidth

Silicon Laboratories, Inc. Rev 1.0 1

Clock Division with Jitter and Phase Noise Measurements Introduction As clock speeds and communication channels run at ever higher frequencies, accurate jitter and phase noise measurements become more

Understand the effects of clock jitter and phase noise on sampled systems A s higher resolution data converters that can

designfeature By Brad Brannon, Analog Devices Inc MUCH OF YOUR SYSTEM S PERFORMANCE DEPENDS ON JITTER SPECIFICATIONS, SO CAREFUL ASSESSMENT IS CRITICAL. Understand the effects of clock jitter and phase

Achieving New Levels of Channel Density in Downstream Cable Transmitter Systems: RF DACs Deliver Smaller Size and Lower Power Consumption

Achieving New Levels of Channel Density in Downstream Cable Transmitter Systems: RF DACs Deliver Smaller Size and Lower Power Consumption Introduction By: Analog Devices, Inc. (ADI) Daniel E. Fague, Applications

CONVERTERS. Filters Introduction to Digitization Digital-to-Analog Converters Analog-to-Digital Converters

CONVERTERS Filters Introduction to Digitization Digital-to-Analog Converters Analog-to-Digital Converters Filters Filters are used to remove unwanted bandwidths from a signal Filter classification according

Simplifying System Design Using the CS4350 PLL DAC

Simplifying System Design Using the CS4350 PLL 1. INTRODUCTION Typical Digital to Analog Converters (s) require a high-speed Master Clock to clock their digital filters and modulators, as well as some

Optical Fibres. Introduction. Safety precautions. For your safety. For the safety of the apparatus

Please do not remove this manual from from the lab. It is available at www.cm.ph.bham.ac.uk/y2lab Optics Introduction Optical fibres are widely used for transmitting data at high speeds. In this experiment,

Experiment # (4) AM Demodulator

Islamic University of Gaza Faculty of Engineering Electrical Department Experiment # (4) AM Demodulator Communications Engineering I (Lab.) Prepared by: Eng. Omar A. Qarmout Eng. Mohammed K. Abu Foul Experiment

RF Measurements Using a Modular Digitizer

RF Measurements Using a Modular Digitizer Modern modular digitizers, like the Spectrum M4i series PCIe digitizers, offer greater bandwidth and higher resolution at any given bandwidth than ever before.

Voice---is analog in character and moves in the form of waves. 3-important wave-characteristics:

Voice Transmission --Basic Concepts-- Voice---is analog in character and moves in the form of waves. 3-important wave-characteristics: Amplitude Frequency Phase Voice Digitization in the POTS Traditional

Ultrasound Distance Measurement

Final Project Report E3390 Electronic Circuits Design Lab Ultrasound Distance Measurement Yiting Feng Izel Niyage Asif Quyyum Submitted in partial fulfillment of the requirements for the Bachelor of Science

W a d i a D i g i t a l

Wadia Decoding Computer Overview A Definition What is a Decoding Computer? The Wadia Decoding Computer is a small form factor digital-to-analog converter with digital pre-amplifier capabilities. It is

ANALYZER BASICS WHAT IS AN FFT SPECTRUM ANALYZER? 2-1

WHAT IS AN FFT SPECTRUM ANALYZER? ANALYZER BASICS The SR760 FFT Spectrum Analyzer takes a time varying input signal, like you would see on an oscilloscope trace, and computes its frequency spectrum. Fourier's

T = 1 f. Phase. Measure of relative position in time within a single period of a signal For a periodic signal f(t), phase is fractional part t p

Data Transmission Concepts and terminology Transmission terminology Transmission from transmitter to receiver goes over some transmission medium using electromagnetic waves Guided media. Waves are guided

DAC Digital To Analog Converter

DAC Digital To Analog Converter DAC Digital To Analog Converter Highlights XMC4000 provides two digital to analog converters. Each can output one analog value. Additional multiple analog waves can be generated

Precision Fully Differential Op Amp Drives High Resolution ADCs at Low Power

Precision Fully Differential Op Amp Drives High Resolution ADCs at Low Power Kris Lokere The op amp produces differential outputs, making it ideal for processing fully differential analog signals or taking

Computer Networks and Internets, 5e Chapter 6 Information Sources and Signals. Introduction

Computer Networks and Internets, 5e Chapter 6 Information Sources and Signals Modified from the lecture slides of Lami Kaya (LKaya@ieee.org) for use CECS 474, Fall 2008. 2009 Pearson Education Inc., Upper

USB 3.0 CDR Model White Paper Revision 0.5

USB 3.0 CDR Model White Paper Revision 0.5 January 15, 2009 INTELLECTUAL PROPERTY DISCLAIMER THIS WHITE PAPER IS PROVIDED TO YOU AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,

EECC694 - Shaaban. Transmission Channel

The Physical Layer: Data Transmission Basics Encode data as energy at the data (information) source and transmit the encoded energy using transmitter hardware: Possible Energy Forms: Electrical, light,

Jitter Transfer Functions in Minutes

Jitter Transfer Functions in Minutes In this paper, we use the SV1C Personalized SerDes Tester to rapidly develop and execute PLL Jitter transfer function measurements. We leverage the integrated nature

LEVERAGING FPGA AND CPLD DIGITAL LOGIC TO IMPLEMENT ANALOG TO DIGITAL CONVERTERS

LEVERAGING FPGA AND CPLD DIGITAL LOGIC TO IMPLEMENT ANALOG TO DIGITAL CONVERTERS March 2010 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com

Taking the Mystery out of the Infamous Formula, "SNR = 6.02N + 1.76dB," and Why You Should Care. by Walt Kester

ITRODUCTIO Taking the Mystery out of the Infamous Formula, "SR = 6.0 + 1.76dB," and Why You Should Care by Walt Kester MT-001 TUTORIAL You don't have to deal with ADCs or DACs for long before running across

Multi-Carrier GSM with State of the Art ADC technology

Multi-Carrier GSM with State of the Art ADC technology Analog Devices, October 2002 revised August 29, 2005, May 1, 2006, May 10, 2006, November 30, 2006, June 19, 2007, October 3, 2007, November 12, 2007

Improving high-end active speaker performance using digital active crossover filters

Improving high-end active speaker performance using digital active crossover filters Dave Brotton - May 21, 2013 Consumer requirement for fewer wires connecting their home entertainment systems is driving

Introduction to Receivers Purpose: translate RF signals to baseband Shift frequency Amplify Filter Demodulate Why is this a challenge? Interference (selectivity, images and distortion) Large dynamic range

Managing High-Speed Clocks

Managing High-Speed s & Greg Steinke Director, Component Applications Managing High-Speed s Higher System Performance Requires Innovative ing Schemes What Are The Possibilities? High-Speed ing Schemes

Harmonics and Noise in Photovoltaic (PV) Inverter and the Mitigation Strategies

Soonwook Hong, Ph. D. Michael Zuercher Martinson Harmonics and Noise in Photovoltaic (PV) Inverter and the Mitigation Strategies 1. Introduction PV inverters use semiconductor devices to transform the

AN-756 APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com

APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com Sampled Systems and the Effects of Clock Phase Noise and Jitter by Brad Brannon

AN-837 APPLICATION NOTE

APPLICATION NOTE One Technology Way P.O. Box 916 Norwood, MA 262-916, U.S.A. Tel: 781.329.47 Fax: 781.461.3113 www.analog.com DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance

HD Radio FM Transmission System Specifications

HD Radio FM Transmission System Specifications Rev. E January 30, 2008 Doc. No. SY_SSS_1026s TRADEMARKS The ibiquity Digital logo and ibiquity Digital are registered trademarks of ibiquity Digital Corporation.

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

DAC-R. Digital to Analogue Converter

DAC-R Digital to Analogue Converter Contents Introduction 1 Technology 2 Front panel indicators & operation 3 Back panel - inputs and outputs 4 In use - Digital output & optical inputs 5 Filter settings

Application Note: Spread Spectrum Oscillators Reduce EMI for High Speed Digital Systems

Application Note: Spread Spectrum Oscillators Reduce EMI for High Speed Digital Systems Introduction to Electro-magnetic Interference Design engineers seek to minimize harmful interference between components,

155 Mb/s Fiber Optic Light to Logic Receivers for OC3/STM1

155 Mb/s Fiber Optic Light to Logic Receivers for OC3/STM1 Application Note 1125 RCV1551, RGR1551 Introduction This application note details the operation and usage of the RCV1551 and RGR1551 Light to

INTRODUCTION TO COMMUNICATION SYSTEMS AND TRANSMISSION MEDIA

COMM.ENG INTRODUCTION TO COMMUNICATION SYSTEMS AND TRANSMISSION MEDIA 9/6/2014 LECTURES 1 Objectives To give a background on Communication system components and channels (media) A distinction between analogue

Lab 5 Getting started with analog-digital conversion

Lab 5 Getting started with analog-digital conversion Achievements in this experiment Practical knowledge of coding of an analog signal into a train of digital codewords in binary format using pulse code

Convention Paper 5694

Audio Engineering Society Convention Paper 5694 Presented at the 113th Convention 2002 October 5 8 Los Angeles, California, USA This convention paper has been reproduced from the author's advance manuscript,

The Future of Multi-Clock Systems

NEL FREQUENCY CONTROLS, INC. 357 Beloit Street P.O. Box 457 Burlington,WI 53105-0457 Phone:262/763-3591 FAX:262/763-2881 Web Site: www.nelfc.com Internet: sales@nelfc.com The Future of Multi-Clock Systems

High Sensitivity Receiver Applications Benefit from Unique Features in 16-bit 130Msps ADC

High Sensitivity Receiver Applications Benefit from Unique Features in 16-bit 130Msps ADC RF IN RF BPF IF BPF LTC2208 ADC DDC/DSP LO1 ADC Driver Wireless receiver design requires extreme care in dealing

The front end of the receiver performs the frequency translation, channel selection and amplification of the signal.

Many receivers must be capable of handling a very wide range of signal powers at the input while still producing the correct output. This must be done in the presence of noise and interference which occasionally

Analog Representations of Sound

Analog Representations of Sound Magnified phonograph grooves, viewed from above: The shape of the grooves encodes the continuously varying audio signal. Analog to Digital Recording Chain ADC Microphone

The Boonton USB Peak Power Sensor, Wi-Fi ac Signals and the ETSI EN Standard

Application Note The Boonton 55006 USB Peak Power Sensor, Wi-Fi 802.11ac Signals and the ETSI EN 300 328 Standard Stephen Shaw Applications Engineer, Boonton Electronics Abstract This application note

Use and Application of Output Limiting Amplifiers (HFA1115, HFA1130, HFA1135)

Use and Application of Output Limiting Amplifiers (HFA111, HFA110, HFA11) Application Note November 1996 AN96 Introduction Amplifiers with internal voltage clamps, also known as limiting amplifiers, have

BPSK - BINARY PHASE SHIFT KEYING

BPSK - BINARY PHASE SHIFT KEYING PREPARATION... 70 generation of BPSK... 70 bandlimiting... 71 BPSK demodulation... 72 phase ambiguity...72 EXPERIMENT... 73 the BPSK generator... 73 BPSK demodulator...

Title: Low EMI Spread Spectrum Clock Oscillators

Title: Low EMI oscillators Date: March 3, 24 TN No.: TN-2 Page 1 of 1 Background Title: Low EMI Spread Spectrum Clock Oscillators Traditional ways of dealing with EMI (Electronic Magnetic Interference)

FREQUENCY RESPONSE OF AN AUDIO AMPLIFIER

2014 Amplifier - 1 FREQUENCY RESPONSE OF AN AUDIO AMPLIFIER The objectives of this experiment are: To understand the concept of HI-FI audio equipment To generate a frequency response curve for an audio

Abstract. Cycle Domain Simulator for Phase-Locked Loops

Abstract Cycle Domain Simulator for Phase-Locked Loops Norman James December 1999 As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks

Clocks Basics in 10 Minutes or Less. Edgar Pineda Field Applications Engineer Arrow Components Mexico

Clocks Basics in 10 Minutes or Less Edgar Pineda Field Applications Engineer Arrow Components Mexico Presentation Overview Introduction to Clocks Clock Functions Clock Parameters Common Applications Summary

Low Noise, Single Supply, Electret Microphone Amplifier Design for Distant Acoustic Signals

Low Noise, Single Supply, Electret Microphone Amplifier Design for Distant Acoustic Signals Donald J. VanderLaan November 26, 2008 Abstract. Modern day electronics are often battery powered, forcing the

Clock Jitter Definitions and Measurement Methods

January 2014 Clock Jitter Definitions and Measurement Methods 1 Introduction Jitter is the timing variations of a set of signal edges from their ideal values. Jitters in clock signals are typically caused

Analog to Digital, A/D, Digital to Analog, D/A Converters. An electronic circuit to convert the analog voltage to a digital computer value

Analog to Digital, A/D, Digital to Analog, D/A Converters An electronic circuit to convert the analog voltage to a digital computer value Best understood by understanding Digital to Analog first. A fundamental

11. High-Speed Differential Interfaces in Cyclone II Devices

11. High-Speed Differential Interfaces in Cyclone II Devices CII51011-2.2 Introduction From high-speed backplane applications to high-end switch boxes, low-voltage differential signaling (LVDS) is the

Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer

Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer Hermann Ruckerbauer EKH - EyeKnowHow 94469 Deggendorf, Germany Hermann.Ruckerbauer@EyeKnowHow.de Agenda 1) PCI-Express Clocking

FREQUENCY RESPONSE ANALYZERS

FREQUENCY RESPONSE ANALYZERS Dynamic Response Analyzers Servo analyzers When you need to stabilize feedback loops to measure hardware characteristics to measure system response BAFCO, INC. 717 Mearns Road

The Need for Speed and its impact on Sync. WSTS 2015 Nigel Hardy

The Need for Speed and its impact on Sync. WSTS 2015 Nigel Hardy 1 The need for Speed and its impact on Sync. Contents The requirements for speed, high h dt data rates, increased dbandwidth The impact

Implementation of Digital Signal Processing: Some Background on GFSK Modulation

Implementation of Digital Signal Processing: Some Background on GFSK Modulation Sabih H. Gerez University of Twente, Department of Electrical Engineering s.h.gerez@utwente.nl Version 4 (February 7, 2013)

NATIONAL CABLE TELEVISION ASSOCIATION ANNUAL CONVENTION CHICAGO, ILLINOIS

121 NATIONAL CABLE TELEVISION ASSOCIATION ANNUAL CONVENTION CHICAGO, ILLINOIS JUNE' 1970 PHASE LOCK APPLICATIONS IN CATV SYSTEMS I. Switzer, P. Eng., Chief Engineer, Maclean-Hunter Cable TV Limited, 27

MSB MODULATION DOUBLES CABLE TV CAPACITY Harold R. Walker and Bohdan Stryzak Pegasus Data Systems ( 5/12/06) pegasusdat@aol.com

MSB MODULATION DOUBLES CABLE TV CAPACITY Harold R. Walker and Bohdan Stryzak Pegasus Data Systems ( 5/12/06) pegasusdat@aol.com Abstract: Ultra Narrow Band Modulation ( Minimum Sideband Modulation ) makes

DDX 7000 & 8003. Digital Partial Discharge Detectors FEATURES APPLICATIONS

DDX 7000 & 8003 Digital Partial Discharge Detectors The HAEFELY HIPOTRONICS DDX Digital Partial Discharge Detector offers the high accuracy and flexibility of digital technology, plus the real-time display

Data Communications Prof. Ajit Pal Department of Computer Science & Engineering Indian Institute of Technology, Kharagpur Lecture # 03 Data and Signal

(Refer Slide Time: 00:01:23) Data Communications Prof. Ajit Pal Department of Computer Science & Engineering Indian Institute of Technology, Kharagpur Lecture # 03 Data and Signal Hello viewers welcome

LVDS Technology Solves Typical EMI Problems Associated with Cell Phone Cameras and Displays

AN-5059 Fairchild Semiconductor Application Note May 2005 Revised May 2005 LVDS Technology Solves Typical EMI Problems Associated with Cell Phone Cameras and Displays Differential technologies such as

3172V21 - Synthesised WBFM Transmitter

1 General This project is a complete crystal-controlled Wide Band Frequency Modulated (WBFM) transmitter delivering a power output in the order of 10 milli-watts (+10dBm) using simple components. The transmitter

Receive Line Interface www.dalsemi.com FEATURES Line interface for T1 (1.544 MHz) and CEPT (2.048 MHz) primary rate networks Extracts clock and data from twisted pair or coax Meets requirements of PUB

PCI Express Transmitter PLL Testing A Comparison of Methods. Primer

PCI Express Transmitter PLL Testing A Comparison of Methods Primer Primer Table of Contents Abstract...3 Spectrum Analyzer Method...4 Oscilloscope Method...6 Bit Error Rate Tester (BERT) Method...6 Clock

Issue 1.0. Cyrus Audio Ltd. Ermine Business Park. Huntingdon. Cambridgeshire, PE29 6XY +44(0) September 2014

Issue 1.0 Cyrus Audio Ltd Ermine Business Park Huntingdon Cambridgeshire, PE29 6XY +44(0)1480 435 577 September 2014 The recipient acknowledges Cyrus designs are protected and remain the property of Cyrus

Signal Types and Terminations

Helping Customers Innovate, Improve & Grow Application Note Signal Types and Terminations Introduction., H, LV, Sinewave, Clipped Sinewave, TTL, PECL,,, CML Oscillators and frequency control devices come

2.1 CAN Bit Structure The Nominal Bit Rate of the network is uniform throughout the network and is given by:

Order this document by /D CAN Bit Timing Requirements by Stuart Robb East Kilbride, Scotland. 1 Introduction 2 CAN Bit Timing Overview The Controller Area Network (CAN) is a serial, asynchronous, multi-master

DVB-T. The echo performance of. receivers. Theory of echo tolerance. Ranulph Poole BBC Research and Development

The echo performance of DVB-T Ranulph Poole BBC Research and Development receivers This article introduces a model to describe the way in which a single echo gives rise to an equivalent noise floor (ENF)

The Effective Number of Bits (ENOB) of my R&S Digital Oscilloscope Technical Paper

The Effective Number of Bits (ENOB) of my R&S Digital Oscilloscope Technical Paper Products: R&S RTO1012 R&S RTO1014 R&S RTO1022 R&S RTO1024 This technical paper provides an introduction to the signal

VOR software receiver and decoder with dspic

VOR software receiver and decoder with dspic By Josef Stastny 9-15-2004-1 - 1. Introduction VOR (VHF Omni-directional Radio range) is a radio navigation system used for civil and military navigation of

Tamura Open Loop Hall Effect Current Sensors

Tamura Open Loop Hall Effect Current Sensors AC, DC, & Complex Currents Galvanic Isolation Fast Response 50kHz small signal frequency bandwidth Quality & Reliability RoHs compliance Overview The following

Glitch Free Frequency Shifting Simplifies Timing Design in Consumer Applications System designers face significant design challenges in developing solutions to meet increasingly stringent performance and

bel canto The Computer as High Quality Audio Source A Primer

The Computer as High Quality Audio Source A Primer These are exciting times of change in the music world. With CD sales dropping and downloaded MP3 music, streamed music and digital music players taking

DIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION

DIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION Introduction The outputs from sensors and communications receivers are analogue signals that have continuously varying amplitudes. In many systems

Transmission of fast signals via optical fibres

Transmission of fast signals via optical fibres Michael Daniel for Richard White rw@ast.leeds.ac.uk 1 Digitizing the signal from an IACT camera: why fast signal transmission is needed. ns The Cherenkov

Electronic Communications Committee (ECC) within the European Conference of Postal and Telecommunications Administrations (CEPT)

Page 1 Electronic Communications Committee (ECC) within the European Conference of Postal and Telecommunications Administrations (CEPT) ECC RECOMMENDATION (06)01 Bandwidth measurements using FFT techniques

Agilent 8904A Multifunction Synthesizer dc to 600 khz

Agilent 8904A Multifunction Synthesizer dc to 600 khz Technical Specifications Build complex waveforms from common signals The Agilent Technologies 8904A Multifunction Synthesizer uses VLSIC technology