ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.7

Transcription

1 ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER A 2.7 Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI Systems Zhiwei Xu 1, Hyunchol Shin 2, Jongsun Kim 1, M. Frank Chang 1, Charles Chien 1,3 1 University of California Los Angeles, CA 2 Qualcomm, San Diego, CA 3 G-Plus, Santa Monica, CA An interconnect transceiver chip-set in CMOS technology that fulfills the demands of future high speed, fault tolerant and smart interconnect systems is presented. By using code- division multiple access (CDMA) techniques in the transmitter and receiver chips, a CDMA-Interconnect (CDMA-I) system has been demonstrated that enables reconfigurability while achieving an aggregate throughput of 2.7Gb/s. The achieved throughput is several orders of magnitude higher than prior work [2]. The proposed CDMA-I uses pseudo-noise (PN) codes to separate different users and I/O ports on a shared bus. It modulates the data into a spread spectrum signal by orthogonal Walsh codes or PN codes such as Gold and Kasami codes. The code-modulated signal from each I/O port is combined into a multi-level signal for transmission. For N I/O ports, the minimum spread ratio is log 2 N+1. Reconfigurability is a unique advantage of CDMA-I as the receiver can detect data sequences of different user s by simply changing codes through firmware rather than additional hardware for retiming and/or framing of different users. Because the same code can be used for different users, CDMA-I can implement any N-to-M (M N) I/O mapping. Moreover, CDMA-I enables reconfigurability not only in connectivity but also bandwidth. One or more users could be allocated more bandwidth by simply assigning more than one code to the user. It can also reduce the communication overhead in a packet switched system by eliminating the need for having I/O port address in the headers of the transmitted packets. The CDMA-I chip-set is used for re-configurable chip interconnects [1], wired busses [2], and future gigascale integrated systems. Figure shows a 4-port system implemented by the CDMA-I transceiver. Each port on the bus sends coded data which can be recovered by any other port using the corresponding code key. Figure shows the CDMA-I transceiver architecture. The CDMA-transmitter consists of a baseband CDMA-modulator to modulate the user data with the assigned code, a Walsh code generator to provide orthogonal data key s, a data combiner to format user data into a serial multi-level signal for transmission, a phase-lock-loop clock generator, and finally a 50Ω matching output buffer. The CDMA-receiver detects the multi-level signal transmitted through an off-chip interconnect. The clock is recovered from the received signals prior to data demodulation using the corresponding Walsh codes. Synchronization of the Walsh code is critical to data recovery in the CDMA demodulator. In commercial wireless CDMA systems, a pilot sequence is used for synchronization which decreases the communication efficiency. The CDMA-I receiver uses an asynchronous error detection correlator that obtains synchronization within one-symbol clock period. Since the received signal has multiple levels as shown in Fig , a multi-level signal clock-data-recovery (CDR) circuit is needed. To fully utilize the edge information of the input signal and avoid extra coding as in [3], the CDR circuit with Alexandertype phase detector[4] is designed to use all data transitions to reduce jitter in the recovered clock and data. This is possible because the received data has more data transitions due to modulation by different Walsh codes. The circuit architecture is shown in Fig a. The edge detector extracts the edge information from the quantized data and the transition arbitrator indicates the phase relationship between the input signal and the clock. As shown in Fig b, the clock falling edge is used as the reference edge to determine the early or late clock. A fully differential charge pump provides a differential control signal to the VCO, whose supply sensitivity is less than 0.1%. An LC VCO is used to ensure low phase noise and jitter. However, a conventional LC VCO uses a single-ended control line, which is sensitive to noise. Differential ring type LC VCO are utilized for noise immunity but at a cost of two to three times increase in silicon area. To achieve immunity to noise on the control line with minimal area penalty, a differential control LC VCO using symmetrical MIS varactor pairs is implemented, as in Fig a. The two pairs of MIS varactors C1(C2) and C3(C4) serve as differential tuning capacitors. Figure 4.7.4b shows that any capacitance change in C1(C2) and C3(C4) cancel each other keeping the total capacitance of C1+C3 and C2+C4 constant. Therefore, the sensitivity to common-mode voltage variations of this VCO is only 1.2MHz/V compared to 110MHz/V achieved with single-ended control line. Further considering the coupling effect of the tank capacitor between control line and supply, the resulting common noise rejection ratio is 16dB higher than that of the single-ended control configuration. Moreover, this VCO has twice the tuning range compared to a conventional LC VCO single-ended control line. A 2x2 interface chip-set has been fabricated in TSMC 0.18µm CMOS technology to demonstrate a 2.7Gbps CDMA-I system. The differential control VCO achieves a tuning range of GHz and phase noise of -96.5dBc/Hz at a 100kHz offset. Figure 4.7.5a shows the transmission data sequence D0 and D1 and the modulated multi-level 400mVp-p output, whose peak-to-peak voltage is 400mV. Figure 4.7.5b shows the received data eye through a 24cm 50Ω cable line. Figure 4.7.6a shows the recovered clock spectrum at 2.65GHz and (b) shows the histogram of the recovered clock. A pseudo random data sequence input produces 2.5ps rms jitter on the recovered clock signal. The waveforms for the input data and the output data are displayed in Fig c, demonstrating the on-the-fly reconfigurability. The chip-set occupies 0.6mm 2 and has been tested in a TQFP package. The transmitter draws 37mA and the receiver draws 45mA from a 1.8V supply. Each I/O pair consumes 74mW. Figure shows the micrograph of the chip-set. Acknowledgments The authors acknowledge G-Plus for chip fabrication and contributions from D. Chow, S. Schell, J. Chen, Y-C. Wu, N. Wang, Professor K. Yang and Dr. S. Stefanos. This work is supported in part by DARPA, SRC and MARCO IFC. References [1] M.F. Chang et al. RF/Wireless Interconnect for Inter- and Intra-Chip Communications. Proceedings of the IEEE, vol.89, (no.4), IEEE, April 2001 [2] R. Yoshimura et al. DS-CDMA Wired Bus with Simple Interconnection Topology for Parallel Processing System LSIs, ISSCC Digest of Tech. Papers, pp , Feb [3] R. Farjad-Rad et al. A 0.3µm CMOS 8-Gb/s 4-PAM Serial Link Transceiver, Symposium on VLSI Circuits Digest of Technical Papers, May 1999 [4] M. Soyuer et al. A Monolithic 2.3Gb/s 100mW Clock and Data Recovery Circuit, ISSCC Digest of Tech. Papers, pp , Feb

2 ISSCC 2003 / February 10, 2003 / Salon 8 / 4:45 PM Figure 4.7.1: A 4-port system implemented by the CDMA interconnect transceiver. Figure 4.7.2: CDMA interconnect transceiver architecture. 4 Figure 4.7.3: (a) Multi-level signal clock data recovery circuit (b) Early and late clock decision. Figure 4.7.4: (a) Differential control VCO circuit diagram (b) Differential pair MIS varactor capacitance. Figure 4.7.5: (a) Transmitter data sequences, three-level signal output and (b) Received data eye through a 24cm cable (1.5GHz bandwidth). Figure 4.7.6: (a) Recovered clock spectrum (b) Recovered clock histogram and jitter (c) Waveforms of CDMA transmitter and receiver.

3 4 Figure 4.7.7: (a) CDMA transmitter chip photo (b) CDMA receiver chip photo.

4 Figure 4.7.1: A 4-port system implemented by the CDMA interconnect transceiver.

5 Figure 4.7.2: CDMA interconnect transceiver architecture.

6 Figure 4.7.3: (a) Multi-level signal clock data recovery circuit (b) Early and late clock decision.

7 Figure 4.7.4: (a) Differential control VCO circuit diagram (b) Differential pair MIS varactor capacitance.

8 Figure 4.7.5: (a) Transmitter data sequences, three-level signal output and (b) Received data eye through a 24cm cable (1.5GHz bandwidth).

9 Figure 4.7.6: (a) Recovered clock spectrum (b) Recovered clock histogram and jitter (c) Waveforms of CDMA transmitter and receiver.

10 Figure 4.7.7: (a) CDMA transmitter chip photo (b) CDMA receiver chip photo.