Read-Only Memory Cells

Transcription

1 Read-Only Memories! Read-Only Memories are nonvolatile Retain their contents when power is removed! Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 1

2 Read-Only Memory Cells BL BL BL 1 WL WL V DD WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2

3 MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads

4 MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

5 ROM Example A1! 4-word x 6-bit ROM Represented with dot diagram A0 Dots indicate 1 s in ROM weak pseudo-nmos pullups Word 0: Word 1: Word 2: Word 3: :4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nmos NORs 5

6 ROM Array Layout! Unit cell is 12 x 8 λ (about 1/10 size of SRAM) Unit Cell 6

7 A1 A0 ROM Array Layout weak pseudo-nmos pullups 2:4 DEC GND ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Word Lines! Unit cell is 12 x 8 λ (about 1/10 size of SRAM) Unit Cell Y5 Y4 Y3 Y2 Y1 Y0 Word Lines are vertically flipped w.r.t. schematic 7

8 Row Decoders! ROM row decoders must pitch-match with ROM Only a single track per word! A0 /A0 A1 /A1 A0 /A0 A1 /A1 VDD GND 8

9 Complete ROM Layout Complement Generation Pull-up Row Decode ROM Core Output Inverters 9

10 MOS NOR ROM Layout Cell (9.5λ x 7λ) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion

11 MOS NOR ROM Layout Cell (11λ x 7λ) Programmming using the Contact Layer Only - Inactive transistors loading word lines + More steps before customization Polysilicon Metal1 Diffusion Metal1 on Diffusion

12 MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row

13 MOS NAND ROM Layout Cell (8λ x 7λ) Programmming using the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion

14 Cell (5λ x 6λ) NAND ROM Layout Programmming using Implants Only Polysilicon Threshold-altering implant Metal1 on Diffusion

15 Equivalent Transient Model for MOS NOR ROM Model for NOR ROM V DD BL WL r word C bit c word! Word line parasitics Wire capacitance and gate capacitance Wire resistance (polysilicon)! Bit line parasitics Resistance not dominant (metal) Drain and Gate-Drain capacitance

16 Equivalent Transient Model for MOS NAND ROM Model for NAND ROM V DD BL r bit C L WL r word c bit c word! Word line parasitics " Similar to NOR ROM! Bit line parasitics " Resistance of cascaded transistors dominates " Drain/Source and complete gate capacitance

17 Decreasing Word Line Delay

18 Precharged MOS NOR ROM f pre V DD Precharge devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

19 PROMs and EPROMs! Programmable ROMs Build array with transistors at every site Burn out fuses to disable unwanted transistors! Electrically Programmable ROMs Use floating gate to turn off unwanted transistors EPROM, EEPROM, Flash Source Gate Drain Polysilicon Floating Gate Thin Gate Oxide (SiO 2) n+ n+ p bulk Si 19

20 Non-Volatile Memories The Floating-gate transistor Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol

21 Flash Programming! Charge on floating gate determines V t! Logic 1: negative V t! Logic 0: positive V t! Cells erased to 1 by applying a high body voltage so that electrons tunnel off floating gate into substrate! Programmed to 0 by applying high gate voltage 21

22 Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V -2.5 V 0 V 0.5 V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T.

23 A Programmable-Threshold Transistor

24 FLOTOX EEPROM Floating gate Source Gate Drain I nm n 1 Substrate p n 1 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic

25 EEPROM Cell BL WL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion # 2 transistor cell

26 Flash EEPROM Control gate Floating gate erasure n + source programming p-substrate Thin tunneling oxide n + drain Many other options

27 Cross-sections of NVM cells Flash Courtesy Intel EPROM

28 Basic Operations in a NOR Flash Memory Erase

29 Basic Operations in a NOR Flash Memory Write

30 Basic Operations in a NOR Flash Memory Read

31 ! High density, low cost / bit Programmed one page at a time Erased one block at a time NAND Flash! Example: 4096-bit pages 16 pages / 8 KB block Many blocks / memory 31

32 NAND Flash Memory Word line(poly) Unit Cell Source line (Diff. Layer) Courtesy Toshiba

33 NAND Flash Memory Select transistor Word lines Active area STI Bit line contact Source line contact Courtesy Toshiba

34 NAND vs NOR Flash NOR NAND Read Faster Slower Write/Erase Slower Faster Density Bigger Smaller (~60%) Applications Code, Config File Storage, SSDs

35 NAND vs NOR Flash 35

36 Characteristics of State-ofthe-art NVM

37 Building Logic with ROMs! Use ROM as lookup table containing truth table n inputs, k outputs requires 2 n words x k bits Changing function is easy reprogram ROM! Finite State Machine inputs n DEC n inputs, k outputs, s bits of state Build with 2 n+s x (k+s) bit ROM and (k+s) bit reg 2 n wordlines ROM Array k outputs inputs n ROM k s state outputs k s 37

38 64 Gb NAND Flash! 64K cells / page! 4 bits / cell (multiple V t )! 64 cells / string 256 pages / block! 2K blocks / plane! 2 planes [Trinh09] 38