Inverting Amplifier. vout = vout. vout v R F. vs v R s. i s. Figur e 8.5

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1 A vo v vs is if iin vs v is s i s i F ; i in vs vout s A v s F vout s i s vs s ; i vs vs i s Inverting Amplifier vout v ; if F 0; v v vout F s vout A v F ; iin Figur e 8.5 0

2 Design Example: Design an inverting amplifier with a closed loop voltage of A v -5. Assume the op-amp is driven by a sinusoidal soorce, v s 0. sin ωt volts, which has a source resistance of s kω and which supply a maximum current of 5 µa. Assume that the frequency is low. v i s s ( s in this example means two resistances : s sr. s v represents the source resistance. Therefore s sr i s sr (max) 0. If i (max) 5 A, then we write (min) vs s µ sr is (max) Ω and should be9 k A v 5. sr Accordingly 5( sr ) kω 0 kω

3 To Solve Ideal Op-Amp Circuit If the noninverting terminal of the op-amp is at ground potential, then the inverting terminal is at virtual ground. Sum currents at this point, assuming zero current enters the op-amp itself. If the noninverting terminal of the op-amp is not at ground potential, then the inverting terminal voltage is equal to that at the noninverting terminal. Sum currents at the inverting terminal node, assuming zero current enters the op-amp itself. For an ideal op-amp circuit, the output voltage is determined from either step or step above and is independent of any load connected to the output terminal. 3

4 Amplifier with a T-Network i i 3 v x 3 4 i 4 v s i v o v x 0 i v s ( ) v x v x v x v i o i4 i3; 4 3 Combing the above equations we get A v vo vs ( ) 4

5 Design Example: An op-amp with a T-network is to be used as a preamplifier for a microphone. The maximum microphone output voltage is mv (rms) and the microphone has an output resistance of kω. The op-amp circuit is to be designed such that the maximum output voltage is. V (rms). The input amplifier resistance should be fairly large but all resistance values should be less than 500 kω.. Av Av ( ) 4 If we choose ( 3 ) 8; We should include the value of the source resistance in the calculation If we set 49 kω and sr kω then the total resistance ( effective ) will be 50 kω kω and 4 38.kΩ 5

6 A Single Difference or Differential Amplifier v out ( v ) v vout Ad vid Figure 8.0 6

7 Instrumentation Amplifier Input (a) and output (b) stages of Instrumentation amplifier Figure 8.4, 8.5 A V vout v v F 7

8 Design Example: Determine the range required for resistor in the instrumentation amplifier to realize a differential gain adjustable from 5 to 500. Assume F, so that the difference amplifier gain is. Assume is a combination of a fixed resistor f and a variable resistor v. Assume v 00 kω AV 500 f 5 and from the maximum gain expression f f.5 f v out v v f kω F and the minimum differential gain is 49 f f 00 and 75.5 kω f v 8

9 Large Signal Operation of Op Amp Like other amplifiers, op amps operate linearly over a limited range of output voltages. Another limitation of the operation of op amps is that their output current is limited to a specified maximum. For example, the op amp 74 is specified to have a maximum output current of ±0 ma. ead Example.5. Another phenomenon that can cause nonlinear distortion when large output signals are present is that of slew-rate limiting. This means there is a specific maximum rate of change possible at the output of a real op amp. This maximum is known as the slew rate (S) of the op amp and is defined as S dv o dt max 9

10 Design Example. Design a difference amplifier with a specified gain and minimum differential input resistance. Design the circuit such that the differential gain is 30 and the minimum differential input resistance is i 50 kω i 50 kω 3 5 kω Since the differential gain is we must have kω 30, 0

11 DC Imperfections Offset Voltage The IC Op-amp comes so close to ideal performance that it is useful to state the characteristics of an ideal amplifier without regard to what is inside the package. Infinite voltage gain Infinite input impedance Zero output impedance Infinite bandwidth Zero input offset voltage (exactly zero out if zero in).

12 Build any op amp circuit, apply zero voltage to its input, and what do you expect at the output? Although you would zero voltage, there is actually an error voltage present at its output. What causes this error? You can trace the error back to a number of unbalances in the op amp's internal transistors and resistors. To account for this in a circuit design, the net error is modeled as an offset voltage, V OS, in series with op amp's input terminals. How will it affect the circuit? That depends on the op amp itself and the circuit design.

13 The input offset voltage can range from µv to mv and can be either polarity. Bipolar op amps have lower offset voltages than JFET or CMOS types. The offset voltage is modeled in series with one of the op amp input terminals. Which one? Although the net effect is the same at either input, it is much easier to analyze V OS in series with the non-inverting input. Why? The resulting circuit with V OS at V looks just like the non-inverting amplifier configuration. 3

14 - V OS V o The input voltage signal is short circuited Vo VOS ( ) Actual op amp - - Offset free op amp V OS 4

15 Offset Voltage Compensation In many applications, especially those for which the input signal is large compared to the offset voltage V OS, the effect of the offset voltage is negligible. However, there are situations in which it is necessary to compensate for or null out the offset voltage. Two such methods are: Offset null terminals: Some op amp are provided with two additional terminals to which a specified circuit can be connected to trim to zero the output DC voltage due to V OS. Offset compensation circuit through two terminals. Capacitively coupling the amplifier. 5

16 V Offset nulling terminals V- Potentiometer The output DC offset voltage of an op amp can be trimmed to zero by Connecting a potentiometer to the two offset-nulling terminals. The wiper Of the potentiometer is connected to the negative supply of the op am. 6

17 C - V OS Capacitively coupled inverting amplifier. 7

18 Exercise.4: Consider an inverting amplifier with a nominal gain of 000 constructed from an op amp with an input offset voltage of 3 mv and with output saturation levels of ±0 V. (a) What is the peak sine-wave input signal that can be applied without output clipping? (b) If the effect of V OS is nulled at room temperature (5 oc) how large an input can now one apply if: (i) the circuit is to operate at a constant temperature? (ii) the circuit is to operate at a temperature in the range 0 o C to 75 o C and the temperature coefficient of V OS is 0 µv/ o C? (b) Vo VOS ( ); Vo 3mV( 000) 3 V Maximum amplitude of a sine wave at the op amp output is0-3 For part (ii) : Temperature range of voltage range of (0-5) 0µ V This input offset range corresponds - 50µ V( 000) (b) For part (i) 0 mv 0 o C to 75 o C corresponds -50µ V to ((75-5) 0µ V to output DC levels of -0.5 V to 500 µ V ( 000) to input offset 0.5 V. 7V. 500µ V. 8

19 Exercise.5: Consider an inverting amplifier with a nominal gain of 000 constructed from an op amp with an input offset voltage of 3 mv and with output saturation levels of ±0 V. The amplifier is capacitively coupled. (a) What is the DC offset voltage at the output and what is the peak sine wave signal that can be applied at the input without output clipping? Is there a need for offset trimming? (b) If kω and MΩ, Find the value of C that will ensure that the gain will be greater than 57 db down to 00 Hz. The maximum amplitude of a sine wave at the output without clipping is mv V, accordingly there is no need for offset trimming. (b) The magnitude of the gain of this amplifier is 0log A d c 57; A d ; C.59µ F ω ; A d jωc c 9 ω

20 Op-amp Input Offset Current One of the practical op amp limitations is that the input bias currents for the two inputs may be slightly different. Even though the inputs are designed to be symmetrical, slight differences which occur in the manufacturing process may give slightly different bias currents. This offset current is typically on the order of a tenth of the input bias current, with 0 na being a representative offset current for a 74 op amp. Even with identical source impedances, this offset current will produce a slight voltage between the input terminals, contrary to the ideal op amp. 0

21 I B - I B 3 / I B 3 / 0 V - I B I B 3 V o I B A resistor may be added in series with the Non-inverting input lead to reduce the value of The output dc voltage due to input bias currents 3 I I V V B OS o o I I I B I B OS B I B I B I B (with (no 3 ) 3 )

22 To minimize the effect of the input bias currents one should place in the positive lead a resistance equal to the DC resistance seen by the inverting terminal. If the amplifier is AC coupled, we should select 3. We must always provide a DC path between each of the input terminals of the op amp and ground. If we couple both input of the amplifier then the circuit will not operate without the resistance 3 to ground.

23 .6: Consider an inverting circuit designed using an op amp and two resistors, 0 kω and MΩ. If the op amp is specified to have an input bias current of 00 na and an input offset current of 0 na, find the output DC offset voltage resulting and the value of resistor 3 to be placed in series with the positive input lead in order to minimize the output offset voltage. What is the new value of Vo. V o 3 V o I B 00 na MΩ 0.V 9.9 kω 0 kω I OS 0 na 9.9 ka 0.0 V 3