SanDisk G 32Gb NAND Flash Multichip Package TMCL4 NAND Flash Controller Die

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Lorraine Daniels
7 years ago
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1 G 32Gb NAND Flash Multichip Package Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Isolation 3.8 Wells and Substrate 4 6T SRAM Cell Analysis 4.1 Overview 4.2 Plan-View Analysis 4.3 Cross-Sectional Analysis (Perpendicular to Wordline) 4.4 Cross-Sectional Analysis (Perpendicular to Bitline) 5 Materials Analysis 5.1 Overview 5.2 TEM-EDS and TEM-EELS Analyses of the Dielectrics 5.3 TEM-EDS of Metallization 5.4 TEM-EDS and TEM-EELS Analyses of Transistors, Contacts, and Poly 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions 7 Statement of Measurement Uncertainty and Scope Variation 8 References About Chipworks

3 Overview Overview 1.1 List of Figures 2 Device Overview Package Photograph Top Package Photograph Bottom Package X-Ray Side View Package X-Ray Plan View Die Photograph NAND Flash Die GRX Die Markings NAND Flash Die GRX Die Photograph NAND Flash Controller Die TMCL Die Markings NAND Flash Controller Die TMCL Annotated Die Photograph Analysis Sites Die Corner A Die Corner B Die Corner C Die Corner D Minimum Pitch Bond Pads 3 Process Analysis General View of TMCL Die Edge Die Seal Bond Pad Right Bond Pad Edge Passivation and ILD TEM Passivation ILD ILD TEM ILD ILD 4 through ILD TEM ILD TEM ILD TEM ILD TEM ILD ILD 1 and PMD TEM PMD Minimum Pitch Metal TEM Metal TEM Metal 7 Hard Mask Layer Minimum Pitch Metal TEM Metal 6 and Via Minimum Pitch Metal 5 and Metal Minimum Pitch Metal 4 and Metal TEM Metal TEM Metal 4

4 Overview TEM Metal TEM Metal Minimum Pitch Metal TEM Metal Via 5s Minimum Pitch Via 4s Vias 3 and Via 2 Stack Minimum Pitch Vias 3s Minimum Pitch Vias 2s Minimum Pitch Via 1s TEM Via Minimum Pitch Contacts to Diffusion Contact to Poly TEM Contact to Diffusion TEM Contact Top TEM Contact to Diffusion NMOS Transistors PMOS Transistors TEM Transistor Gate TEM Gate Oxide Minimum Pitch Gate Minimum Width STI STI under Poly Gate Gate Wrap over STI SCM Profile of Well Structure SRP Peripheral P-Well 4 6T SRAM Cell Analysis T SRAM Metal 3 Wordlines and Power Buses Metal 2 Bitlines Metal 2 and Via 2s Metal 1 Local Interconnects SRAM at Poly SRAM at Diffusion SRAM Perpendicular to Wordline TEM NMOS Pull-Down and Access Transistors TEM NMOS Pull-Down Transistor TEM NMOS Access Transistor PMOS Pull-Up Transistors TEM Pull-Up Transistor TEM Butted Contact SRAM Perpendicular to Bitline SRAM Perpendicular to Bitline

5 Overview Materials Analysis TEM-EDS Passivation TEM-EDS Metal 7 Hard Mask Layer TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS PMD 4 and PMD TEM-EDS PMD 2 and PMD TEM-EELS PMD TEM-EDS STI Oxide TEM-EDS Metal 7 Barrier Metal TEM-EDS Metal 2 Liner TEM-EDS Gate Silicide TEM-EDS Source/Drain Silicide TEM-EELS Oxide Buffer TEM-EELS Nitride Sidewall Spacer

6 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Package, Die, and Bond Pad Sizes 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor Horizontal Dimensions Transistor and Polycide Vertical Dimensions Die Thickness and Well Depths 4 6T SRAM Cell Analysis SRAM Dimensions 6 Critical Dimensions Package, Die, and Bond Pads Minimum Pitch Metals Minimum Pitch Contacts and Vias Transistor Horizontal Dimensions SRAM Dimensions Vertical Dimension Dielectrics Vertical Dimensions Metals Transistor Vertical Dimensions Die and Wells Vertical Dimensions

7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

Intel Q3GM ES 32 nm CPU (from Core i5 660)

Intel Q3GM ES 32 nm CPU (from Core i5 660) Intel Q3GM ES Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call