Memory. Hot electron injection and electron tunneling mechanisms for analog memory (Shih-Chii Liu) Uses of long-term analog storage.

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1 Hot electron ection and electron tunneling mechanisms for analog memory (Shih-Chii Liu) Memory Short-term memory (ms->s) Memory can be stored as charge on a capacitor. Needs frequent refresh or updating because of leak currents. olatile memory storage. nformation is lost when power is turned off. Long-term memory (s->yr) Memory is stored as charge on a floating gate No updating is necessary Non-voltage charge storage. nformation is retained when power is turned off. Write Floating gate s completely surrounded by SiO 2 Uses of long-term analog storage Adaptation Learning Poly SiO 2 SiO 2 is an insulator Floating gate charge can stay for years. This is called nonvolatile memory. Si Markram, Science, 1998 Memory types Floating-gate MOSFET RAM (Random Access Memory) DRAM (Dynamic RAM) SRAM (Static RAM) ROM (Read Only Memory) PROM (Precursor to EPROM, OTP) EPROM (Electrically Programmable ROM) U-EPROM EEPROM (Electrically Erasable Programmable ROM) Flash EEPROM Analog floating gate memory Neuromorphic Engineering Lec. 12 1

2 Two ways of overcoming a SiO2 barrier Tunneling Take electrons off the by tunneling Electrons tunnel off and onto nwell Two tunneling mechanims Direct Electrons tunnel from/to Si conduction bands Requires extremely thin oxide Fowler-Nordheim Electrons tunnel from Si conduction band to SiO 2 oxide conduction band Requires high voltage to make effective distance small Fowler-Nordheim tunneling 3.2e 3.2e + - Si SiO 2 Si Direct Fowler-Nordheim 3.1e Oxide conduction band nwell Electron wave function, ~ e ikx k 2 > 0, travelling wave k 2 < 0, e - k x exponentially damped Probability ~ ~ e -2 k x ~ tunneling current p- substrate =0 Fowler-Nordheim tunneling Fowler-Nordheim tunneling model e Effective thickness Oxide Conduction band i ox 0 e 0 ox Constant Oxide voltage p substrate Oxide current Another constant >>0 Oxide thickness nwell Neuromorphic Engineering Lec. 12 2

3 Tunneling current Tunneling current vs. ox Tunneling degrades over time Measuring oxide current tun ref C out ( out ref dout dq 1 dt dt C dout iox C dt ) Q / C Why can t we tunnel onto gate? + - p substrate The well can only go positive relative to the substrate Two hot-electron ection s nfet ector Create hot electrons directly Must run in subthreshold for large electric field at drain Must have gate at higher potential than channel Not possible with normal nfet s possible with additional p-base implant pfet ector pfet carriers are holes Holes are accelerated at drain Holes knock loose electrons by impact ionization Electrons are accelerated back into channel A few electrons end up in oxide conduction band, and are drawn to by electric field Neuromorphic Engineering Lec. 12 3

4 nfet ection & tunneling pfet hot electron ection p+ P-base p + p + Holes in channel Hot electron ection Hot electron ection Depletion region Depletion region Hole Hole Electron mpact ionization pfet hot electron ection Drain Put electrons onto by ection E c E g Electron E g Hole pfet carriers are holes Holes are accelerated at drain Holes in channel Holes knock loose electrons by impact ionization Electrons accelerated back into channel A few electrons end up in oxide conduction band, and are drawn to by electric field E v Channel Neuromorphic Engineering Lec. 12 4

5 pfet ector & tunneling Hot electron ection & tunneling p+ p+ metal1 poly1 poly2 gate oxide p+ p+ Hot electron ection & tunneling Hot electron ection & tunneling Floating gate () Tunneling p+ p+ njection Tunneling njection njection model njection models are empirical They depend on 2-dimensional electrostatics around drain of transistor njection model 1) Source of current : (in subthresho ld) s 2) Sufficient voltage drop so that electrons canbe above SiO2 barrier : f 1 ( ) dc e ( drain to channel potential) dc 3) Depletionregion shouldbe as short as possible : f2( d ) dep e (d is depletion region width) dep 4) potential d so that all electrons will be swept into : f3( ) fg d e ( fg d ) Neuromorphic Engineering Lec. 12 5

6 njection model njection efficiency vs s Empirical relationship : dc s e where 250m 500m ection efficiency s Efficiency Source current N vs. P FET ection Neuromorphic systems that use Learning synapses (Diorio et al 1996; Haefliger 2007; Liu et al 2008; Ramakrishnan et al 2011). Parameter storage on multi-neuron arrays (Hafliger and Rasche 1999; Schemmel et al 2004; Brink et al 2013) Construction of FPAA (Field Programmable Analog Arrays) Brink et al Summary Mechanism for long-term analog storage Mechanism can be used for modeling long time-constant learning processes in silicon Details of tunneling and ection process Neuromorphic Engineering Lec. 12 6