CHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS

Transcription

1 CHAPTER 4 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 4. Digital Logic Inverters 4. The CMOS Inverter 4.3 Dynamic Operation of the CMOS Inverter 4.4 CMOS Logic-Gate Circuits 4.5 Implications of Technology Scaling: Issues in Deep-Submicron Design NTUEE Electronics III 4-

2 4. DIGITAL LOGIC INVERTERS The Voltage-Transfer Characteristic (VTC) The function of the inverter is to invert the logic value of its input signal The voltage-transfer characteristic is used to evaluate the quality of inverter operation VTC parameters V OH : output high level V OL : output low level V IH : the minimum value of input interpreted by the inverter as a logic V IL : the maximum value of input interpreted by the inverter as a logic 0 Transition region: input level between V IL and V IH NTUEE Electronics III 4-

3 Noise Margins The VTC is generally non-linear V IH and V IL are defined as the points at which the slope of the VTC is Robustness (noise margin at a high level): NM H = V OH V IH Robustness (noise margin at a low level): NM L = V IL V OL Static inverter characteristics for ideal VTC: V OH = V V OL = 0 V IH = V IL = V / NM H = NM L = V / Ideal VTC NTUEE Electronics III 4-3

4 Power Dissipation Static power dissipation: power dissipated when the inverter stays in logic 0 or logic Dynamic power dissipation: power dissipated as the output is switching P D CV Propagation Delay f t PHL : high-to-low propagation delay t PLH : low-to-high propagation delay t P (propagation delay) = ( t PLH + t PHL )/ Maximum switching frequency f max = /t P The output transient of the inverter can be characterized by a RC charge/discharge model v O ( t) V ( V V t / RC 0 ) e NTUEE Electronics III 4-4

5 Power-Delay Product and Energy-Delay Product Power and delay are often in conflict for inverter operation Power-delay product is a figure-of-merit for comparing logic-circuit technologies or families Power-delay product is defined as Energy-delay product is defined as Silicon Area PDP P t Area reduction through advances in processing technology Area reduction through advances in circuit design techniques Area reduction through careful chip layout Fan-In and Fan-Out D P CV EDP CV t P / Fan-in of a gate is the number of its inputs Fan-out is the maximum number of similar gates that a gate can drive Logic-Circuit Families / NTUEE Electronics III 4-5

6 Inverter Implementation Simplest implementation of the inverter with a MOSFET and a load Inverter implementation with complementary switches Inverter implementation with a double-throw switch NTUEE Electronics III 4-6

7 Circuit Operation 4. THE CMOS INVERTER A CMOS inverter consists of an n-channel and a p-channel MOSFET The n-channel device turns on and the p-channel device turns off as the input level goes high The p-channel device turns on and the n-channel device turns off as the input level goes low ' The turn-on device is modeled by a resistance: ' rdsn kn W / L n( V Vtn) and rdsp k p W / Lp V OH = V and V OL = 0 for any CMOS inverter ( V V ) tp NTUEE Electronics III 4-7

8 The Voltage-Transfer Characteristic The transistors go through five different operation regions as the input goes from 0 to V The operating point is obtained by making i DN = i DP Region I: (Q N off; Q P tri.) Region II: (Q N sat.; Q P tri.) Region III: (Q N sat; Q P sat) Region IV: (Q N tri.; Q P sat.) DN i DP Region V: (Q N tri.; Q P off) i DN i DP ( 0) i i i i DN DN DN ( 0) kn( vi Vtn ) kn( vi Vtn) kn vi Vtn) v i i DP DP v k p ( V k i p ( V v k I V I tp v V ( V )( V tp ) v v V ( O O DP p I tp O ) ) ( V v O ) i D i D Region I v O Region II v O i D i D i D Region III Region IV Region V v O v O NTUEE Electronics III 4-8 v O

9 Static Characteristics of the CMOS Inverter Ratioless logic: V OH and V OL are independent of ratio of the transistors V OH = V V OL = 0 Static power dissipation is zero for both states Noise margins can be determined by the VTC The switching voltage (when v I = v O ) is defined by r( V V ) V k tp tn p p ( W / L) p V where r M r kn n( W / L) n V M increases (VTC shifts) with r NM L increases and NM H decreases as r increases NM L decreases and NM H increases as r decreases NTUEE Electronics III 4-9

10 The Matched Inverter A matched inverter has equivalent pull-up and pull-down device with k n = k p and V tn = V tp = V t The VTC is symmetric Determine V IL from the VTC in Region II: ( vi V ) t ( V v V )( V v Determine V IH from the VTC in Region IV: I t O ) ( V v O v I Vt ( V vo ) ( V vi Vt ) ( V vo ) dvi V IL (3V 8 V ) Noise margins: NM H = NM L = (3V + V t )/8 Switching voltage: V M = V / t dv ( vi Vt ) vo vo ( V vi Vt ) dvo dvo vo ( vi Vt ) vo ( V vi Vt ) dvi dvi VIH (5V V t ) 8 O ) dv dv O I NTUEE Electronics III 4-0

11 4.3 DYNAMIC OPERATION OF THE CMOS INVERTER Determining the Propagation Delay Evaluated by charging/discharge the output capacitor C through Q P and Q N Average current method: t PHL : I i i av DN t PLH : i DN ( E) idn ( M ) ( E) kn( V Vtn) V M ) kn ( V Vtn) CV n C I k V V DN ( t PHL where t PLH CV I where n av n av n 7 3V tn Vtn / 4 V V Propagation delay: t P = (t PHL +t PLH )/ pc k pv 7 3 Vtp Vtp / 4 V V NTUEE Electronics III 4-

12 An alternative approach: Modeling the turn-on device as a resistance Use RC charge/discharge behavior to evaluate the propagation delay The empirical values of the resistors are given by R.5 ( k) ( W / L) R ( ) N P k n ( W / L) p t PHL = 0.69R N C t PLH = 0.69R P C and 30 NTUEE Electronics III 4-

13 Determining the Equivalent Load Capacitance Components accountable for the equivalent load capacitance Transistor parasitic capacitances Wiring capacitance or interconnect capacitance Input capacitance of the following stages C Cgd Cgd Cdb Cdb Cg3 Cg 4 C w NTUEE Electronics III 4-3

14 Inverter Sizing Minimum length permitted by the technology is usually used as the length for all channels Device aspect ratio (W/L) n is usually selected in the range to.5 The selection of (W/L) n is relative to (W/L) n Matched inverter by (W/L) p : (W/L) n = n : p (W/L) p = (W/L) n : minimum area, small propagation delay (W/L) p = (W/L) n : a frequently used compromise Transistor sizing (aspect ratios are increased by a factor of S) versus propagation delay Load capacitance: C Equivalent resistance: Propagation delay: Dynamic Power Dissipation Dynamic power dissipation: Cint Cext SCint0 R eq RN ( S Req 0.69 S C ext R R P eq ) S S ( SC 0 ) 0.69 R t 0 P Cext eq C int 0 0 int 0 eq0 PD fcv R S C ext Peak current: I peak V kn V tn NTUEE Electronics III 4-4

15 CMOS Logic-Gate Structure 4.4 CMOS LOGIC-GATE CIRCUITS Implementation of PDN Implementation of PUN The PDN can be most directly synthesized by expressing. The PUN can be most directly synthesized by expressing Y. The PDN can be obtained from the PUN (and vice versa) using duality property. However, duality of the PDN and PUN is not a necessary condition. Y NTUEE Electronics III 4-5

16 Transistor Sizing The (W/L) ratios are chosen for a worst-case gate delay equal to that of the basic inverter The derivation of equivalent (W/L) ratio is based on the equivalent resistance of the transistors Series Connection ( W / L)... eq ( W / L) ( W / L) r DS ( W / L) ParallelConnection ( W / L) eq ( W / L) ( W / L)... Effects of Fan-In and Fan-Out Each additional input to a CMOS gate requires two additional transistors Increases the chip area and the propagation delay due to excess capacitive loading The number of NAND gate is typically limited to 4 Redesign the logic design may be required for a higher number of inputs Advantages of using CMOS logic: static power dissipation, ratioless design, noise margin Disadvantage of using CMOS logic: area, complexity, capacitive loading, propagation delay NTUEE Electronics III 4-6

17 Examples for CMOS Logic Gates NTUEE Electronics III 4-7

18 4.5 IMPLICATIONS OF TECHNOLOGY SCALING Moore s Law A new technology is developed for every ~3 years due to cost and speed requirement The trend was predicted more than 40 years ago by Gordon Moore For every new technology generation: The minimum length is reduced by a factor of.44 and the area is reduced by a factor of The cost is reduced by half or the circuit complexity is doubled Device scaling generally decreases the parasitics and enhances the operating speed The operating power is reduced The current technology node advances into deep-submicron Issues in deep-submicron technologies have to be taken into account for circuit designs NTUEE Electronics III 4-8

19 Scaling Implications NTUEE Electronics III 4-9

20 Velocity Saturation Long-channel devices: Drift velocity: v n = n E Electric field in the channel: E = v DS /L Short-channel devices: Velocity saturates at a critical field E cr with v sat 0 7 cm/s The v DS at which velocity saturates is denoted by V DSsat V DSsat = E cr L = v sat L/ n V DSsat is a device parameter The I-V Characteristics Long-channel devices Saturation current: Short-channel devices i D nc V ) For V GS -V t < V DSsat : same as long-channel devices For V GS -V t > V DSsat : I Dsat W ncox VGS Vt ) V L WCoxvsat VGS Vt V ox W L V ( V ( DSsat DSsat DSsat GS t NTUEE Electronics III 4-0

21 Current Equation for Velocity Saturation For v GS -V t V DSsat and v DS V DSsat, the drain current is given by i D C n ox W L V DSsat v GS Vt V DSsat ( V DS ) The current is reduced from the predication of a long-channel device The dependence on v GS is more linear rather than quadratic Four regions of operation: cutoff, triode, saturation and velocity saturation Short-channel PMOS transistors undergo velocity saturation at the same value of v sat The effects on PMOS are less pronounced due to lower mobility and higher V DSsat NTUEE Electronics III 4-

22 Subthreshold Conduction The device is not complete off in deep-submicron devices as v GS < V t The subthreshold current is exponentially proportional to v GS : i D = I s exp(v GS /nv T ) It is a problem in digital IC design for two reasons: Such current leads to nonzero static power dissipation for CMOS logics May cause undesirable discharge of capacitors in dynamic CMOS logics The Interconnect The width of the interconnect scales down with the CMOS technology The metal wire is no longer an ideal short Series parasitic resistance may cause undesirable voltage drop and excess delay Parasitic capacitance to ground may lead to speed degradation and additional dynamic power NTUEE Electronics III 4-