Lecture 260 Buffered Op Amps (3/28/10) Page 260-1

Transcription

1 Lecture 260 Buffered Op Amps (3/28/0) Page 260 LECTURE 260 BUFFERED OP AMPS LECTURE ORGANIZATION Outline Introduction Open Loop Buffered Op Amps Closed Loop Buffered Op Amps Use of the BJT in Buffered Op Amps Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2602 INTRODUCTION Buffered Op Amps What is a buffered op amp? Buffered op amps are op amps with the ability to drive a low output resistance and/or a large output capacitance. This requires: An output resistance typically in the range of 0 R o 000 Ability to sink and source sufficient current (C L SR) v IN R out Large v OUT Op Amp Buffer R out Small v OUT Types of buffered op amps: Open loop using output amplifiers Closed loop using negative shunt feedback to reduce the output resistance of the op amp CMOS Analog Circuit Design P.E. Allen 200

2 Lecture 260 Buffered Op Amps (3/28/0) Page 2603 OPEN LOOP BUFFERED OP AMPS The Class A Source Follower as a Buffer Simple g m v Small signal gain g m g mbs G L < IN M vout Low efficiency V R out = g m g mbs 500 to 000 NBias M2 Level shift from input to output Maximum upper output voltage is limited Broadbanded as the pole and zero due to the source follower are close so compensation is typically not a problem CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2604 The PushPull Follower as a Buffer Voltage loss from 2 cascaded followers g A v m3 g m g m3 g mbs3 g m g mbs G < L Higher efficiency 0.5 R out g m g 250 to 500 mbs Current in M and M2 determined by: V GS4 V SG3 = V GS V SG2 = 2I 6 K n '(W 4 /L 4 ) 2I 5 K p '(W 3 /L 3 ) 2I K n '(W /L ) 2I 2 K p '(W 2 /L 2 ) V NBias Use the W/L ratios to define I and I 2 from I 5 and I 6 Maximum positive and negative output voltages are limited V PBias I 5 M V SG3 V DD V GS v IN M3 M4 V GS4 I v OUT V SG2 I 6 M2 I CMOS Analog Circuit Design P.E. Allen 200

3 Lecture 260 Buffered Op Amps (3/28/0) Page 2605 TwoStage Op Amp with Follower M3 M4 C c M M2 M7 V I I 5 7 NBias I 9 C L Power dissipation now becomes (I 5 I 7 I 9 ) Gain becomes, A v = g m g m6 g ds2 g ds4 g m8 g ds6 g ds7 g m8 g mbs8 g ds8 g ds CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2606 SourceFollower, PushPull Output Op Amp M7 R out M4 I Bias M M2 R M3 M7 R M M2 M3 M4 R C c M5 M0 V SG8 M6 M8 M9 V GS9 I 7 I 20 M20 Buffer M22 V GS22 V SG2 M2 C L Fig. 7. g m2 g m22 000, A v (0)=65dB (I Bias =50μA), and GB = 60MHz for C L = pf Note the bias currents through M8 and M9 vary with the signal. CMOS Analog Circuit Design P.E. Allen 200

4 Lecture 260 Buffered Op Amps (3/28/0) Page 2607 Compensation of Op Amps with Output Amplifiers Compensation of a threestage amplifier: This op amp introduces a third pole, p 3 (what about zeros?) With no compensation, V out (s) V in (s) = A vo s p s p 2 s p 3 Illustration of compensation choices: jω Poles p ' and p 2 ' v 2 Unbuffered op amp jω x Output stage Pole p 3 ' C L R L Fig. 7.4 p 2 Compensated poles Uncompensated poles p 3 ' p 2 ' p ' p σ p 2 p 3 = p 3 ' p 2 ' p ' p σ p 3 Miller compensation applied around both the second and the third stage. Miller compensation applied around the second stage only. Fig. 7.5 CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2608 CrossoverInverter, Buffer Stage Op Amp Principle: If the buffer has high output resistance and voltage gain (common source), this is okay if when loaded by a small R L the gain of this stage is approximately unity. M7 M3 I Bias M4 C C 2 Input stage ' M Cross over stage M2 Output Stage R L This buffer trades gain for the ability to drive a low load resistance The load resistance should be fixed in order to avoid changes in the buffer gain The pushpull common source output will give good output voltage swing capability CMOS Analog Circuit Design P.E. Allen 200

5 Lecture 260 Buffered Op Amps (3/28/0) Page 2609 CrossoverInverter, Buffer Stage Op Amp Continued How does the output buffer work? The two inverters, MM3 and M2M4 are designed to work over different regions of the buffer input voltage,. Consider the idealized voltage transfer characteristic of the crossover inverters: I Bias ' M7 C M3 M C 2 M4 M2 R L VDD Active MM3 Inverter Saturated Saturated M2M4 Inverter Active 0 ' V A V B Crossover voltage V C = V B V A 0 V C is designed to be small and positive for worst case variations in processing. CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2600 Large Output Current Buffer In the case where the load consists of a large capacitor, the ability to sink and source a large current is much more important than reducing the output resistance. Consequently, the commonsource, pushpull is ideal if the quiescent current can be controlled. A possible implementation: M3 M4 If W 4 /L 4 = W 9 /L 9 and W 3 /L 3 = W 8 /L 8, then the I b I=2I b M0 quiescent currents in M and M2 can be determined by the following relationship: W I = I 2 = I b /L W 7 /L 7 = I b W 2 /L 2 W 0 /L 0 When is increased, turns off M2 and turns on M to source current. Similarly, when is decreased, turns off M and turns on M2 to sink current. M7 I=2I b I b M M CMOS Analog Circuit Design P.E. Allen 200

6 Lecture 260 Buffered Op Amps (3/28/0) Page 260 CLOSED LOOP BUFFERED OP AMPS Principle Use negative shunt feedback to reduce the output resistance of the buffer. v IN A v R o R OUT v OUT R L Output resistance R o R OUT = A v Watch out for the case when R L causes A v to decrease. The bandwidth will be limited by the feedback (i.e. at high frequencies, the gain of A v decreases causing the output resistance to increase. CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2602 Two Stage Op Amp with a Gain Boosted, Source Follower Buffer :K M0 M3 M4 C c R out M M2 M7 V I I 5 7 M I NBias R out g m8 K Power dissipation now becomes (I 5 I 7 I ) Gain becomes, A v = g m g m6 g ds2 g ds4 g m8 K g ds6 g ds7 g m8 Kg mbs8 KG L CMOS Analog Circuit Design P.E. Allen 200

7 Lecture 260 Buffered Op Amps (3/28/0) Page 2603 Gain Boosted, SourceFollower, PushPull Output Op Amp V T 2V OṈ M24 M4 I Bias M23 M M2 M3 M7 M M2 M3 M4 R C c M5 M0 V SG8 M6 M8 M9 V GS9 M7 I 7 I 20 M23 M22 V GS22 V SG2 M2 :K M20 M25 :K Gain Enhanced Buffer R out K(g m2 g m22 ) 000 K 00 A v (0)=65dB (I Bias =50μA) Note the bias currents through M8 and M9 vary with the signal. M24 R out M26 CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2604 Common Source, Push Pull Buffer with Shunt Feedback To get low output resistance using MOSFETs, negative feedback must be used. Ideal implementation: v iin Gain Amplifier Error Amplifier Error Amplifier M2 i out C L M R L Fig. 7.5A Comments: The output resistance will be equal to r ds r ds2 divided by the loop gain If the error amplifiers are not perfectly matched, the bias current in M and M2 is not defined CMOS Analog Circuit Design P.E. Allen 200

8 Lecture 260 Buffered Op Amps (3/28/0) Page 2605 Low Output Resistance Op Amp Continued Offset correction circuitry: vin M6 C c A V OS Unbuffered op amp VBias M7 Error Loop A2 A M3 A M2 M0 M Fig. 7.6 The feedback circuitry of the two error amplifiers tries to insure that the voltages in the loop sum to zero. Without the M2 feedback circuit, there is no way to adjust the output for any error in the loop. The circuit works as follows: When V OS is positive, tries to turn off and so does A. I reduces thus reducing IM2. A reduction in IM2 reduces IA thus decreasing VGS8A. VGS8A ideally decreases by an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2. CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2606 Low Output Resistance Op Amp Continued Error amplifiers: M3 M4 Cc A VBias M M2 MR MR2 M2A MA VBias A amplifier A M4A A2 amplifier M3A Basically a twostage op amp with the output pushpull transistors as the secondstage of the op amp. Cc2 CMOS Analog Circuit Design P.E. Allen 200

9 Lecture 260 Buffered Op Amps (3/28/0) Page 2607 Low Output Resistance Op Amp Complete Schematic VBiasN M6 C c M M2 M7 MN3 MN4 M3H M4H MP4 M3 M4 MP5 MP3 MR Short circuit protection(max. output ±60mA): MP3MN3MN4MP4MP5 MN3AMP3AMP4AMN4AMN5A R out r ds6 r ds6a LoopGain 50k 5000 = 0 C c A A C c2 MR2 M0 MP4A MN5A M3 M2 M MN4A g m MP3A MN3A M4HA R C C M4A C C g m6 M2A MA A R R L C L VBiasP M3A M3HA Fig. 7.8 CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page 2608 Simpler Implementation of Negative Feedback to Achieve Low Output Resistance M3 M4 200μA 0/ / / 0/ M M2 C L 0/ 0/ / M0 0/ / 0/ M7 Fig. 7.9 R out = (g ds6 g ds7 ) g m2 2g m4 (g m6 g m7 )Ro Output Resistance: R o R out = LG where R o = g ds6 g ds7 and LG = g m2 2g m4 (g m6 g m7 )R o Therefore, the output resistance is: CMOS Analog Circuit Design P.E. Allen 200

10 Lecture 260 Buffered Op Amps (3/28/0) Page 2609 Example 260 Low Output Resistance Using Shunt Negative Feedback Buffer Find the output resistance of above op amp using the model parameters of K N = 20μA/V 2, K P = 25μA/V 2, N = 0.06V and P = 0.08V. Solution The current flowing in the output transistors, and M7, is ma which gives R o of R o = (N P )ma = = 7.43k To calculate the loop gain, we find that g m2 = 2K N 0 00μA = 490μS g m4 = 2K P 00μA = 70.7μS and g m6 = 2K P 0 000μA = 707μS Therefore, the loop gain is LG = ( )7.43 = 9.26 Solving for the output resistance, R out, gives R out = 7.43k 9.26 = 353 (Assumes that R L is large) CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page USE OF THE BJT IN BUFFERED OP AMPS Substrate BJTs Illustration of an NPN substrate BJT available in a pwell CMOS technology: Emitter Base Collector ( ) ;;; n (Emitter) ;; p ;n p ;;; ;; well (Base) ; n substrate (Collector) Fig. 7.0 Base Collector( ) Emitter Comments: g m of the BJT is larger than the FET so that the output resistance w/o feedback is lower Collector current will be flowing in the substrate Current is required to drive the BJT Only an NPN or a PNP bipolar transistor is available CMOS Analog Circuit Design P.E. Allen 200

11 Lecture 260 Buffered Op Amps (3/28/0) Page 2602 A Lateral Bipolar Transistor nwell CMOS technology: It is desirable to have the lateral collector current much larger than the vertical collector current. Triple well technology allows the current of the vertical collector to avoid flowing in the substrate. Lateral BJT generally has good matching. VC Vertical Collector STI STI B n LC E LC p p p nwell Lateral Collector STI Substrate Emitter Base CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page A FieldAided Lateral BJT Use minimum channel length to enhance beta: ßF 50 to 00 depending on the process VC STI B n LC p E LC p p p Keeps carriers from flowing at the surface and reduces /f noise nwell STI Substrate Vertical Collector STI Lateral Collector Emitter Base CMOS Analog Circuit Design P.E. Allen 200

12 Lecture 260 Buffered Op Amps (3/28/0) Page TwoStage Op Amp with a ClassA BJT Output Buffer Stage Purpose of the source follower: M7 M2.) Reduce the output resistance Q0 (includes whatever is seen from vin M M2 the base to ground divided by I Bias F ) C c M3 M4 C 2.) Reduces the output load at the L R L M3 drains of and M7 M Smallsignal output resistance : R out r 0(/g m9 ) ß F = g m0 g m9 (ß F ) Output Buffer Fig. 7. = = 58.3 where I 0 =500μA, I 8 =00μA, W 9 /L 9 =00 and ß F is 00 2K P v OUT (max) = V SD8 (sat) v BE0 = I 8 (W 8 /L 8 ) V t ln Voltage gain: v g m in g m6 g ds2 g ds4 g m9 g ds6 g ds7 g m0 R L g m9 g mbs9 g ds8 g 0 g m0 R L Compensation will be more complex because of the additional stages. I c0 I s0 CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page Example 2602 Designing the ClassA, Buffered Op Amp Use an nwell, 0.25μm CMOS technology to design an op amp using a classa, BJT output stage to give the following specifications. Assume the channel length is to be 0.5μm. The FETs have the model parameters of K N = 20μA/V 2, K P = 25μA/V 2, V TN = V TP = 0.5V, N = 0.06V and P = 0.08V along with the BJT parameters of I s = 0 4 A and ß F = 50. = 2.5V = 0V GB = 5MHz A vd (0) 2500V/V Slew rate 0V/μs R L = 500 R out 50 C L = 00pF ICMR = V to 2V Solution A quick comparison shows that the specifications of this problem are similar to the folded cascode op amp that was designed in Ex Borrowing that design for this example results in the following op amp. Therefore, the goal of this example will be the design of M2 through Q5 to satisfy the slew rate and output resistance requirements. v IN V NB I I 2 M M2 M3 I3 V PB I 4 I 5 M4 V PB2 I 6 I 7 M7 V NB2 M V NB M0 V PB I 2 M2 M3 M4 I 5 R out v O Q5 C CMOS Analog Circuit Design P.E. Allen 200

13 Lecture 260 Buffered Op Amps (3/28/0) Page Example 2602 Continued BJT follower (Q5): SR = 0V/μs and 00pF capacitor give I 5 = ma. Assuming the gate of M4 is connected to the gate of, the W/L ratio of M4 becomes W 4 /L 4 = (000μA/25μA)60 = 280 W 4 = 640μm I 5 = ma /g m5 = V/mA = 25.8 MOS follower: To source ma, the BJT requires 20μA (ß =50) from the MOS follower (M2M3). Therefore, select a bias current of 00μA for M3. If the gates of M3 and M3 are connected together, then W 3 /L 3 = (00μA/00μA)5 = 5 W 3 = 7.5μm To get R out = 50, if /g m5 is 25.8, then design g m2 as g m5 = g m2 (ß F ) = 24.2 g m2 = (24.2)(ß F ) = = 80μS g m2 and I 2 W/L = W 2 = 5μm CMOS Analog Circuit Design P.E. Allen 200 Lecture 260 Buffered Op Amps (3/28/0) Page Example 2602 Continued To calculate the voltage gain of the MOS follower we need to find g mbs9 ( N = 0.4 V). g m2 N g mbs2 = = 2 2 F V BS = 58μS where we have assumed that the value of V SB2 is approximately.25v 0.7V = 0.55V. 80μS A MOS = 80μS58μS6μS8μS = The voltage gain of the BJT follower is 500 A BJT = = 0.95 V/V Thus, the gain of the op amp is A vd (0) = (3,678)(0.825)(0.95) = 2,885 V/V The power dissipation of this amplifier is, P diss. = 2.5V(25μA25μA00μA000μA) = 3.375mW The signal swing across the 500 load resistor will be restricted to ±0.5V due to the 000μA output current limit. CMOS Analog Circuit Design P.E. Allen 200

14 Lecture 260 Buffered Op Amps (3/28/0) Page SUMMARY A buffered op amp requires an output resistance between 0 R o 000 Output resistance using MOSFETs only can be reduced by, Source follower output (/g m ) Negative shunt feedback (frequency is a problem in this approach) Use of substrate (or lateral) BJT s can reduce the output resistance because g m is larger than the g m of a MOSFET Adding a buffer stage to lower the output resistance will most likely complicate the compensation of the op amp CMOS Analog Circuit Design P.E. Allen 200