Advantages of e-mmc 4.4 based Embedded Memory Architectures

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1 Embedded NAND Solutions from 2GB to 128GB provide configurable MLC/SLC storage in single memory module with an integrated controller By Scott Beekman, senior business development manager Toshiba America Electronic Components, Inc. As NAND Flash continues to increase in density and decrease in cost per gigabyte, it has enabled more cost-effective storage in digital cameras, audio players and the latest mobile phones, as well as a growing list of new applications. However, the progression to the ever-smaller process geometries used to achieve the latest high density memory solutions has also increased the complexity of designing NAND into a system. To minimize development requirements and ease integration into system designs, embedded memory solutions with an integrated controller to offload the NAND management functions from the host processor have been developed. The most popular embedded high density mobile storage solution with an integrated controller is the JEDEC standard e-mmc, derived from the MultiMedia Card standard. e-mmc modules incorporate one or many multi-level cell (MLC) NAND die stacked together with a controller that has an MMC interface and manages the errorcorrection code (ECC), wear leveling and block management requirements of the MLC NAND die, relieving the host processor of these tasks. Figure 1: e-mmc Modules using multiple thin die stacking technology packaged with a controller for NAND management help simplify design-in of NAND flash in embedded applications.

2 Page 2 of 7 Applications One of the first major applications for e-mmc has been mobile phones, where the need for both code storage and large capacity user data storage for audio, video and other data has driven the development of the latest JEDEC standards for e-mmc. Additional applications incorporating e-mmc include digital video cameras and digital still cameras, ebooks, netbooks, GPS systems, printers, set top boxes, tablets, and servers, to name a few. e-mmc 4.4 Enhancements Figure 2: e-mmc Embedded NAND flash modules provide a single component solution packaged with a powerful e-mmc controller to offload NAND management functions from the host processor With the introduction this year of a new JEDEC standard for e-mmc, version 4.4, new memory architectures can be implemented more easily to reduce cost and potentially reduce package height or board space. The new standard supports new security features including increased write protection management, a new secure-access controlled memory block, plus Secure Erase and Secure Trim functions for data erase operations. These features help protect code and OS from malicious access and enable complete removal of data from physical memory so that sensitive personal information, for example, can be securely erased as desired. In addition, the new e-mmc version 4.4 standard allows for the NAND memory to be divided into more partitions, as programmed by the host controller (one time programmable). As we see in the example of figure 3, the NAND manufacturer may enable some partitions to be SLC, MLC, or the NAND memory can be programmed as either SLC or MLC by the host controller.

3 Advantages of e-mmc 4.4 based Embedded Memory Architectures Page 3 of 7 Figure 3: MultiPartitioning Feature in e-mmc 4.4 Compared to e-mmc 4.3 shown at the left, the latest generation provides more flexibility in partitioning memory areas as SLC. An additional four general-purpose (GP) blocks can be configured by the system manufacturer as SLC NAND or MLC NAND. A Replay Protected Memory Block (RPMB) area allows a portion of memory to be accessed with a hidden security key or trusted security function, providing secure storage for the host to protect crucial programs or data, as well as enable copy protection. Those areas requiring better reliability are SLC or can be programmed as SLC. The Boot Area, which stores the boot code, and the Enhanced User Data Area, which may store, for example, system log files, are SLC. The User Data Area, which may store music, pictures, videos and other files is MLC. There are four general-purpose areas that can be configured as SLC or MLC as the system manufacturer desires, with no limit to the proportion that can be configured as SLC up to almost the full density of the e-mmc. Each 1 bit configured as SLC results in 2 bits less of MLC. Theoretically an 8GB[1] e-mmc device (densities are defined in MLC terms), could be configured virtually all as SLC and thus would be approximately 4GB. In most cases, it is more likely that the majority of the memory would be configured as MLC to support higher density. Evolution of Memory Subsystem Architectures Using GB class phones as an example, conventional embedded NAND based memory architectures generally incorporated Low Power (LP) SDRAM die for working memory and SLC NAND die for code storage packaged together in a multi-chip-package (MCP), or alternatively in a package-on-package (POP) which is then stacked on a processor to save board space. DRAM densities typically ranged from 256Mbit to 4Gbit and SLC NAND from 512Mbit to 8Gbit. In the last year or two, e-mmc modules have become a popular addition to provide high capacity user data storage.

4 Page 4 of 7 Today, GB class mobile memory architectures typically fall into two categories as reflected in Figure 4. Figure 4: Traditional Mobile Phone Memory Architectures with e-mmc In case (2), e-mmc is incorporated within the MCP/POP along with LP SDRAM and SLC NAND. The benefit of this is to save board space. When combined as one MCP chip, this solution has only one footprint, or in the case of POP, takes no additional board space when stacked on a processor if the processor can support POP. Limitations with case (2) are that the maximum e-mmc storage density supported may be limited. For example, in the case of POP where memory package heights are constrained, and therefore the number of memory die that can be stacked are limited, only 4 or 8GB of e-mmc may be supported. In case (1), greater flexibility may be realized to support a variety of e-mmc storage densities more easily, although this solution adds an additional footprint relative to case (2). e-mmc has relativity few flavors by density, each supporting a common 169ball JEDEC standard footprint. In comparison, the variety of combinations of LP SDRAM + SLC NAND MCP/POP can be many based upon different DRAM and NAND densities, organizations, interfaces such as DDR vs. SDR, or other specifications. As a result, by keeping e-mmc as a separate chip, it is much easier to migrate from one density to another, to offer multiple product SKUs, or to make last minute development adjustments in densities based upon changing market needs. It may also lead to a lower priced solution as each chip can be negotiated separately with suppliers optimally suited to support each solution. And potentially lower inventory risk may be achieved as the e-mmc portion of the overall memory is less customized than if it were combined with LP SDRAM and SLC NAND.

5 Page 5 of 7 One of the major benefits of e-mmc Ver. 4.4 for embedded memory architectures is that the need for a separate SLC NAND die can be eliminated as a result of SLC/MLC partitioning, so only LP SDRAM and e-mmc are required. Thus, new GB class mobile memory architectures can be developed as shown in Figure 5. Figure 5: Mobile Phone Memory Architecture without Discrete SLC NAND. The tradeoffs between (1) and (2) are similar to those mentioned previously. The removal of the SLC NAND die provides additional advantages in addition to reduced cost. In case (1), LP SDRAM can now be supported as a single package as a discrete device or stacked on a processor as POP. Being less customized results in lower inventory risk, and enables more options for sourcing. For case (2), even when LP SDRAM is combined with e-mmc, this is still a less customized solution than if SLC NAND were included. Choosing the Right e-mmc Capacity When determining how much board space to layout for the memory package containing the e- MMC, there is a tradeoff that needs to be considered between cost and board space. From a cost perspective, it is generally better to have fewer stacks of larger density NAND dies, than more stacks of smaller density NAND dies. For example, 16GB of e-mmc supported by stacking four 32Gbit dies would be less expensive than stacking eight 16Gbit dies. But since a larger NAND die requires more space, the minimum package size that can support a 32Gbit die is larger than that supporting a 16Gbit die.

6 Page 6 of 7 Today, the high volume, cost effective MLC NAND die density is 32Gbits. Thus, densities from 4GB to 64GB are most cost effectively supported by stacking from 1 to 16 die of 32Gbit MLC NAND. Since these are stacked in a staircase fashion so that the leads can be connected to each die, as opposed to simply placing one die on top of another, it means the minimum package size supporting 64GB e-mmc would be larger than that of a 4GB e-mmc. The fact that so many e-mmc densities can be supported by the same 32Gbit MLC NAND die has Figure 6: Internal Side View of 16 NAND die stacked with controller in e-mmc module. important implications for lower density e-mmc such as 1GB or 2GB. Lower density e-mmc will utilize MLC NAND die which is not the mainstream density (8Gbit or 16Gbit), and therefore suffers from lower supply volumes and economies of scale relative to the 32Gbit MLC die used in 4GB and larger e-mmc. Toshiba has also developed the first 128GB e-mmc module by stacking sixteen 64 gigabit (8GB) die, achieved through innovative thinning and layering technologies to achieve individual chips that are less than 30 microns thick. See Table 1 below for available densities from 2GB to 128GB, with part numbers and package sizes, and Table 2 for an overview of product specifications. Table 1. Toshiba 32nm e-mmc Lineup Capacity Package Part Number 2GB* 11.5x13x1.2mm Samples ES Nov 10 4GB* 12x16x1.2mm Samples ES Nov 10 8GB 12x16x1.2mm THGBM2G6D2FBAI9d 16GB 12x16x1.2mm THGBM2G7D4FBAI9 32GB 12x16x1.4mm THGBM2G8D8FBAIB 64GB 17x22x1.4mm THGBM2G9D8FBAIF 128GB 17x22x1.4mm THGBM2T0DBFBAIF * 2/4GB currently supported in 43nm (Ver4.3) 12x16x1.3 Pkg (2GB: THGBM1G4D1EBAI7, 4GB: THGBM1G5D2EBAI7)

7 Page 7 of 7 Table 2. Toshiba 32nm e-mmc Product Specifications Interface Voltage Bus Width Write Speed 2 Read Speed 2 Operation Temp Package MMCA Version 4.4 HS-MMC 2.7V 3.6V (Memory Core) 1.65V 1.95V/2.7V 3.6V (Interface) x1/x4/x8 Typ. 21MB/s (Interleave, SDR/DDR function) Typ. 46 MB/s (Interleave, SDR for 64GB) Typ. 55 MB/s (Interleave, DDR for 64GB) -25 degree C to +85 degree C JEDEC Standard Summary With the introduction of e-mmc version 4.4, new partitioning and security features are available, and SLC NAND die can be removed enabling lower cost, while potentially reducing package height or board space. This approach has become popular in Smartphones and high-end mobile phones and may be applicable in a wide variety of additional applications. Tradeoffs need to be considered between board space and supply flexibility, and therefore potentially overall supply and inventory costs, when determining whether to combine LP SDRAM and ver4.4 e-mmc in one package or to keep them separate. 1 Product density is identified based on the maximum density of memory chip(s) within the Product, not the amount of memory capacity available for data storage by the end user. Consumer-usable capacity will be less due to overhead data areas, formatting, bad blocks, and other constraints, and may also vary based on the host device and application. 2 Transfer rate: For purposes of measuring read and write speed in this context, 1 Megabyte or MB = 1,000,000 bytes. Read and write speed may vary depending on the controller, read and write conditions, such as file sizes you read and/or write. Information in this article including product details and specifications, content of services and contact information is current and believed to accurate as of the data of publication, but is subject to change without prior notice. Technical and application information contained here is subject to the most recent applicable Toshiba product specifications. In developing designs, please ensure that Toshiba products are used within specified operating ranges as set forth in the most recent Toshiba product specifications and the information set forth in Toshiba s Handling Guide for Semiconductor Devices, or Toshiba Semiconductor Reliability Handbook. This information is available at or from your TAEC representative. All trademarks are the property of their respective owners Toshiba America Electronic Components, Inc. (9/10 v1)