High Speed Inter-chip Signaling in CMOS

Transcription

1 High Speed Inter-chip Signaling in CMOS Area Exam Jim Goodman May 5, 2000

2 The Problem Moore s Law and Rent s Rule Speed & functionality double every 18 months Pin bandwidth not growing as quickly [Dally97] Np = K p Ng β = 7 Ng 0.2 High speed communications require Gb/s High Speed Inter-chip Signaling in CMOS 2/31

3 Paper Selection & Overview A 700 Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers [Sidiropoulos97] A 0.5 µm CMOS 4-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling [Yang98] A 900 Mb/s Bidirectional Signaling Scheme [Mooney95] A 0.4µm CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter [Farjad-Rad99] High Speed Inter-chip Signaling in CMOS 3/31

4 High Speed Signaling Overview binary data stream Tx termination Transmission Medium termination Rx binary data stream bits voltages voltages voltages voltages bits Serial links speed is everything timing information embedded in signal stream willing to tolerate latency, area, and power Parallel links minimal overhead bundled timing information High Speed Inter-chip Signaling in CMOS 4/31

5 Transmission Lines & Termination Z 0 (ω) Very high edge rates and frequencies lumped impedance models become distributive x Rdx Ldx Cdx Gdx x+dx Z 0 ( ω) = R + jωl G+ jωc Impedance discontinuities create reflections use termination to eliminate Z 0 I f I r Z 1 Z 0 I r = I Z 1 + Z 0 f Parallel and series terminations Z 1 L --- C High Speed Inter-chip Signaling in CMOS 5/31

6 Terminating the Termination Discussion... On vs. off chip termination off-chip components more precise off-chip leaves unterminated stub of package Active termination (e.g., [DeHon93]) requires calibration phase additional area/power/complexity much more accurate than passive termination term 3 term 2 term 1 term 0 1x 2x 4x 8x R on R equiv = term 3:0 R on High Speed Inter-chip Signaling in CMOS 6/31

7 Signaling Modes Voltage mode (VM) low impedance data data R term out Current mode (CM) high impedance data R term R term out out data Advantages Disadvantages VM CM No static power dissipation Less power than CM Simple driver structures Good supply noise immunity Current summing is very simple (and useful!) Vulnerable to supply noise Series termination slow (multiple time of flights) Requires parallel termination Dissipates static power Requires source termination High Speed Inter-chip Signaling in CMOS 7/31

8 Signaling Schemes How is reference provided to the Receiver? Single-ended minimum # of wires VERY susceptible to noise d in ref d out Differential very good noise immunity twice as many wires d in d out Pseudo-differential good noise immunity wiring overhead amortized d in,0 d in,n-1... ref dout,0 d out,n-1 High Speed Inter-chip Signaling in CMOS 8/31

9 Bidirectional Signaling {a i } Tx Tx {b i } Z 0 {b i } Rx Rx {a i } Tx Tx Z 0 Z 0 Fully-duplexed communication halves the number of wires Cancellation of Tx signal is difficult must terminate line at both ends jitter, skew, noise all affect cancelation slower than two equivalent unidirectional links High Speed Inter-chip Signaling in CMOS 9/31

10 Noise and Inter-Symbol Interference (ISI) Proportional vs. Fixed Sources of Noise V N = V fixed + k prop V swing fixed sources overcome with increased SNR proportional sources require careful design to manage ISI makes it difficult to correctly decode channel memory coupling effects between channels High Speed Inter-chip Signaling in CMOS 10/31

11 Basic Transmitter Design bit stream Transmitter Encoder Synchronizer Pre-driver Tx TxClk termination Translate bitstream into voltage pulses perform channel coding (e.g., ECC) encode timing information (e.g., 8b/10b code) Bandwidth limited signaling finite slew rate: low swing signaling low swing signaling lowers power/noise Reference generation (pseudo-differential) High Speed Inter-chip Signaling in CMOS 11/31

12 Transmitter Multiplexing Combine N slow streams into one fast stream f select = N f in N input streams at f in... f out = N f in RC of multiplexor output limits speed place at Tx output out out out d 0 /d 0 Φ 0 Φ 1 d 1 /d 1 Φ 0 d 0 d 1 d 0 d 0 d 1 d 1 Φ 1 High Speed Inter-chip Signaling in CMOS 12/31

13 Improved Transmitter Multiplexing Multiplexor pulse width may limit performance use overlapping clocks to qualify output d clk Φ 0 1 q out out 1 Φ 1 out d 0 /d 0 d 1 /d 1 Φ 0 d 0 d 1 d 0 d 0 d 1 d 1 Φ 2 Φ 2 Φ 1 Φ 1 Φ 1 Φ 2 Requires finely-spaced, well controlled clocks low jitter PLL s and clock drivers High Speed Inter-chip Signaling in CMOS 13/31

14 Basic Receiver Design refclk TxClk Synchronizer (PLL/DLL) RxClk S/H Regenerative Amplifier received bitstream Clocked Comparator Performance limited by clocks & comparator low jitter PLL/DLL (t jitter ) fast comparator w/small aperature (t aperture ) t bit Comparator Offset Reduced Eye Height t jitter t aperture t jitter High Speed Inter-chip Signaling in CMOS 14/31

15 Receiver Demultiplexing Relaxes timing constraints of comparator still require small aperture time Φ 0 in d0 d1 d2 d3 d4 d5 d6 Comp out 0 Φ 0 Φ 1 Φ 1 in C in = 4C comp Comp Comp Comp Φ 2 Φ 3 out 1 out 2 out 3 Φ 2 Φ 3 out 0 out 1 out 2 out 3 d0 d1 d2 d3 d4 d5 d6 Requires finely-spaced, well-controlled clocks Increased input capacitance may limit performance, introduce ISI High Speed Inter-chip Signaling in CMOS 15/31

16 Synchronization & Clock Phase Generation PLL vs. DLL DLL is unconditionally stable, no phase acc. PLL can generate frequency multiples Phase generation tapped ring oscillator or delay line phase interpolation (~2% error [Yang98]) V ctrl φ interpolator φ interpolator φ interpolator φ interpolator Φ 7 Φ 1 Φ 3 Φ 5 Φ 0 Φ 2 Φ 4 Φ 6 High Speed Inter-chip Signaling in CMOS 16/31

17 Paper #1: [Sidiropoulos97] 1V local clk clk data 0 dt DLL sample clk datap 0 data n dt dt datan 0... datap n-1 1V dt datan n-1 V ref 700 BER < 10-14, V dd = 3.3V Series terminated VM External 1V supply Pseudo-differential 2:1 Tx multiplexor 300mW 3.3V DLL-based synchronization Low jitter ECL local Rx clk 2:1 Rx demultiplexor Duty cycle adjustor High Speed Inter-chip Signaling in CMOS 17/31

18 Current Integrating Receivers Single sample/bit susceptible to noise events low pass filter noise using current integration noise event must be longer than t bit /2 Integrate V = V data,i - V ref over entire bit time sign of result gives symbol (+ve = 1, -ve = 0) Integrate using current steering to dump charge on matched capacitors Φ C C Φ V out V High Speed Inter-chip Signaling in CMOS 18/31

19 Current Integrating Receiver Problems... Integrating over periods of low SNR lowers average SNR reducing t int equivalent to conventional methods t int t int t jitter/skew high SNR Previous symbol contribution Jitter introduces ISI integration includes previous/next symbol Approximates matched filtering as integrator impulse response matches wideband pulse shape High Speed Inter-chip Signaling in CMOS 19/31

20 Paper #2: [Yang98] Conventional data recovery utilizes PLL slow response leads to jitter accumulation Oversampling data recovery via phase picking feedforward so it is fast and can track jitter improves performance 4 BER < 10-14, V dd = 3.3V Parallel terminated CM 170 mv diff. swing Fully differential 8:1 Tx multiplexor PLL-based synchronization 3x oversampling of Rx data Phase picking decoder 1:8 Rx demux (+ 1:2 logic) V V High Speed Inter-chip Signaling in CMOS 20/31

21 Oversampling Data Recovery clk ref Clock Generator sclk 23:0 Phase Picking Decoder Phase Detect/Filter sample select data data in Multi-phase Data Receiver/Sampler Delay data out transition best sample transition 3x oversampling of each bit 24 equally-spaced clock phases requires finely-spaced, well-controlled clocks Use pairwise XOR to find transitions Look for equally spaced transitions across 3 byte sliding window choose sample furthest away from transition High Speed Inter-chip Signaling in CMOS 21/31

22 Oversampled Data Recovery Problems... Phase error due to quantization SNR penalty offsets benefits of fast jitter tracking Large area/power/latency overhead ~100% area penalty? ~33% of system power is decision logic! still need good Rx PLL to generate phases Authors ultimately admit PLL design is better approach limited to high jitter environments basically, the worse your PLL, the better it is! High Speed Inter-chip Signaling in CMOS 22/31

23 Paper #3: Bidirectional VM-based Signaling da in Z 0 Z 0 Z 0 db in instantiated 16 times V rx,b instantiated 16 times db out da out V ref,b Vref H = 3/4 V dd Vref L = 1/4 V dd z 0 z 0 Vref H = 3/4 V dd Vref L = 1/4 V dd da in,db in V rx,b V ref,b V rx,b - V ref,b da out /4V dd -1/4V dd /2V dd 3/4V dd -1/4V dd /2V dd 1/4V dd 1/4V dd V dd 3/4V dd 1/4V dd 1 High Speed Inter-chip Signaling in CMOS 23/31

24 Notes & Issues (where to begin...) Very few details given (in particular no # s)... Self-series terminating drivers eliminates additional power dissipation in R term Authors completely ignored dynamic power given large swing (> 3V?), it s significant no mention of static power in references either Very sensitive to mismatches local supply voltage used as reference driver impedances (sets middle reference) utilizes adaptive impedance control to offset High Speed Inter-chip Signaling in CMOS 24/31

25 Paper #4: [Farjad-Rad99] Attenuation of high frequencies in wires dielectric absorption skin effect: R f f s introduces ISI, limits performance [Dally97] Compensate for channel response using Tx/Rx equalization attenuate low frequencies lowers SNR, opens eye [Farjad-Rad99] High Speed Inter-chip Signaling in CMOS 25/31

26 Transmitter Pre-distortion & 4-PAM Utilize multi-level signaling to increase bit/sym 4-PAM: 2 bits/symbol 2-bit DAC to generate signals 2-bit ADC to resolve signals (not described...) Current mode DAC binary-weighted current sources current summing output combines sources Implement 3-tap Tx FIR to compensate channel exploit current summing to simplify circuit can t do equalization in the receiver... yet! High Speed Inter-chip Signaling in CMOS 26/31

27 [Farjad-Rad99] Transmitter Design shunt peaking bondwire inductor R term Dout/Dout Φ i = Clk i /Clk i+1 Dout/Dout D 0 /D 0 Clk i /Clk i+1 D 1 /D 1 1X 2X D/D 1:0 Φ 0 Φ 1 Φ 2 Φ 3 DAC MAIN 200ps DAC FIR1 200ps DAC FIR2 200ps DAC FIR3 Φ 1:4 Φ 2:5 Driver #2 Driver #3 Φ 3:6 Φ 4:7 Driver #4 D/D 3:2 D/D 5:4 D/D 7:6 D/D 9:8 Driver #5 Switched current steering logic Driver #1 5:1 Tx multiplexor 4 branches per leg external Iref s for FIR 3.3V Iref 1 Iref 2 Iref 3 8 clocks + complements 5 Gsymbols/s, 10 Gb/s duty cycle adjustment Large output capacitance 20 branches at output! (1.4 pf, 35 ps) utilize shunt peaking to extend bandwidth (1.8x) High Speed Inter-chip Signaling in CMOS 27/31

28 Discussion No one paper addresses all aspects of the system all systems have their problems [Sidiropoulos97] most efficient (101 pj/bit) serial links only 3-4x more energy per bit Proper choice depends on requirements solution for every situation Signalling at 1-5 Gb/s appears straightforward differential current-mode signalling on-chip adaptive termination hard decision decoders low jitter PLL/DLL and VCO High Speed Inter-chip Signaling in CMOS 28/31

29 Future Directions & Open Problems Next level requires careful consideration of the channel limitations frequency dependant attenuation some form of equalization required Synchronization requirements are likely to be the biggest implementation problem reduce symbol rate to relax time constraints increase bits/symbol to restore bandwidth Use bandwidth more efficiently via multi-level signaling and channel coding soft decision decoders [Black97] multi-bit ADC s at Gsample/s [Ellersick00] High Speed Inter-chip Signaling in CMOS 29/31

30 It s just a bandlimited channel... Past abstraction of a high SNR, wideband channel no longer applies exploit techniques used in existing bandlimited communication systems modems (getting 56 kbps from 3 khz channel) Still alot of work to be done on required building blocks high speed, low resolution ADCs high speed soft decision decoders receiver equalization schemes Only real limit is Shannon s Limit High Speed Inter-chip Signaling in CMOS 30/31

31 References W.J. Dally, et. al., Multi-gigabit signaling with CMOS, IEEE/LEOS 8th Workshop on Interconnections Within High-Speed Digital Systems, May 12, S.Sidiropoulos and M. Horowitz, A 700 Mb/s/pin CMOS signaling interface using current integrating receivers, JSSC, May C.K. Yang, et. al., A 0.5µm CMOS 4.0-Gbit/s serial link transceiver with data recovery using integrating receivers, JSSC, May R. Mooney, C.Dike, and S. Borkar, A 900 Mb/s bidirectional signaling scheme, JSSC, December R. Farjad-Rad, et. al., A 0.4µm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter, JSSC, May A. DeHon, T. Knight, and T. Simon, Automatic impedance control, ISSCC 93, February 1993 W.J. Black and T.H. Meng, A 1-Gb/s, four state, sliding block viterbi decoder, JSSC, June W. Ellersick et. al., GAD: 12 GS/s/ CMOS 4-bit A/D converter for an equalized multi-level link, 1999 IEEE Symposium on VLSI Circuits, June High Speed Inter-chip Signaling in CMOS 31/31