DRM compatible RF Tuner Unit DRT1

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1 FEATURES DRM compatible RF Tuner Unit DRT1 High- Performance RF Tuner Frequency Range: 10 KHz to 30 MHz Input ICP3: +13,5dBm, typ. Noise full gain: 14dB, typ. Receiver Factor: -0,5dB, typ. Input Impedance: 50 Ohms 12 khz IF output: 1,5Vpp, max. Single-Supply Operation: 220mA, typ. 8pol. Crystal Filter 45,0 MHz BW: 10 khz LO: 14 Bit DDS tuning steps < 1mHz Long Time Frequency Stability: 5ppm/ 5 years High stability of Gain Control Reference Voltage Output: 2,5V Highest gain independent Linearity Long Lifetime due to lack of Electrolytic Capacitors Small geometrical Dimensions APPLICATIONS High-End DRM and HD Radio Receivers Observation and Monitoring Receivers Measurement Receivers Amateur radio Receivers 1

2 PRODUCT DESCRIPTION The DRT1 is a high- performance RF- tuner unit with an input frequency ranging from 10 KHz to 30 MHz. It was designed for software defined receiver concepts using an A/D conversion at the 2 nd IF output at 12kHz standard. So a PC standard soundcard may be used as A/D converter by example. Other customer specific IF output frequencies than 12 KHz, up to 2 MHz, are easy to implement on request. High selection is provided by means of an 8 pol. crystal filter at 1 st IF. The standard bandwidth is 10 khz, other customer specific bandwidths are easy to implement on request. The strong linear output peak level together with levelling to high dynamic reserve allows bandwidth tuning by DSP after A/D conversion. The use of a high level 1 st mixer in combination with high linear gain control stages and amplifiers provides an excellent over all linearity at all gain values and temperature stability of gain. Low narrowband phase noise of the 14 bit DDS provides compatibility to new digital modulations like DRM or HD Radio with high decoder SNR. For measurement application it is recommended to use the on board reference voltage for VGC generating together with an additional D/A converter. This provides high gain accuracy. The gain response over receiving frequency is very flat. The board layout is designed for direct soldering to a back- plane PCB. ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION RF_IN Maximum Input Power 15 dbm 5P_IN Quiescent Supply Voltage. +5,5V All other Inputs IOUPD, SDIO, RESET SCLK, VGC_IN.. +5,5V Operating Temperature Range. 20 to +75 C Storage Temperature Range. -65 C to +100 C All outputs are short circuit protected. BOARD DIMENSIONS 72mm x 57mm x 8,5mm DIMENSIONS OF LAND PADs 2

3 ELECTRICAL SPECIFICATIONS Parameter Temp. Min Typ Max Unit Receiving Frequency Range Full 0,01 30 MHz Input Impedance 25 C 50 Ohms Input f =10,0 + 10,1 MHz 2x C +13,5 dbm dbm ; 9,9 MHz Noise Figure full gain 25 C 14 db LO Phase 1 KHz offset 25 C dbc Receiver Faktor (ICP3-F) 25 C -0,5 dbm IM free dynamic range (3KHz BW) db DDS Spurious mixing attenuation* 25 C 65 db Inband Intermodulation 2 nd order 25 C see Figure 7 at page 6 Inband Intermodulation 3rd order 25 C see Figure 7 at page 6 Maximum 4,2V VGC 25 C db Minimum 0,3V VGC 25 C -5 0 db DRM- Sensitivity at 15 db SNR 25 C ,2 1,8 DRM- Performance (max. SNR) 25 C db IF 1 db Full 5 8 KHz IF 6dB Full KHz IF 30 db Full KHz IF 85 db Full KHz Current Consumption Full P_IN = 5,0V Logic Inputs 1 Voltage 25 C 2,2 V Logic Inputs 0 Voltage 25 C 0,8 V Logic 1 Current 25 C 3 12 µa Logic 0 Current 25 C 12 µa Maximum of linear IF output swing 25 C 1,5 Vpp Reference Voltage at VREF_OUT 25 C Full Frequency Accuracy Additional over temperature range Additional aging 25 C Full 25 C 2,45 2,5 2, , dbm (true rms) µv absolute V ppm/ C ppm ex factory ppm absolute ppm /5years * A theoretical value, only measurable by chance, that a DDS spurious and a strong input signal have a difference of exact 45 MHz (1 st.if) or the spurious falls into the 45 MHz filter curve. Otherwise no mixing products or birdies by DDS-spurious are measurable. Calculated from DDS Spurious specs worst case. Fax: +49 3

4 PIN FUNCTION DESCRIPTIONS Pin Name Function 1 RF_IN Antenna Input 50 Ohms ; Maximum Input Power +15 dbm; DC- shorted to GND by low pass coils and input transformer 2 AGND Ground Pin for 50 Ohms Antenna Input 3 AGND Ground Pin for signal VGC_IN 4 VGC_IN Gain Control Input Voltage. DC input resistance approx. 10 KOhms; operating range 0,3V to 4,2V. Gain Scale Factor approx. 25 db/v. Internal low pass 1 st order 0,5 ms. VGC have to be free of noise and spikes, otherwise danger of AMmodulation of the IF output signal! 5 IF_OUT Output of the 12 KHz IF. Source Impedance approx. 500 Ohms DC free by internal coupling capacitor. Maximum of linear output swing 1,5Vpp. Load impedance should be more than 10 KOhms. 6 AGND Ground Pin for IF Signal IF_OUT 7 AGND Ground Pin for supply voltage 8 5P_IN Supply Voltage +4,75 to +5,25 Volts; current consumption max. 250mA; typ. 220mA. The supply voltage have to be stabilised and free of noise and spikes. 9 VREF_OUT Reference Voltage output +2,5V for external use (by example for VGC- DA/- converter). Decoupled by internal serial resistor 470 Ohms. NC, if not used. 10 RESET DDS- Reset Input. External Reset only needed before 1 st tuning data telegram if the rise time of power supply voltage is longer than 1ms. Normally the power rise resets the DDS by internal capacitor to 5P_IN. 11 SCLK This pin functions as the serial data clock for I/O operations of DDS AD9951. Decoupled by 1KOhms serial resistor. 5V CMOS level. 12 SDIO Serial data input of DDS AD9951; also bi-directional I/O, if configured. Decoupled by internal 1KOhms serial resistor. 5V CMOS level. 13 DGND Separate Digital Ground Pin, only when BR1 is desoldered. By soldered BR1 internal connected to AGND. NC if BR1 is soldered. 14 IOUPD Update Input of DDS AD9951; the rising edge transfers the contents of the internal buffer memory to the I/O registers. Decoupled by internal 1 KOhms 15, 16, 17, 18 AGND serial resistor. 5V CMOS level. Additional ground pins for mechanical stabilisation at the back plane. 4

5 TYPICAL PERFORMANCE CHARAKTERISTICS Figure 1: Response of Input Reflection Figure 2: Frequency tracked over all Receiver Gain Response at fixed VGC Figure 3: Top of the over all Bandwidth Curve Figure 4: Over all Bandwidth Curve 5

6 Gain [db] F[dB] VGC [V] Figure 5: VGC- Gain- Curve Gain [db] Figure 6: Gain dependence of Noise Figure Figure 7: Over all inband IMD 2 nd and 3 rd order in dependence of 2- tone input level; VGC tracked to 1 Vpp output level 6

7 7

8 APPLICATION ADVICES For first tuning tests use our evaluation and tuning software module V1.1 or later. This tuning software runs under WINDOWS systems and works together with the RS232- CMOS level converter MC1489 (ON Semiconductor ), wired like shown in the test circuit. It is available for free download at our web pages (www.sat-schneider.de). For your own implementations please refer to the AD9951 datasheet (www.analog.com). The following parameters and DDS- presettings are recommended: FCLK = 45,012 MHz; CLK multiplier = 8 ; Charge Pump Current = 150µA flo = fin + 45,0 MHz On request we offer the well-commented software sources. This could be helpful in fast implementation of customer specific systems. Be aware, that the used MC1489 inverts the logic levels! An AGC circuit is not included on the board because software defined AGC loop is recommended using a 5V D/A- converter. If hardware AGC loop is needed, however, figure 8 shows a simple tested hardware AGC circuit. Adjust the AGC level that way, that the maximum of 12 KHz IF output swing is not more than 0,5Vpp at all kinds of modulation. So enough dynamic headroom is sure. Respect by adjustment, the crest factor of a DRM signal is 10 db! For wideband applications (AM, NFM, DRM) one AGC loop is sufficient. For narrowband applications (CW, SSB, FSK) with a following narrowband DSP software filter two AGC loops are necessary. The 1 st. loop has to detect the full 10 KHz IF bandwidth and acts to the VGC_IN of the tuner board. The 2 nd loop detects only the small bandwidth after the DSP software filter and has to control the AF output level at D/A conversion. This makes sure, that an overdrive of tuner stages and/ -or A/D converter by strong signals inside the 10 KHz tuner bandwidth but outside the DSP filter bandwidth is prevented. For measurement applications a steady AGC loop is not recommended, because the VGC- gain curve is not strong db -linear. But the curve is stabile. Here a gain switching in db steps is recommended. One calibration table for the db gain steps (by example 2; 5; or 10 db steps) is sufficient because the gain response over receiving frequency is very flat (see figure 2). For high-speed measurements it is necessary to decrease the internal VGC filter capacitor of 4µ7 to lower values. This increases the request to the noise level of the VGC voltage. Also for measurement applications an additional 50 Ohms jack for RF_IN is prepared. The jack type MCX can be placed at the board on request. In precision devices it is recommended to use the separate digital ground option. Desolder BR1 and connect pin 13 (DGND) with the separate digital ground of the final device. Be sure, that the digital ground and the analog ground of the final device is connected together outside tuner board at only one point. Attention! Power up of the DRT1 without connection between AGND and DGND is forbidden. Otherwise danger of damage will occur! The excellent linearity from RF input to IF output shows Figure 7. The IF output level was kept constant to 1Vpp by VGC at several 2-tone input levels. The 2- tone carriers falls inside the crystal filter curve, also the IMproducts 2 nd and 3 rd order. IMD2 was measured at 9 KHz carrier spacing and IMD3 was measured at 2 KHz carrier spacing. Due to the low noise figure the tuner works without input attenuator in front of the 1 st mixer. The achived input ICP3 of more than +13 dbm is a very good value despite using only a 5V power supply. By use of long wire antennas (over 10m long) an additional input attenuator or a preselector could be helpful at nighttime, however in detecting of weakest amateur radio signals. For broadcast applications it is not required. A reflow soldering of DRT1 to the back plane is possible. The temperature profile depends of back plane structure, however, and has to be defined by the final customer. An additional TCXO fine-tuning is recommended after reflow process. Soldering by hot spot or by soldering iron should be favoured. Fax:

9 Figure 8: Hardware AGC circuit ESD CAUTION ESD (electrostatic discharge) sensitive device. Permanent damage may occur on the device subjected to high energy electrostatic discharges. Therefore proper ESD precautions are recommended for handling, testing and production process of final device. Specifications subject to change without notice. Trademarks and registered trademarks are the property of their respective owners. Fax:

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