Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc

Size: px

Start display at page:

Download "Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc"

Vincent Shepherd
8 years ago
Views:

2 Disclaimer Presentation Disclaimer: All opinions, judgments, recommendations, etc. that are presented herein are the opinions of the presenter of the material and do not necessarily reflect the opinions of the PCI-SIG. Copyright 2015, PCI-SIG, All Rights Reserved 2

that are presented herein are the opinions of the presenter of the

3 Agenda PCIe Base vs CEM Tx testing Testing Challenges in Tx and Rx Automation to Simplify Tx Testing Automatic Calibration Essential for Rx Testing Effective Instruments for PLL Testing Getting Ready for PCIe 4.0 Conclusions Copyright 2015, PCI-SIG, All Rights Reserved 3

for Rx Testing Effective Instruments for PLL Testing Getting Ready

4 PCIe Base vs CEM Tx Testing What test point each type of testing addresses? How do we get to see the signal at the point of interest? Measure for Base Capture Measure for CEM Copyright 2015, PCI-SIG, All Rights Reserved 4

the added effects of the channel S-Parameters are acquired for the replica channel Signal at TX Pins Measured Signal

5 Base Spec Testing Base Specification measurements are defined at the pins of the transmitter Signal access at the pins is often not possible De-embedding is required to see what the signal looks like at the pins of the TX, without the added effects of the channel S-Parameters are acquired for the replica channel Signal at TX Pins Measured Signal at TP1 De-embed using S-Parameters Signal with Channel Effects Removed Copyright 2015, PCI-SIG, All Rights Reserved 5

CEM Testing CEM Specification measurements are defined at the slicer of a receiver Signal access at this test point not possible Embedding of the compliance channel and package, as well as

6 CEM Testing CEM Specification measurements are defined at the slicer of a receiver Signal access at this test point not possible Embedding of the compliance channel and package, as well as application of the behavioral equalizer is required SigTest or custom software like SDLA and DPOJET will perform the embedding and calculate measurements Signal Acquired from Compliance Board Embed Compliance Channel and Package Closed Eye due to the Channel Apply CTLE + DFE Open Eye for Measurements Copyright 2015, PCI-SIG, All Rights Reserved 6

software like SDLA and DPOJET will perform the embedding and calculate measurements Signal Acquired from Compliance Board Embed

7 Agenda PCIe Base vs CEM testing Testing Challenges in Tx and Rx Automation to simplify Tx testing Automatic Calibration Essential for Rx Testing Effective instruments for PLL testing Getting ready for PCIe 4.0 Conclusions Copyright 2015, PCI-SIG, All Rights Reserved 7

8 Testing Challenges in Tx Meet requirements for effective testing Compliance mode support, proper patterns Toggling support (100MHz clock on Rx Ln0) Correct Tx equalization settings Preset and Lane ID encoding in Tx pattern How to handle all lanes, speeds and presets The answer is test automation, RF switch Measurement algorithms require channel embed and behavioral equalizer with optimization Implemented in SigTest, or scope specific software Copyright 2015, PCI-SIG, All Rights Reserved 8

lanes, speeds and presets The answer is test automation, RF switch Measurement algorithms require channel embed and

9 Automation of Tests Automation steps Acquisition of waveforms Processing of waveforms Reporting Toggling of Presets (Tx equalization) Use AFG or another signal source to generate toggle 4.0 will introduce addition ones Connecting to all lanes Use RF Switch PCI Express testing lends to efficient automation thanks to the methodology based on individual files (test items) Copyright 2015, PCI-SIG, All Rights Reserved 9

0 will introduce addition ones Connecting to all lanes Use RF Switch PCI Express testing lends to

10 Automated Capture Use applications built into the scope Optimize signal capture quality and speed Organize test data by using naming convention Supports various test modes Copyright 2015, PCI-SIG, All Rights Reserved 10

Organize test data by using naming convention Supports

11 Automated Processing Typically the processing is built into the standard based application Processing occurs in series with capture Processing is serial due to test software limitation (SigTest) Scope compute platform does not necessarily have the latest processor and is otherwise occupied with scope control, acquisition and visualization Parallel processing provides improvement Well designed system provides scalability Sigtest engines that can be added any time Copyright 2015, PCI-SIG, All Rights Reserved 11

latest processor and is otherwise occupied with scope control, acquisition and visualization Parallel processing provides

12 Practical Comments on Sigtest Make sure you are using the latest approved version for given technology Version requires template patch for Gen2 New installer is being tested Command line interface is available Flexible for scripting, for example Sigtest.exe /e /d folder /s *.wfm /t "PCIE_3_0_CARD\PCIE_3_8GB_CEM.dat" Binary location different on 32 vs 64 bit system Two copies can be run but they are not guaranteed to peacefully coexist Scripting using batch file, powershell or python is available Copyright 2015, PCI-SIG, All Rights Reserved 12

$Sigtest.exe /e /d folder /s *.wfm /t "PCIE_3_0_CARD\PCIE_3_8GB_CEM.$

13 Agenda PCIe Base vs CEM Testing Testing Challenges in Tx and Rx Automation to Simplify Tx Testing Automatic Calibration Essential for Rx Testing Effective Instruments for PLL Testing Getting Ready for PCIe 4.0 Conclusions Copyright 2015, PCI-SIG, All Rights Reserved 13

14 Essentials of Rx Testing PCIe 3.0 introduced formal Rx testing Based on stress testing of the DUT in loopback Looped back signal must contain the same data as the stressed signal DUT must support loopback initialization and training Impairments in stress must be controlled and repeatable DUT must receive stressed signals without errors for certain time or confidence level (below specified BER10-12 ) Copyright 2015, PCI-SIG, All Rights Reserved 14

the same data as the stressed signal DUT must support loopback initialization and training Impairments in stress

closure ( Interference ). 8G PRBS Gen Combiner Cal.

15 Stress Composition Tx Eq PCI Express 3.0 uses a long circuit board channel that closes the eye, and two forms of vertical eye closure ( Interference ). 8G PRBS Gen Combiner Cal. Channel Replica Channel Test Equipment RJ Source SJ Source Postprocessing Diff Interference CM Interference Eye Height Adjust Copyright 2015, PCI-SIG, All Rights Reserved 15

16 Automatic Calibration Due to complex test setup and variations in DUTs and test equipment just dialing up the settings on the signal source is not sufficient Stress must be measured and adjusted Automatic calibration is used to achieve the right amount of stress Margin testing complements the compliance testing Help understand your device s margins How much additional stress does it tolerate? Copyright 2015, PCI-SIG, All Rights Reserved 16

used to achieve the right amount of stress Margin testing complements the compliance testing Help understand

19 Rx Testing Challenges for 16G Rev 4.0 Spec attempts to streamline testing by reducing differences between Base and CEM Significant differences at 8GT/s recognized BERT with required stress generation RJ, SJ are likely the most challenging specs De-emphasis Accurate coverage of the coefficient space Variable ISI channels Use ISI emulators or ISI boards planned in PCI-SIG Custom loopback initialization for test silicon Copyright 2015, PCI-SIG, All Rights Reserved 19

recognized BERT with required stress generation RJ, SJ are likely the most challenging specs De-emphasis Accurate

20 Rx Testing Summary High complexity of equipment and procedures Repeat of extensive correlation studies at 16GT/s in PCI-SIG that helped streamline solutions from multiple vendors Similar stress signals Guided calibration and test execution (MOIs) Good correlation on latest workshops Copyright 2015, PCI-SIG, All Rights Reserved 20

multiple vendors Similar stress signals Guided calibration and test execution

21 Agenda PCIe Base vs CEM Testing Testing Challenges in Tx and Rx Automation to Simplify Tx Testing Automatic Calibration Essential for Rx Testing Effective Instruments for PLL Testing Getting Ready for PCIe 4.0 Conclusions Copyright 2015, PCI-SIG, All Rights Reserved 21

22 Effective Instrument for PLL Testing For PLL testing use a setup that requires single instrument The method is based on modulating the 100MHz reference clock and measuring the bandwidth with clock recovery unit The limits for bandwidth are 2-4MHz with 2dB peaking If BW 4-5MHz, peaking must remain under 1dB Copyright 2015, PCI-SIG, All Rights Reserved 22

25 Agenda PCIe Base vs CEM Testing Testing Challenges in Tx and Rx Automation to Simplify Tx Testing Automatic Calibration Essential for Rx Testing Effective Instruments for PLL Testing Getting Ready for PCIe 4.0 Conclusions Copyright 2015, PCI-SIG, All Rights Reserved 25

26 Review of PCIe 4.0 Characteristics Some important characteristics Use of the same form-factor, backward compatibility Due to long channels wider use of extension devices (repeaters) More states, more complexity in speed and equalization training New SRIS independent Ref Clk modes SRNS Separate RefClk Independent with No SSC Architecture SRIS Separate RefClk Independent with SSC Architecture Increased number of presets in Tx, 11 presets at 16GT/s, total of 25 presets as of 0.5 spec revision More complex behavioral receiver (CTLE, DFE with higher number of taps), more time needed for optimization in measurement algorithms Copyright 2015, PCI-SIG, All Rights Reserved 26

27 Getting Ready for PCIe 4.0 Utilize the investment in PCIe 3.0 as much as possible Tx signal quality tests At least 25GHz Oscilloscope, 100GSa/s sampling 16GT/s capable RF switch for automation Signal source for automation (toggle) Rx Testing BERT and related equipment capable of 16GT/s testing New test boards from PCI-SIG Copyright 2015, PCI-SIG, All Rights Reserved 27

28 Conclusions PCIe 3.0 was a significant step forward in technology and testing methodology Dealing effectively with closed-eye standard and signals Virtual test points, multiple presets and lanes Introducing new types of measurements (uncorrelated jitter) Formalizing Rx stress test process PCIe 4.0 is an evolution in test methodology Methods used in PCIe 3.0 will be extended to higher signaling rate assuming similar losses in the channel Extension devices (redrivers/retimers) will have impact Deal with higher number of test items (e.g. waveforms in Tx) Use efficient tools and you will be ready for PCIe 4.0 testing Copyright 2015, PCI-SIG, All Rights Reserved 28

Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance

Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance Page 1 Agenda Introduction PCIe 2.0 changes from 1.0a/1.1 Spec 5GT/s Challenges Error Correction Techniques Test tool