Data Transmission Control Line Intermodule Exchange Interface, Advantages and Disadvantages

Transcription

1 IMPLEMEPITATI ON AND ANALYS IS OF THE TRIrtOSBUS SELF-CLOCKIFJG INTERFACE V. I. Varshavskii, V. B. Marakhovskii, L. Ya. Rozenblyum, and A. V. Yakovlev Avtomatika i V ichislitel 'naya Tekhnika, Vol. 19, No. 4, pp , 1985 UDC It is established that the TRIMOSBUS intermodule exchange interface with a three-wire system of data transmission control lines in VSLI circuits does not belong to the class of speed-independent interfaces, i. e., it is not invariant to the element and line delays. INTRODUCTION Paper [I] dealt with principles of self-clocking matching of modules in VLSI systems and proposed formal models of self-clocking digital stmctures (SDS), in particular intermodule exchange interface protocols. It is of definite interest to apply these models to the analysis and implementation of computer system interfaces, both those already existing and those already under development. In 1979, at a conference sponsored by the California Institute of Technology (Caltech) on VLST systems, three American niversities and the Digital Equipment Corporation (DEC) presented an organizational project 4 or the TRIMOSBUS interface [2], this interface being invariant to the time parameters of the modules; it was noted that this design was intended for use in many forthcoming developments of VLSIbased computer systems. The interface is intended for matching the functional modules of a system upon transmission of information between them in a "one source/several receivers" mode (one-to-all). This mode of operation is extremely useful in applications involving dynamic checking of correctness of module operation in a system, as well as the possibility of a system reconfiguration. Paper [2], in dealing with TRIMOSBUS, provided an informal idea of the exchange protocol at the lowest level of matching, and also provided functional diagrams of the data source and receiver interface devices. It is of interest to analyze the protocol and the circuits with a view to the self-clocking properties that have been claimed for them. SELF-CLOCKING IN THE CASE OF Ol4E-TC-ONE AND ONE-TO-ALL INTERACTION Assume that a pair of system modules is linked by a bundle of parallel information lines and a pair of control lines A and B. If one of the modules functions as the data %$z= source, the other as the data receiver, then self-clocking of the transmission requires, g in the first place, that the modules interact on the basis of the handshaking principle,.b: i.e., using "accompanyingt' (or "tracking") and acknowledgement signals A and By as is the case in many contemporary interfaces. It is also necessary to ensure unconditional satis-,+1 faction of the precendence relation (<) between event D.P-R (transmission from the spacers to the - :< information set R on a parallel bundle of lines) and event A+ (establishment of tracking 7. 3' signal). For both the data source and receiver, we should have Ds-R<A+. The protocol for this interaction is specified by a special graph (see Fig. 1). K In most available interfaces, the self'-clocking principle is violated through the introduction of specific delays, which ensure with some probability at least some reliable degree of compensation of "signal mismatch" in the parallel bundle in relation to the tracking signal. Thus, in a common bus the overall compensating delay is standardized and equal to 150 nsec (tlmismatch plus decoding of the address"). In the environment of VLSI structures, this method is not satisfactory. An alternative solution involves the use of a self- Q 1985 by Allerton Press, Inc. ~ig. 1. One-on-one interaction protocol. 8 0

2 slocxing or self-tinlng cod [3j..Anoccer version o' deeling xi:? Lnenis?etcn ~-3c12n involves the "creation" of I-Zeractlon conditions oecween so~rce 2nd r~coi-:sf sn :ze ol2ctrical and physical levels such that nismatcn is not 2 hazerd. The idea is thac, if on tne basis of analyzing the physical properties of the lines and the rncei-~er/trznsnitter circuits, it is possible to establish that the line delays in the bundle are negligible as compared to the switching time of the drivers, then each line can be regarded as an "equipotential zone" and the set of events in all its points is only one event [2,4]. This is the idea that was employed by the authors of TRIMOSBUS project, who avoided dealing with the mismatch problem per se and instead dealt with the problem of organizing self-clocking matching of one data source and many receivers (one-to-all). Let us consider some examples of the use of the one-to-all mode. First example. In any system based on the bus principle, data exchange between the master and slave (or actuating) devices involves a phase of selection of a single slave device by the master device. It is natural to assume that, when the self-clocking principle is employed, the device-selection signals in the protocol should be received by all possible slave devices, and that only after decoding of the address in each module can there be two-way exchange (reading or writing of data). Since there is no way for the master device to reliably establish the instant of determination of the phase of selection of the requisite slave device other than to obtain a -collective "acknowledgement" from a11 modules that the decoding process has been completed, it is obvious that the one-to-all principle cannot be avoided in this phase. Second example. The system has a central computer and a decentralized digital control system for entities that are distributed in space. In this system, virtually any exchange between the "center" and the subscribers that is initiated by the "center 1 ' takes place in a "broadcasting 1 ' mode, i.e., transmission of a message to all modules in order for each module to utilize its own part of the information by an association mechanism. On-board installations, as an example, may be systems of this type [2]. It is clear that the use of the one-to-all mode in this case is much more efficient that a dialog between the "center" and each subscriber. The TRIMOSBUS interface project offers an extremely interesting way of solving the problem in question. However, a detailed analysis of it reveals a number of weak points-; in particular, the principle of independence of element delays is violated in the proposed source and receiver interfacing structures. Features of TRIMOSBUS interface. The name itself of the project was not chosen at random. In the first place, it reflects the use of a three-wire system of transmission control lines (an analog is provided by the three-wire system of the IEC standard [51). The signal-chang& protocol on these lines operates without time constraints on the response of the modules. Second, the design presumes the use of MOS gates (drivers) at points at which signals are received and fed to parallel information lines, which are characterized by a high-impedance state, thus making it possible to employ the information lines as an intermediate buffer, and a fairly large switching time of the MOS switches relative to the delays in the lines, whose length is limited to 20 cm (an entirely acceptable figure for the intermodule interface for the VLSI system), so that the wire can be regarded as equipotential. A major advantage of TRIMOSBUS over the IEC interface as regards protocol organization using three control lines is a reduction in the number of changes in control Signals. A complete transmission of a batch of data from source to receivers consists of three operations: 1) delivery of the data to the information lines; 2) establishment of a data-tracking signal on one of the control lines; 3) generation of a collective acknowledgement-ofreceipt signal by all subscribers. We should note that the source implements the first operation as follows. The information lines are excited upon switching of the drivers. The source fixes the voltage levels established on the information lines. The excitation is removed when the required value is attained, prior to delivery of the signal. Thus, the source is immediately disconnected from the bus once the data have been delivered to it, and does not wait for the slowest receiver to receive them. In view of the buffer properties mentioned above, the bus itself stores the data in-each exchange event. Now let us consider the organization and analysis of the control-line protocol in more detail.

3 Fig. 2. General structure of one-to-all interaction: 1) transmitter module; 2) receiver module; 3) source; 4) consumer; 5) transmission control unit; 6) reception control unit; 7) data bus. Fig. 3. Model of lower level of module interfacing; a) signal graph; b ) logic diagram. Fig. 4. Data transmission control protocol in TRIMOSBUS. i Transmission control protocol in TRIMOSBUS. Figure 2 shows the overall structure of interaction of modul,es engaged in exchange in the one-to-all mode; it can be seen that each exchange participant is decomposed into a higher-level entity and a lower-level en tit;^. Thus, in he transmitting module the source provides a higher-level entity, while the transmission control unit provides a lower-level entity. In the receiver modules, these are the consumer and reception control unit respectively. For the upper level, exchange 'llooks" ra like an ordinary two-wire handshake at the junctions (ai, bi). Therefore, if we disregard the internal structure of the lower layer (dashed rectangle), its external behavior at the junction with the upper level can be specified by the signal graph shown in Fig. 3a, from which it is evident that the lower level functions as a decoupling timing or clocking device. This behavior is realized logically by the circuit in Fig. 3b, where the indicator is a standard aperiodic circuit, namely a G-flip-flop, with an intrinsic function of the form )'=b,.b,.....b,vy (b,vb2v...v 6,) [6]. It is quite obvious that the model in Fig. 3 cannot be used in practice to implement matching of modules in a one-to-all mode, although it makes elements and leads delay-independent, since it is a model with individual acknowledgement lines from each module. Therefore we have the problem of organizing the lower level of TRIMOSBUS using the bus principle of module connection, for which we require transmission and reception control units which in effect convert a two-wire handshake to a protocol with three control lines. To obtain the effect of collective acknowledgement of correct reception from all consumers, the TRIMOSBUS protocol uses a property of wired AND logic: establishment of a low voltage on the control line by one of the participants (i.e., connection to the line), resets the voltage of the entire line; it is possible to return to a high voltage level only provided that the low-level values are removed by all of the participants in the interaction (i.e., they disconnect from the line). Figure 4 shows the transmission control protocol based on three lines, in the form of a signal graph; it is evident that each exchange begins in a state in which a low voltage M- is established on onecof the wires (i.e., all modules are connected to it), while a high voltage is established on the two others (i.e., all modules are disconnected from them).

4 Yig. 5. Model of interaction with pair of control lines: a) structure (zero represents the transmitting module; 1,..., n the receiving modules); b) signal graph. Let us clarify the semantics of the protocol by the following interpretation of the sequence of states of its lines. A B C initial state: all modules connected to line A; all disconnected from B and C transmitting module connected to B, informing receivers that there is data on information bus, after which the receivers also connect to B transmitter disconnects from A, while receivers, upon completion of data receptibn, also disconnect from A; appearance of high voltage on A indicates collective acknowledgement of reception and completion of the exchange event by all participants. System now ready for next event. Similar operations occur in the next event, except that the tracking signal is now transmitted over line C (and then over A, B,...), while B is employed for the collective acknowledgement signal instead of A (and then C, A,...). It follows from what has been said that the protocol is cyclical, and that three phases can be distinguished in each cycle. Before proceeding to describe an im~l~ement the logical transmission- and receptioncontrol units, let us deal with one more issue. The protocol described above employed three control lines for providing a one-to-all mode, but only two lines -"operate" in each exchange event. A question that arises is whether three lines do indeed comprise the minimum. We will demonstrate briefly that two wires are not sufficient for the protocol to ensure a one-to-all mode independently of the delays of the exchange participants. Consider the model of interaction with two control lines shown in Fig. 5a. Figure 5b shows a fragment of the signal graph specifying the process of signal change for the variables A, B, A., A1, An, BOJ Ab, Bn. Let us make some comments regarding it. The transmitter begins operation with the transition A., after which a zero voltage is established on line A. The state of this line is fixed by all the receivers, i.e., - - i i the transitions A1 and An. After data reception, they execute transitions B1 and Bn, + in parallel with which the transition Bo - occurs in thetransmitter.* By the time all of these events have taken place, a high voltage is established on line 8. Since, however, there is only a pair of wires, the next event begins on the same wire B (transitions B o - and B-) where the collective acknowledgement signal was just generated. As a result, there are two adjacent signal changes on the same line for the receivers, and this can lead to the following: the slowest receiver, which changed the state of wire B from zero to 1, may not be able to I1index1' (i.e., store in its internal circuitry) the fact of completion of transition B+ prior to the reverse.change B- caused by the transmitter. We now have almost all the necessary information to describe the behavior of each of che participants, i.e., transmission and reception control units: in particular, the in-ceraction protocols with the upper level and the three-wire transmission control protocol. However, we still need to include some details associated with implementation of the operstions of "connection to line" and "disconnection from line. " Accordingly, we now represent the interaction level under consideration in the form of the structure shown in Fig. 6a,

5 Fig. 6. Model of lower level of interfacing: a) structure (1 represents the logical sublevel, 2 the transmission control unit, 3 the reception control unit, and 4 the electrical sublevel); b) model of cornrnunlcations linefor logical sublevel. where the level is structured into two sublevels (logical and electrical). The first sublevel contains the coordination logic for the lnteraction protocol with the upper level and the three-wire control protocol, while the second comprises the lines themselves and the drivers for performing the operations in question. If the drivers are implemented using inverting amplifiers, the model of each line for the logical sublevel is a logical NOR element (Fig. 6b), whose inputs are fed the output signals of the cofitrol units, and whose output provides the signal from the line and is fed to the corresponding inputs of the control units. Implementation of logical transmission and reception control units. The description of the TRIMOSBUS project [2] gives logical circuits that implement the transmission and reception control units; however, verification of these structures revealed that they depend on the element delays. Therefore it was necessary to resort to a formal synthesis procedure for the units, by changing over from the protocol description, first to local models of the exchange participants and then to aperiodic circuits that implement these models in AND-OR-NOT logic [7]. The signal graphs that model the logical transmission and reception control units are shown in Fig. 7a and 7b respectively. These graphs specify the ordering of the changes in the variables that model respectively the communications lines with the upper level a and b, the TRIMOSBUS lines A, B, and C, and the output control signals for the drivers of the electrical interface sublevel TA,TB and TC. After analyzing these models, in order to proceed to implementation it proved necessary to introduce additional variables providing internal memory for the control units and eliminating indetermlnacy in certain situations (the presence of repeating situations can readily be established if transition diagrams are set up on the basis of the signal graphs). After the additional variables were introduced, the signal graphs shown in Fig. 8 were obtained; to simplify the description of the protocol, common vertices correspond to variables that switch in different phases and that differ only in terms of the line index. Forexample, the notation B(C, A) means that in the first exchange event variable B switches from 1 to 0; variable C in the second; variable A in the third; again B in the fourth, and so forth. To obtain the system of intrinsic Boolean functions of the implementing aperiodic circuit, we can convert to transition diagrams, and to truth tables, from which (through minimization) we can write out logical expressions for the variables in AND-OR-NOT logic. Manual use of this procedure is fairly laborious, however, and therefore in manual synthesis it is convenient to resort to decomposition of local descriptions. It turns out that the variables DA(B.CJ, TA@.CJ in both control units can be implemented by a mod 3 scaling circuit (tristable counter flip-flop), specified by the following equations: Figure 9 shows complete structural diagrams of the transmission and recpetion control units; in addition to the counter flip-flop, there are circuits described by the following equations : circuit for analyzing the channel state in the tran'smission control unit : IZI,=ABVBCVAC, '

6 Fig. 7. Signal graphs that model logical transmission-control (a) and recepttion-control (b) units. ~ig. 8 Fig. 9 Fig. 8. Models of logic units for transmission control (a) and reception control (b) after introduction of additional variables. J Fig. 9. ~~ructural diagrams of transmission and reception control units: 1) source; 2) consumer; 3) source-matching arrangement; 4, 6) tri-stable counter flip-flops; 5, 8) channel state analysis circuits; 7) electrical interface sublevel. Fig. 10. Signal graph of model of communications channel (electrical sublevel). - control - VAT,c, t,sbi ; analogous circuit in the reception unit : ~,=BT,.LVCT,YV bo=ro; matching circuit: tqo=aopovmo; po=m; Po=aoPo; to=~o(povr~): So=Polvl. Source

7 The initial state of the circuits (~~alues of the correspondin3 veriables) is also shown in 3ig. 9. It is not hard to establish that the circuits operate exactly in accordance with the signal graphs in Fig. 8, and are delay-independent. Modeling of communications channel and problem of fault-tolerance of TRIMOSBUS. To set up the transmission and reception control units on the logical level it was necessary to resort to segregating the lower interface level (see Fig. 6), containing lines A, 5, and C and the drivers (switch transistors) in each of the modules that "hang" on the TRIYOSSUS bus. In view of the fact that the circuits of the interface units are "speed-independentjlt they ensure, first, invariant operation to parametric element failures; second, comple~e self-testability relative to faults at element outputs of the "stuck-at zero" and "stuc~at one 1 ' type [81. Thus, on the level of logical description of TRIMOSBUS, in which the lines function as NOR elements, the interface meets the criteria of delay independence, self-clocking. However, on the level of transistors, i.e., the electrical interfacing sublevel, the description of the communications channel loses this independence. Indeed, the collectors of the driver transistors are connected to the corresponding lines that realize "wired AND" relative to the high voltage (logical 1). Let us assume that the entire system of lines is in state 0 0 1, and that the transistor on line B for one of the receivers (e.g., the first) has a very large delay (e.g., is an open circuit). The fact that this switch did not. open in the phase of connection of this receiver to B in no way affects the behavior of the system, and the transition from state to state is independent of the process of information reception in this receiver. Generally speaking, the fact that this switch is an open circuit can be detected, but only when the module becomes a transmitter in phase 1 1 0, and hence cannot lfcompel" the line to assume a zero voltage, i.e., the process stops. Up to this point the reliability of operation of the circuit will be in doubt. The fact that the drivers of the receivers cannot be indexed can be established by analyzing the signal graph describing the channel model in question for conflicts and dangerous situations [I]. This graph is shown in Fig. 10, where the. variables TA, TB andtc model the inputs of the transistor switches in each of the modules, while the variables Kd', KB and K C model the state of the corresponding collector circuits ofthe transistors ( 0 and 1 represent closed and open respectively). Since vertices KiB+, XnBf do not precede anything, it is possible for a point to appear simultaneously at the input of and at the input of Icln- (under the assumption that the transistor on line B of the first module is 'fslow", thus indicating conflict behavior of the structure. In addition, in the next cycle of use of line B for data tracking a second point at the input of l<io+ may appear. CONCLUSION As a result of detailed analysis of the TRIMOSBUS interface, using formal models of self-clocking digital structures, we have been able to reject the hypothesis that the interface operates independently of delays; in addition, we have established that, upon going to the transistor level of analysis of the properties of self-clocking (as is indeed necessary for VLSI structures), similar problems arise in any gate containing wired logic. Still, for the three-wire TRIMOSBUS protocol it is possible to construct a self-clocking driver circuit. However, it is not our aim to describe this circuit, the more so in that its synthesis is more of an engineering art than a formal procedure. Our example with the TRIMOSBUS interface is only an illustration of the thesis that the use of the self-clocking principle is perhaps the only way of resolving all the problems encountered in the creation of VLSI computer systems. REFERENCES 1. V. I. Varshavskii, V. B. Marakhovskii, L. Ya. Rozenblyum, and A. V. Yakovlev, "Principle of self-clocking and interface models in VLSI systems," AVT [Automatic Control and Computer Sciences], no. 3, pp , I. Sutherland, C. Molnar, R. Sproul, et al., "The TRIMOSBUSJll in: Proc. Caltech Conf. VLSI, Pasadena, CA, pp , V. I. Varshavskii, V. B. Marakhovskii, V. A. Peschanskii, et al., "Possibiiitg of implementation of an asynchronous interface using a self-clocking code with an identifier," AVT [Automatic Control and Computer Sciences], no. 5, pp , C. Mead and L. Conway, Introduction to VSLI Systems, Addison-Wesley, Reading, 13P., N. I. Gorelikov, A. N. Domaratskii, S. N. Domaratskii, et al., Interface for Pro- ' grammable Devices in Systems for Automating Experiments [in Russian!,??~uKa, Moscow,

8 5.?.periodic :l.utoca;a [ :;,?.l;ssia;.], ::zzi~,.,!cscc:,,, A. V. lakovlev, "3eslgn and L:.c:eze-zetion cc esync3ro?.c1~s iers-e:<:henge zn0~ in an interface between n?.odules," Author's Abstract 3: :an5:5z','s DLsserta:i~n, ienlngrad, V. I. Varshavskii. L. Ya. Rozenblgum, -. and A. R. Taubin, "Completely self-testing combination circuits and the property of indexability," Avtomatika i Telemekhanika, no. 5, pp, , May 1984 Revised 21 September