A Multichannel Storage Capacitor System for Processing of Fast Simultaneous Signals. Atsushi Ogata. IPPJ-T-16 Oct. 1973

Transcription

1 A Multichannel Storage Capacitor System for Processing of Fast Simultaneous Signals Atsushi Ogata IPPJ-T-16 Oct. 1973

2 A Multichannel Storage Capacitor System for Processing of Fast Simultaneous Signals Atsushi Ogata IPPJ-T-16 Oct Further conununication about this report is to be sent to the Research Information Center, Institute of Plasma Physics, Nagoya University, Nagoya, Japan.

3 Abstract A storage capacitor system is described which collects simultaneous signals in a very short sampling time, store them in capacitors and gives them as an output slowly in a serial form

4 In the course of experimental research we often meet the problem of collecting, displaying and processing the several simultaneous signals. An obvious solution is to equip as many oscilloscopes with Polaroid cameras, but it is costly and suffers from other drawbacks. We have reported previously a delay cable system which displays several simultaneous signals in the nanosecond region on a single oscilloscope trace. This method uses interchannel delay cables in order to separate the simultaneous signals. However, it is not practical to be used in combination with relatively slow devices, such as an analogto-digital converter and a storage oscilloscope, because it requires long cables to give long interchannel delays, which make attenuation in the cables very serious. We have developed a storage capacitor system to meet the requirements which cannot be met by the delay cable method. It collects simultaneous signals in a very short sampling time, and gives them as an output in a serial form slowly. It is based on principles utilized in the standard sample and hold circuitary and the analog multiplexer. original purpose of the system is to display the transient The simultaneous signals, such as a Thompson scattering spectrum in a plasma or an energy spectrum of an injection beam of an 2 electron ring accelerator, on a single oscilloscope trace. However the system is also useful to multiplex continuous signals and the output can be combined to a fast analog-todigital converter such as Datel's UH8B (whose conversion time is 100 nsec/8 bit)

5 A block diagram and time sequences in two time scales are shown in Figs.l and 2, respectively. The system has eight input channels and each channel consists of a sampling switch (SW01 to SW08 in Fig.l), a storage capacitor, a buffer amplifier with high input impedance and a reading switch (SW1 to SW8). The sampling switches are closed simultaneously charging the storage capacitors, while the reading switches are closed successively by the output pulses of a shift register, reading the voltage stored in the capacitors, as is shown in Fig.2(b). Outputs of the reading svitches are summed in an operational amplifier and the result is fed to the oscilloscope or to the analog-to-digital converter. Actual circuit diagrams are shown in Figs.3 and 4. Figure 3 shows the control pulse generator to close the switches. A monostable multivibrator MM1 generates a pulse 20 nsec in width which is shaped in gates Gl to G8 and is distributed to close the sampling switches. Gates G9 and G10 constitute a clock pulse generator which is controlled by the output of MM2. The clock frequency depends on C and R values. A shift register SRI accepts a serial input from MM3, clock pulses from G10 and a clear pulse from Gil, and generates pulses to close the reading switches successively. Figure 4 shows the sampling switch, the buffer amplifier, the reading switch and the summing amplifier. Both the sampling and the reading switches are made of HP hot carrier diode matched bridges. The SN72733 video amplifiers _ O _

6 are used to shape the control pulset: and supply them in positive and negative polarities to the switches. The LH0033C unity gain buffers are used between the two kinds of switches, whose slew rate is 1500 V/isec and input impedance is 10 ohm. The ratio of the voltage V charged in the storage c capacitor C during the closing of the sampling switch &t to the input signal voltage V. is/ if V. is constant during at, V V in = X ~ ex P [-<*t/(r on + r g )C]. where r on and r s are "on" resistance of the diode and the source impedance of the signal, respectively. According to maker's data sheet r =10 ohm, and in our case at = 20 nsec, r = 50 ohm and C = 20 pf. Hence we get V /V. = If V. varies during t, V follows V. with time xn c in constant of (r + r )C nsec. I*-, should be noted on s that V is nearly equal to V. at the moment of opening of the sampling switch, which is caused 70 nsec after the rise time of the trigger pulse, as is shown in Fig.2(a). More accurately, V AS avaragedv. value during the switching C in time, which depends on the rise time of the control pulses (T01 to T08 in Pig.l) and is about 5 nsec. The ratio of the voltage V, remaining in the storage c. acitor after the holding time t. to the initially cv.ai jfid voltage V is o - 4 -

7 V V c = exp 1-% where 1/R = l/r Qff + l/r L + l/r c + l/r i, where r. r T, r_ and r. are "off" resistance of the off L C i diode, input impedance of the buffer amplifier, leakage resistance through storage capacitor and leakage resistance through the circuit insulation/ respectively. We estimate r _, = 10 8 ohm, r T = ohm, r_ = lo 10 ohm and r. = 10 9 on j-i c i ohm, and get V./V = for t. = 3 psec, which is the voltage ratio remaining in the storage capacitor when the last reading switch SW8 is closed. Zero-temperature-coefficient cermic disc capacitors are used as the storage capacitors, becauce they are small in size. Their variance in capacitance values is + 10 %. id. does not influence the characteristics of the system, as is clear in above equations. A.i LH0024C operational amplifier is used to sum the output of the reading switches. The exact gain in each channel depends mainly on the gain of the buffer amplifier, and the values of the input resistors (Rl to R8 in Fig.l) are adjusted to give weights which effect a uniform gain in all eight input channels. The final gain of the system is Polarity of the input signal is inverted. Output impedance is 50 ohm. The system gives good linearity for the input range of V. As is shown in Fig.2(a), the trigger pulse in the TTL level must be. fed preceding the sampling switch closing by 50 nsec. When the system is used to multiplex the - 5 -

8 continuous signals, the maximum sampling frequency is 250 khz. Figure 5 shows an oscilloscope photograph of the test performance. Eight inputs receive pulses different in amplitude (maximum in channel 1 and minimum in channel 8) and equal in width and timing. One of the input signal is shown in the lower trace. Output waveform is shown in the upper trace. Though transient undershoots are generated at the moment of switching, they will not be very harmful. This result confirms the applicability of the system to the experimental research. The author is grateful to Prof. K. Adati for his encouragement and suggestion

9 REFERENCES 1. A. Ogata and G. Horikoshi, Nucl. Instr. and Meth. 108 (1973) A. Miyahara et al., IPPJ-T-11 (1972)

10 FIGURE CAPTIONS Fig.l. Block diagram. Fig.2. Time sequences. Closing of the switches is shown by high level. Fig.3. Circuit diagram of control pulse generator. Fig.4. Circuit diagram of sampling switch, buffer amplifier, reading switch and summing amplifier. Fig.5. Oscilloscope photograph of test performance. Upper trace-output signal,.2v/div.. Lower trace-width and timing of input signal. Horizontal scale-.5 usec/div.. _ 8 _

11 Ch. I INPUT >-j- swoji 1 I Jc I 1 isw i! ONE SHOT.^TRIGGER ^ INPUT Ch. 2 INPUT > VD Ch.3 INPUT i SW0J2! Jc Jc ; [SW2 o4- SW3 1. SHIFT REGISTER CLOCK PULSE GENERATOR Ch.8 INPUT L SAMPLING SWITCHES SW8 1 I I J BUFFER READING AMPLIFIERS SWI'.CHES SUMMING AMPLIFIER ^ OUTPUT Fig. 1

12 TRIGGER CLOSING OF SAMPLING SWITCHES \* so CLOSING OF SW I 170 (a) Time (nsec) TRIGGER CLOSING OF SAMPLING SV1/ITCHES INPUTS (DASHED) AND < CAPAUTOR VOLTAGES CLOSING OF READING 1 SWITCHES OUTPUT ' Ch.l Ch.2 Ch.3 Ch.8 f SW 1 SW2 SW3 - SW8 i -4 i 1 1 JL 1 r 1 T i 1 I I i! \ 1 1Ch N 3.1 I (b) Fig J 8 ^ 3 Time ( u,sec)

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14 TOI Ch.l SN72733 INPUT f _7V " -7V '" -7V 2XHP230I HP LH0033C HP I 2XHP230I IK y&- vw- IK "10p +7V.003//.! 9 20 P JC 1-7V SN OUTPUT other 7 channels j Fig. 4

15 Pig