FPGA ACM/SIGDA Fourth International Symposium on FPGAs February 11-13, 1996, Monterey, CA

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1 FPGA ACM/SIGDA Fourth Iteratioal Symposium o FPGAs February 11-13, 1996, Moterey, CA Etropy, Coutig, ad Programmable Itercoect AdréDeHo adre@mit.edu MIT Artificial Itelligece Laboratory NE43-791, 545 Techology Sq., Cambridge, MA Phoe: (617) FAX: (617) Abstract Covetioal recofigurable compoets have substatially more itercoect cofiguratio bits tha they strictly eed. Usig coutig argumets we ca establish loose bouds o the umber of programmable bits actually required to describe a itercoect. We apply these bouds i crude form to some existig devices, demostratig the large redudacy i their programmable bit streams. I this process we review ad demostrate basic coutig techiques for idetifyig the iformatio required to specify a itercoect. We examie several commo itercoect buildig blocs ad loo at how efficietly they use the iformatio preset i their programmig bits. We also discuss the impact of this redudacy o importat device aspects such as area, routig, ad recofiguratio time. 1 Itroductio Despite the fact that programmable devices (e.g. FPGAs) are mareted by the umber of gates they provide, a device s itercoect characteristics are the most importat factors determiig the size of the programmable device ad its usability. Whe desigig the itercoect for a programmable device we must simultaeously address several importat, ad ofte coflictig, requiremets: 1. Provide adequate flexibility, allowig the realizatio of a sufficietly large space of iterestig itercoectios 2. Efficietly specify itercoect behavior, miimizig the space ad time required to cofigure the itercoect 3. Balace device bisectio badwidth with available or allowable spatial costraits 4. Miimize itercoectio delays I this paper we focus o the size ad redudacy of our programmable itercoect descriptio (requiremet umber 2). I the Copyright (c) 1996 by the Associatio for Computig Machiery, Ic. Permissio to mae digital or hard copies of part or all of this wor for persoal or classroom use is grated without fee provided that copies are ot made or distributed for profit or commercial advatage ad that ew copies bear this otice ad the full citatio o the first page. Copyrights for compoets of this wor owed by others tha ACM must be hoored. Abstractig with credit is permitted. To copy otherwise, to republish, to post o servers or to redistribute to lists, requires prior specific permissio ad/or a fee. Request Permissios from Publicatios Dept, ACM Ic., Fax +1 (212) , or <permissios@acm.org>. process of discussig itercoect descriptios, the paper broadly addresses itercoect flexibility. Fudametally, itercoect descriptio memory eed ot grow as quicly as wire ad switch requiremets. This leaves us with desig poits which are geerally wire ad switch limited. We may, cosequetly, ecode our itercoect descriptio sparsely whe memory area is early free ad wirig chaels are determiig die size. Sice itercoect memory grows slowly compared to switch ad wire requiremets, itercoect memory eed ever dictate die size for large, sigle-cotext, recofigurable compoets. As we begi to mae heavy use of the recofigurable aspects of programmable devices, device recofiguratio time becomes a importat factor determiig the performace provided by the part. I these rapid reuse scearios, itercoect ecodig desity ca play a sigificat role i determiig device area ad performace. 1. Oe techique for reducig the recofiguratio time is to store multiple, o-chip cotexts. Sice desigs ted to be wire ad switch limited, multiple o-chip cotexts eed ot substatially icrease die area. Multi-cotext desigs, however, geerally merit more dese itercoect ecodigs tha sigle-cotext desigs i order to miimize the impact which cofiguratio memory has o die size. For small umbers of cotexts, oe is, i effect, sacrificig some ecodig sparcity for extra, o-chip cotexts. For large umbers of cotexts, cofiguratio memory, ad hece ecodig desity, ca dictate device size. 2. Off-chip cotext reloads for sigle- or multi-cotext devices are slow because a large amout of cofiguratio data (typically, > 10 5 bits) must be trasfered across a limited badwidth i/o path. Trasferrig sparsely ecoded bitstreams across this i/o bottleec exacerbates already poor reload performace dictated by i/o badwidth limitatios. This paper starts out by idetifyig a simple metric for characterizig itercoectivity a cout of the umber of useful ad distict itercoectio patters. While simple, this metric turs out to be difficult to calculate i the geeral case. We ca, oetheless, aalyze a umber of commo structures to obtai bouds o the umber of patters provided by more complicated topologies. From this aalysis we observe that covetioal, programmable architectures have highly redudat programmig bit streams. The aalysis helps us idetify opportuities to save programmable memory area ad lower recofiguratio time by reducig that bit stream redudacy.

2 FPGA ACM/SIGDA Fourth Iteratioal Symposium o FPGAs February 11-13, 1996, Moterey, CA Itercoect Lut is source<3> source<2> source<1> source<0> sel<1> sel<0> Chael Coectios Figure 1: DPGA Iput Coectio si<j> source<i> RAM Cell si<j> Figure 2: Crossbar Crosspoit with Memory I the ext sectio, we ope with a motivatioal example to illustrate the issue ad aalysis. I Sectio 3, we defie the itercoectio metric more precisely. I Sectio 4, we loo at some basic itercoectio buildig blocs which ca be easily aalyzed i isolatio. Sectio 5 loos at some ideal or pedagogical etwor structures by composig the primitives from Sectio 4. Sectio 6 touches briefly o the role of placemet i itercoect flexibility. Sectio 7 loos at covetioal itercoect examples usig the results of Sectio 5 to estimate the amout of redudacy these devices exhibit. We discuss the implicatios ad impact of this redudacy i more detail i Sectio 8 before cocludig i Sectio 9. 2 Motivatioal Example Cosider a case where we wish to drive ay of sources oto each of m sis. I our DPGA prototype [7], for example, we eeded to drive the 4 iputs to the 4- from the 15 lies which physically coverged upo the cell (m = 4, = 15, See Figure 1). This id of structure is typical whe coectig logic bloc iputs to a routig chael. We could provide full coectivity by buildig a full crossbar betwee the = 15 sources ad m = 4 sis. This requires m, 60 i this case, crosspoits. If each crosspoit is built with its ow memory cell, as show i Figure 2, this arragemet etails equally may memory cells. At this poit it is worth otig that there are 2 60 > ways to program 60 memory cells, but may of those coectios are ot useful. I fact, of the memory cells alog each iput wire, at most oe should eable its crosspoit at ay poit i time. Sice each output should be drive by oe source, there are, i fact, oly m, (15) 4 = 50; 625 i this case, combiatios which may be useful. We ca, i fact, cotrol the m crosspoits with oly dm log 2 ()e memory cells, or 16 i this case. Here, each group of dlog 2 ()e bits serves to select which of the iputs should drive oto each of the m output lies (See Figure 3). If, as is the case for the DPGA, the logic bloc is a -iput looup table, eve this arragemet provides more routig flexibility tha is ecessary. There is, for istace, o eed for ay of the iputs Figure 3: Ecoded Crossbar Cotrol to be the same. Strictly speaig there are at most (i this m 15 example, = 1365) distict selectios of the = m iputs 4 from the sources. This implies we could get away with as few as 11 (dlog 2 (1365)e) cotrol bits if we icluded heavy decodig. From this calculatio we ca also coclude that ay combiatios provided beyod the 1365 distict itercoect patters etailed by the 15 choose 4 combiatios are redudat ad offer us o additioal fuctioality. This boudisofte usefuliuderstadigthe gross characteristics of a itercoect. All itercoects which provide all these combiatios are fuctioally equivalet. Above this poit we ca compare the umber of specificatio bits to the umber of requisite specificatio bits to uderstad the redudacy i the ecodig scheme. For itercoects providig less distict itercoect patters, we ca compare the umber of achievable itercoect patters to the maximum umber of distict itercoect patters to get a scalar metric of the flexibility of the itercoect. I practice, the DPGA prototype used 4, 8-iput muxes. This gave it oly 32 crosspoits requirig 4log 2 (8)=12 bits to specify the iput. Due to the limited size iput muxes, it oly supported 1217 distict iput combiatios. Our ecodig is withi oe bit of the theoretical miimum of 11 ad routes 89% of the 1365 combiatios idetified above. With respect to memory bits, we see that dese ecodig of the combiatios yields a more sigificat reductio i requisite memory cells tha depopulatig the crossbar i a memory-cell-percrosspoit sceario. I a uecoded case, 12 memory bits would ot eve support a sigle coectio from each of the 15 potetial iputs. Of course, miimizig the umber of memory bits does ot, ecessarily,produce the smallest layout sice dese ecodigs must be decoded ad routed. We will visit this issue i Sectio 8. This example uderscores several issues which are worthwhile to uderstad whe desigig programmable itercoect. Idepedetly programmig each crosspoit leads to highly redudat itercoect programmig, icludig a large space of o-useful cofiguratio specificatios. The umber of bits required to cofigure a itercoect ca be much lower tha the umber of pass gates or crosspoits i the itercoect. The umber of useful cofiguratios provided by a piece of itercoect caot be determied by looig at the itercoect i isolatio. Whe we cosider the cotext i which the itercoect is used, may of its cofiguratio may become redudat.

3 FPGA ACM/SIGDA Fourth Iteratioal Symposium o FPGAs February 11-13, 1996, Moterey, CA Simple bouds o the theoretical ecodig desity ad required flexibility are helpful i evaluatig the gross merits of various proposed itercoect solutios. c<1:0> c0 c1 c0 c1 c2 c2 3 Itercoectio Metric c3 c3 The itercoectio metric we are focusig o here is to cout: the umber of uique ad useful coectio patters which the etwor ca realize. Useful Coectios With sparse ecodig, may bit combiatios may be parasitic or o-useful. I the bit-per-crosspoit example above, we saw that it was ot useful to have more tha oe crosspoit eabled alog a output lie. I these cases, a large portio of the etire bit stream ecodig space refers to itercoectio patters which are at best osesical ad may eve be damagig to the part. Uique Coectios A itercoectio patter which provides the same fuctioality as aother specifiable patter adds o capability to the itercoect. That is, the flexibility which allows both specificatios provides o additioal itercoect power. I the example above, we saw that a full crossbar provided (15) 4 = 50; 625 specifiable coectios. However, with the coectios feedig ito a 4-, a patter which brig iputs 15, 13, 10 ad 7 ito the is o differet from a patter which brigs iputs 10, 15, 7 ad 13 ito the. The full crossbar thus provides 50; 625, 1; 365 = 49; 260 redudat patters which add o fuctioality to the itercoect. It is worthwhile to ote that itercoect flexibility as used here ca be applied to ay itercoectio etwor or family of graphs. As such it is very differet from the itercoect flexibility defied i [6] [3] which is used to describe the level of populatio of switches i a particular itercoect family. Itercoectio Patters It is importat that we loo at the itercoectio patters as a whole to uderstad which patters are fuctioally idetical. Agai, looig at the - iput selector i isolatio from the logic bloc, we ca idetify more distict patters tha we see whe viewed i a esemble. It is also sigificat that the metric loos at the esemble of itercoectios feasible rather tha looig at the itercoect flexibility afforded to a sigle iput i isolatio. Sice resources are typically shared, the focus o patters accouts for the limited availability of shared resources. 4 Basic Primitives I this sectio we idetify a few basic primitives used i buildig itercoectio etwors. We cout the umber of itercoectio patters they provide, as well as relatig the abstract primitives to their more physical implemetatios. Muxes A -iput multiplexor (mux) ca coect ay of its iputs to its output. I isolatio, the multiplexor realizes Figure 4: Multiplexor Symbol with Three Potetial Implemetatios c<1> c<0> Figure 5: 8 8 Crossbar distict itercoect patters, requirig dlog 2 ()e bits to specify its behavior. Figure 4 shows a multiplexor ad several possible implemetatios. Note that a series of tristate drivers attached to a sigle, physical wire serves logically as a multiplexor ad ca be treated as oe for the purposes of aalysis. This remais true whether the tristate drivers have separate or cetral cotrol. The series of tristate drivers with distributed cotrol has the additioal ability to drive o value oto the lie, but this offers o additioal logical fuctioality sice we ca just as easily drive ay value oto the output i such a case. The tristate drivers could also have multiple values drive simultaeously oto the output, but, uless this is used to perform a logical fuctio, the multiple drive cases are parasitic rather tha useful behavior. Crossbars A crossbar has a set of iputs ad a set of m outputs ad ca coect ay of the iputs to ay of the outputs with the restrictio that oly oe iput ca be coected to each output at ay poit i time. Logically, a m crossbar is equivalet to m-iput multiplexors. The crossbar ca realize m distict itercoect patters ad requires dm log 2 ()e bits to specify its behavior. The crossbar represets the most geeral id of itercoect ad ca ofte be used to calculate a upper boud o the flexibility which could be offered by a piece of itercoect. A small crossbars is show i Figure 5. We have already see some potetial implemetatios i Figures 2 ad 3. Subset Selectio With subset selectio, we select a group of m outputs from iputs. We saw this selectio whe routig the iputs to a -. This id of selectio is also typical whe cocetratig outputs from oe regio dow to a limited size chael coectig to aother regio of the compoet. As we saw i Sectio 2, this fuctio is ot as trivially implemeted as the crossbar, but the fuctio is frequetly desired maig this primitive highly

4 FPGA ACM/SIGDA Fourth Iteratioal Symposium o FPGAs February 11-13, 1996, Moterey, CA useful for aalysis. Subset selectio etails distict itercoectio patters ad requires log 2 bits to specify its m m behavior. Pass gates Idividual pass gates are too primitive to geerally be useful from a aalysis stadpoit. Aloe, each pass gate has 2 itercoectio states which ca be specified with oe bit. From a aalysis stadpoit it is geerally more useful to group collectios of pass gates together ito a larger structure. As oted above, whe the directio of sigal flow is apparet, groups of pass gates used to selectively drive oto a sigle lie effectively form a logical multiplexor. 5 Compositio Examples I this sectio we apply ad compose the primitives of the previous sectio to examie a few families of etlists ad etwors of geeral iterest. Netlists of -iput logic blocs Let us cosider the family of etlists with logic blocs where each logic bloc has at most iputs. Further, the etlist has i iputs ad o outputs. To get a upper boud, we assume all logic blocs may provide a distict fuctio. I geeral, each of the logic bloc iputs may wat ay of the logic bloc outputs or ay of the i iputs. Each output may come from ay of the logic bloc outputs. There are (i+) () possible itercoect patters for the ( ) logic bloc iputs ad o itercoectio patters for the outputs. All together, there are o (i + ) () itercoectio patters which the etlist may exhibit. Without exploitig placemet (See Sectio 6), if all itercoects are give equally log descriptios, it will require at least do log 2 ()e + d log 2 (i + )e bits to describe each itercoectio patters. Networ for -iput logic blocs I a similar maer, we ca loo at a device or itercoect ad boud the umber of itercoectio patters it provides. Agai, assumig we have logic blocs with iputs eachalogwith iiputs adooutputs, if we do ot allow iputs to be directly coected to outputs, we have a total umber of itercoectio patters of, at most: N o direct io patters o (i + ) () (1) If iputs ca be directly coected to outputs, we have(i+) o possible output patters for a total umber of itercoectio patters bouded by: N direct io patters (i + ) o (i + ) () (i + ) (+o) (2) For may devices, each iter-chip i/o pi ca serve as either a output with eable or a iput. We thus let o = 2i, assumig we may have to route both the output ad the eable for each iter- physical pi, ad have a total of at most (i + ) (+2i) coectio patters. The itercoect ca thus be specified with d( + 2i) log 2 (i + )e cofiguratio bits. Elemet Number of Logic Blocs Logic Bloc Area Logic Bloc Cofiguratio Itercoect Cofiguratio Growth O() O() O( log()) Crosspoits/switches O( 2 ) Wire O( 2 ) Table 1: Growth Rates for Key Elemets of a Fully Flexible Programmable Device From this ad the previous example, it is worth observig that etwor cofiguratio requiremets are growig as O( log()) assumig is fixed ad i grows at most liearly i proportio to. We ca compare this to the cofiguratio requiremets for the logic which are growig as O(). We ca also compare this with the umber of crosspoits or total legth of itercoect wire which is growig as O( 2 ) if we are goig to provide the full itercoect to support ay of the possible -ode etlists. These geeral observatios, summarized i Table 1, are worthwhile to remember. Asymptotically, they tell us wires ad crosspoits will be the pacig items for offerig flexibility i programmable devices. They also tell us to expect itercoect programmig to grow faster tha logic cell programmig. We ca describe ay itercoect much more cheaply tha we ca spatially route it, uderscorig the eed to reuse physical crosspoits ad wires i time as we build larger programmable devices ad systems. Networ of -s If a device s etwor is built etirely out of -s, we ca get a slightly tighter boud o the umber of itercoectio patters provided. Agai, our source of iputs is the outputs ad the i iputs. Each must choose iputs i from (i + ) + sources. Together, this maes for total itercoectio patters. If we also assume o = 2i ad outputs ca come directly from iputs, the total umber of itercoectio patters is at most: N lut itercoect patters i + (i + ) (2i) (3) The differece betwee this case ad the previous isthat the etwor, sas output coectios, has at most patters i + rather tha, (i + ). The ratio betwee these two expressios is: 0 1 B (i + ) i + A For large (+i) ad small, (+i), 1 (+i), (+i). This ratio is the roughly (!). I terms of cofiguratio bits, this amouts to log 2 (!) a small savigs liear i for fixed. e.g. for = 4, oe ca save at most 4-5 etwor cofiguratio bits per by exploitig the iput pi equivaleces. Referrig bac to

5 FPGA ACM/SIGDA Fourth Iteratioal Symposium o FPGAs February 11-13, 1996, Moterey, CA Logical Arragemet 0f 2 s: 1,0 1,1 0,0 0,1 etwor coectios (same for all s) 0,0 0,1 1,0 1,1 out Figure 6: Limited Itercoect Networ of 4, 2-s Table 1, this tells us that exploitig iput equivaleces saves us O() cofiguratio bits, but does ot, fudametally, chage the growth rate for itercoect cofiguratio. 6 Placemet Freedom Oce we idetify a level of desired itercoect flexibility, it is ot ecessaryfor the physicalitercoectio etwor to solely provide that flexibility. I programmable devices, we also have freedom i where we place fuctios ad results withi the itercoectio etwor. The et result of this freedom is that we ca achieve a give flexibility N patters with a etwor which provides fewer tha N patters itercoectio patters., This alsomeas we could, i theory at least, use less tha log 2 Npatters bits to specify the itercoect patter whe we observe that the placemet of fuctios ad results relative to the etwor also gives us a degree of specificatio freedom. To mae this cocrete, let us cosider a very simple itercoectio problem where we wish to itercoect 4 2-iput s 4 ( = 4, = 4 2). We ow there are 2 = 1296 possible itercoectio etwors for this small example. First, we cosider a limited itercoectio etwor where we arrage the four s ito a 2 2 array. Each has oe iput which may come from either i the first colum ad a secod iput which may come from either i the secod colum (See Figure 6). Each of the (2 4) =8 iputs i this restricted itercoect ca come from oe of two places, maig for a total itercoect flexibility of 2 8 = 256. It is also worthwhile to ote that all 256 itercoect combiatios are distict. If we had fixed the placemet of the 4 logic fuctios i the array, the we could oly realize these 256 itercoectpatters. Allowig the fuctios to be arraged withi the array allows greater flexibility. We ow there are 4! = 24 ways to place 4 logic fuctios i the 2 2 array. Because of the high symmetry of the physical etwor, it turs out that groups of 8 permutatios are equivalet with respects to routig. As a result there are 3 distiguishable placemet classes. This could provide us with at most = 768 itercoectio patters if all of the permuted itercoects were distict. I practice, this gives us 720 of the 1296 possible patters. Figure 7: Less Symmetric, Limited Itercoect Networ of 4, 2-s Usig a alterate itercoectio scheme with less symmetry, show i Figure 7, we ca get 6 distiguishable placemet classes ad achieve 1104 of the 1296 possible patters. The 1104 itercoectio patters are, of course, over a factor of four more patters tha the 8 bits of itercoect programmig could specify, aloe. This example uderscores the fact that placemet i asymmetric etwors allows us to expad the umber of realizable etwors for a give, limited, physical itercoect. Additioally, we see that successfully routig etwors i this scheme requires picig the correct permutatio for the etwor (placemet) ad the the correct itercoectio patter (routig). Asymmetry i the etwor ca have the effect of both icreasig the flexibility, by maig more itercoectio patters realizable, ad of maig the routig problem harder, by offerig a larger space of distict placemet classes to explore durig routig. I geeral, the extet to which placemet ca reduce the demad for itercoect resources, icludig wires, switches, ad cofiguratio bits, remais a ope issue. 7 Some Covetioal Architectures Table 2 summarizes the major characteristics for several cotemporary programmable devices. Additioally, a pure 4- desig is icluded for sae of compariso with the idustrial offerigs. We ca mae a rough, bac-of-the-evelope-style computatio o the bits required to cofigure the etwor by maig the assumptio that the etwor does support all potetial etwors without exploitig placemet flexibility. That is, we assume that the basic logic blocs are fully coected. Sice the covetioal offerigs are far from beig fully itercoected,this gives us a upper boud o the umber of etwor cofiguratio bits. Adaptig Equatio 2 ad taig the base two logarithm to covert to bits, we get: N et bits = d( bloc is blocs + io is io) (4) log 2 ( bloc outs blocs + io outs io)e We ca also calculate the umber of bits required to specify the logic bloc fuctios i the obvious maer: N logic bits = bloc logic bits blocs (5)

6 FPGA ACM/SIGDA Fourth Iteratioal Symposium o FPGAs February 11-13, 1996, Moterey, CA Part blocs io Programmig Bits Referece Xilix xc CLBs 192 IOBs 240K [9] Xilix xc CLBs 196 IOs 160K [10] Altera EPF LEs 184 IOEs 192K [2] [1] Pedagogical Referece s 200 Family bloc is bloc ous io is io outs bloc logic bits XC4K CLB = 40 XC5K CLB = 64 Altera 8K LE = 16 Referece = 16 Table 2: Parameters for a Samplig of Cotemporary Programmable Devices Part N et bits N logic bits Programmig Bits Uaccouted Cotrol Bits Xilix xc K 23K 240K o-logic CLB/IOB cofiguratio, edge decoders Xilix xc K 20K 160K o-logic CLB/IOB cofiguratio Altera EPF K 16K 192K LAB cotrol ad Peripheral Bus Pedagogical Referece 45K 16K Table 3 summarizes the results of these basic calculatios for the idetified compoets. The compariso is ecessarily crude sice vedors do ot provide detailed iformatio o their cofiguratio streams. However, we expect the uaccouted cotrol bits i Table 3 to ot be more tha 10% of the total device programmig bits. With this expectatio, we see that these devices exhibit a factor of two to three more itercoect cofiguratio bits tha would be required to provide full, placemet-idepedet, logic bloc ad i/o itercoect. We ca, of course, derive a tighter boud for the referece 4- desig by adaptig Equatio 3: N et bits = blocs log 2 Table 3: Cofiguratio Space versus Bit Stream Size blocs + io io outs + d io io is log 2 ( blocs + io io outs)e For the 1, case idetified above, N et bits 40K, savig roughly 5 bits per as suggested i Sectio 5. Eight of the 13 iputs o the XC4K go ito 4-s ad all 16 of the XC5K iputs go ito 4-s. Cosequetly, all of these arrays require comparably fewer etwor cofiguratio bits. The 4 iputs o the Altera 8K LE also go ito a 4-. Sice oe iput may also be used i a cotrol capacity, the reductio is slightly lower for the Altera 8K part. As we see i Table 1, we ultimately expect devices to be wire or switch limited. I the wire limited case, we may have free area uder log routig chaels for memory cells. I fact, dese ecodig of the cofiguratio space has the egative effect that cotrol sigals must be routed from the cofiguratiomemory cells to the switchig poits. The closer we try to squeeze the bit stream ecodig to its miimum, the less locality we have available betwee cofiguratio bits ad cotrolled switches. I Figure 3, for istace, we had to ru additioal cotrol lies ito the crossbar to cotrol the crosspoits. These cotrol lies compete with etwor wirig, exacerbatig the routig problems o a wire domiated layout. I a multiple cotext or switched itercoect case, the effects of memory desity are more proouced. Limited wire resources are reused i time, maig more efficiet use of the wires ad miimizig the effects of bisectio wirig limitatios. I these cases the chip eeds to hold may cofiguratios worth of memory simultaeously. If oe is ot careful about the desity of the itercoect cofiguratio ecodig, the cofiguratio memory stores ca domiate chip area. I the aforemetioed DPGA Prototype [7], for example, eve with four o-chip cotexts, wirig ad switchig accouted for over half of the die area. Networ cofiguratio memory made up about oe fourth of the area. A factor of 2-4 icrease i the cofiguratio memory due to sparser ecodig would have forced a substatial (20-60%) icrease i die area. 8 Impact of Cofiguratio Desity Area The total, o-chip cofiguratio memory ca be oe of the major cotributors to chip area (e.g. [4]). As such, redudacy i the cofiguratio space may cost additioal die area. The effect, however, is techology ad desig poit depedet. Whe the desig is active silico area limited, the cofiguratio size ca play a large factor i determiig desig size. However, whe the desig is wire limited, the redudat cofiguratio memory may be free or egligible. Performace I covetioal, sigle cotext FPGAs, the cofiguratio iputs to switches are static durig ormal operatio. Ay time associated with decodig switch cotrol from memories is ot i the critical path ad will ot affect the timig o sigal flow through the itercoect. I the rapidly switched, multiple cotext case, this is less true. Memory access ad decodig time defie the overhead required to chage betwee cotext cofiguratios. Recofiguratio Time The recofiguratio time of both sigle- ad multi-cotext recofigurable devices is directly im-

7 FPGA ACM/SIGDA Fourth Iteratioal Symposium o FPGAs February 11-13, 1996, Moterey, CA pacted by ecodig desity. As we have see i Sectio 7, cotemporary recofigurable devices have very large cofiguratio bit streams. Due to physical i/o limitatios, chagig bit streams is a expesive operatio. I cases of heavy device reuse this reload time ca have a sigificat effect o system performace (e.g. [5] [8]). Of course, the real problem associated with recofiguratio time is the i/o badwidth limitatio. It is certaily ot ecessary for the bits stored i the cofiguratio memories to be idetical to the off-chip itercoect specificatio or the specificatio trasmitted across the chip boudary. I wire limited cases, where local memory cells are iexpesive or free ad routig cotrol sigals are expesive, the device could decompress the cofiguratio specificatio durig cofiguratio reload time. For example, let us revisit the itercoectio example from Sectio 2 i the wire limited case. Here, we suppose the techology costs dictate that the memory-cell-per-crosspoit desig is more area efficiet tha the deser ecodig schemes idetified that sectio. We could build a sigle copy of the decoder for the 15 log 2 = 11 bit ecodig scheme. This sigle decoder 4 could the be used to decode each 11 bits of iput cofiguratio ito the 60 bits required to program the iput crossbar. As a result, we reduce the iput portio of the bitstream by a factor of 60 5:4 over the uecoded case. 11 It is worthwhile to ote at this poit that the compressio we are discussig here is desig idepedet. That is, the bouds o cofiguratio size we have derived throughout this paper are applicable across all possible itercoectio patters which a etwor may provide. It is also possible to exploit redudacy withi the desig to further compress the cofiguratio bit stream i a desig depedet maer. Safety Oe effect of dese ecodig is to elimiate parasitic cofiguratios. As oted, cofiguratio specificatios which allow multiple drivers sharig a commo lie to be eabled simultaeously are geeral parasitic. It is, i fact, possible to destroy may covetioal devices by uploadig parasitic cofiguratios. 9 Coclusios Sparse itercoect cofiguratio ecodigs ca result i bloated bit stream cofiguratios. Asymptotic growth rates suggest that dese ecodigs grow more slowly tha desired itercoect requiremets, placig desigs i a wire ad switch limited domai. Cosequetly,some ecodig desity may be judiciously sacrificed at the o-chip storage level to decrease cotrol itercoect i programmable devices. Multiple-cotext compoets, o the other had, have a greater demad for o-chip storage ad merit deser ecodig i order to mae effective use of silico area. Sparsely ecoded bit streams have their largest impact o cofiguratio load time. As device size icreases ad the recofigurable aspects of programmable devices are heavily exploited, the i/o badwidth limited recofiguratio time becomes a sigificat performace factor. Dese cofiguratio ecodig ca be exploited to miimize the exteral storage space required for cofiguratios ad the trasmissio time required to commuicate cofiguratios. At a broader level, we have focussed o itercoect flexibility to establish gross bouds o the iformatio required to cofigure a device. We demostrated simple buildig blocs ad metrics for gaugig the flexibility of a itercoect ad apprisig the level of redudacy i a particular itercoect descriptio. These tools ca be useful for first order aalysis of programmable itercoect desigs. Acowledgmets This research is supported by the Advaced Research Projects Agecy of the Departmet of Defese uder Rome Labs cotract umber F C Refereces [1] Altera Corporatio, 2610 Orchard Parway, Sa Jose, CA FLEX 8000 Hadboo, May [2] Altera Corporatio, 2610 Orchard Parway, Sa Jose, CA Data Boo, March [3] Stephe D. Brow, Robert J. Fracis, Joatha Rose, ad Zvoo G. Vraesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 101 Philip Drive, Assiippi Par, Norwell, Massachusetts, USA, [4] Richard Guo, Hug Nguye, Adi Sriivasa, Quaid Nasir, Hog Cai, Steve Law, ad Amar Mohse. A Novel Reprogrammable Itercoect Architecture with Decoded RAM Storage. I Proceedigs of the IEEE 1994 Custom Itegrated Circuits Coferece, pages IEEE, May [5] Chris Joes, Joh Oswald, Bria Schoer, ad Joh Villaseor. Issues i Wireless Video Codig usig Ru-timerecofigurable FPGAs. I Peter Athaas ad Ke Poce, editors, Proceedigs of the IEEE Worshop o FPGAs for Custom Computig Machies, Los Alamitos, Califoria, April IEEE Computer Society, IEEE Computer Society Press. [6] Joatha Rose ad Stephe Brow. Flexibility of Itercoectio Structures for Field-Programmable Gate Arrays. IEEE Joural of Solid-State Circuits, 26(3): , March [7] Edward Tau, Ia Eslic, Derric Che, Jeremy Brow, ad Adré DeHo. A First Geeratio DPGA Implemetatio. I Proceedigs of the Third Caadia Worshop o Field- Programmable Devices, pages , May [8] Michael J. Wirthli ad Brad L. Hutchigs. A Dyamic Istructio Set Computer. I Peter Athaas ad Ke Poce, editors, Proceedigs of the IEEE Worshop o FPGAs for Custom Computig Machies, Los Alamitos, Califoria, April IEEE Computer Society, IEEE Computer Society Press. [9] Xilix, Ic., 2100 Logic Drive, Sa Jose, CA The Programmable Logic Data Boo, [10] Xilix, Ic., 2100 Logic Drive, Sa Jose, CA XC5200 Logic Cell array Family Techical Data, prelimiary (v1.0) editio, April 1995.