C.Yaashuwanth Department of Electrical and Electronics Engineering, Anna University Chennai, Chennai , India..

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1 (IJCSIS) Iteratioal Joural of Computer Sciece ad Iformatio Security, A New Schedulig Algorithms for Real Time Tasks C.Yaashuwath Departmet of Electrical ad Electroics Egieerig, Aa Uiversity Cheai, Cheai , Idia.. Abstract - The mai objective of this paper is to develop the two differet ways i which roud robi architecture is modified ad made suitable to be implemeted i real time ad embedded systems. The schedulig algorithms plays a sigificat role i the desig of real time embedded systems. Simple roud robi architecture is ot efficiet to be implemeted i embedded systems because of higher cotext switch rate, larger waitig time ad larger respose time. Missig of deadlies will degrade the system performace i soft real time systems. The mai objectives of this paper is to develop the schedulig algorithms which removes the drawbacks i simple roud robi architecture. A compariso with roud robi architecture to the proposed architectures has bee made. It is observed that the proposed architectures solves the problems ecoutered i roud robi architecture i soft real time by decreasig the umber of cotext switches waitig time ad respose time thereby icreasig the system throughput. Key words - Roud robi architecture, time slice, deadlies, soft real time. I. INTRODUCTION This paper describes the two differet ways i which roud robi architecture is modified ad made suitable to be implemeted i real time ad embedded systems The ew approach describes the schedulig of processes i modified roud robi architecture. Simple roud robi architecture is ot efficiet if the taskset has processes with variable CPU burst because the processes arrivig i roud robi will be allocated time slice i first come first serve maer. This drawbacks of variable process bursts of processes i a taskset leads to larger waitig time. The larger respose time of processes with less CPU burst which leads to icrease i waitig time ad respose time of system thereby degradig the system performace The proposed algorithm has the advatage of processes with less CPU burst will have a better waitig time ad respose time tha compared to simple roud robi architecture ad covers the drawbacks of roud robi architecture by reducig the waitig time ad reducig the respose time thereby icreasig the system throughput Dr.R.Ramesh Departmet of Electrical ad Electroics Egieerig, Aa Uiversity Cheai, Cheai , Idia.. The secod approach describes the calculatio of itelliget time slice for roud robi architecture is a modified versio of simple roud robi architecture. Simple roud robi architecture caot be implemeted i soft real time systems because of high cotext switch rate, larger waitig time ad larger respose time. Because of these performace criteria of the roud robi architecture is ot suitable to implemet i real time systems. Soft real time systems have o hard deadlies for tasks but missig of deadlies i soft real time systems will degrade the system performace. Real time systems always has a time costrait o computatio. Each task should be ivoked after the ready time ad must complete before its deadlie[12][13][14], a attempt has bee made to satisfy these costraits. Simple roud robi architecture[1] is ot suitable to implemet i softreal time due to more o of cotext switches, loger waitig ad respose times. This i tur leads to low throughput i the system. Richard roehi[3] proposed a ew way of schedulig which implemets a ew priority queue i the roud robi architecture that gives priority to tasks with short CPU burst thereby improvig the performace of the tasks with less cetral processig uit (CPU) burst. Fair schedulig with tuable latecy[8] is a Roud Robi approach that proposes a alterative ad lower complexity approach to packet schedulig, based o modificatios of the classical Roud Robi scheduler. The authors showed that appropriate modificatios of the weighted Roud Robi (WRR) service disciplie ca, i fact, provide tight fairess properties ad efficiet delay guaratees to multiple sessios. Roud robi approach has its applicatios o etworks by allowig the etwork devices to have a free share of etwork resources. Various types of schedulig algorithms such as Dificit roud robi [6], Dificit roud robi alterated [4] ad credit roud robi[7] have bee implemeted. Real-time schedulig theory has show a trasitio from cyclical executive based ifrastructure to a more flexible schedulig models such as fixed-priority schedulig, dyamic-priority schedulig, feedback schedulig or exteded schedulig[10]. I fact, recet studies show that almost every existig real-time operatig system provides oly POSIXcompliat fixed-priority schedulig [11] sice it ca be easily implemeted i commercial kerels,. I task schedulig policies for real time system the author[1] has discussed the basic architecture of fixed priority schedulig which implies 61

2 that there will be sigle server ad the jobs will be allocated based o the priority give by the user. A. Burs[5] proved that stadard aalysis of fixed priority assumes that all the computatios of each task must be completed i task deadlies but i practice this is ot the case, deadlies is most curretly associated with last observed evet of the task. Reidir ad Pieter revealed[2] the worst case respose time aalysis of real time tasks usig hierchial fixed priority schedulig.usig a example which cosist of sigle server the author portrays that the existig worst case respose time aalysis ca be improved. With these observatios it is foud that these existig simple roud robi architecture are ot suitable to be implemeted realtime embedded system. The proposed algorithms are a modified versio of roud robi algorithm with shortest jobs schedulig of tasks i roud robi ad itelliget time slicig cocept. II. ROUND ROBIN ARCHITECTURE Roud robi architecture is a pre emptive versio of first come first serve schedulig algorithm. The processes are arraged i the ready queue i first come first serve maer ad the executes the process from the ready queue based o time slice. If the time slice eds ad the processes are still executig o the the scheduler will forcibly pre-empt the executig process ad keeps it at the ed of ready queue the the scheduler will allocate the to the ext process i the ready queue. The preempted process will make its way to the begiig of the ready list ad will be executed by the from the poit of iterruptio. A scheduler requires a time maagemet fuctio to implemet the roud robi architecture ad requires a tick timer. The time slice is proportioal to the period of clock ticks. The time slice legth is critical issue i soft real time embedded applicatio as missig of deadlies will have egligible effects i the system performace. The time slice must ot be too small which results i frequet cotext switches ad should be slightly greater tha average process computatio time. A. Roud Robi Drawbacks i Operatig Systems Roud robi whe implemeted i soft real time systems faces two drawbacks they are high rate of cotext switch ad low throughput. These two problems of roud robi architecture are iterrelated. B. Larger waitig time ad Respose time I roud robi architecture the time the process speds i the ready queue waitig for the to get executed is kow as waitig time ad the time the process completes its (IJCSIS) Iteratioal Joural of Computer Sciece ad Iformatio Security, job ad exits from the taskset is called as tur aroud time. Larger waitig ad respose times are clearly a drawback i roud robi architecture as it leads to degradatio of system performace. C. Low throughput Throughput is defied as umber of process completed per time uit. If roud robi is implemeted i soft real time systems throughput will be low which leads to severe degradatio of system performace. If the umber of cotext switches is low the the throughput will be high. Cotext switch ad throughput are iversely proportioal to each other. D. Cotext Switch Whe the time slice of the task eds ad the task is still executig o the the scheduler forcibly pre empts the tasks o the ad stores the task cotext i stack or registers ad allocates the to the ext task i the ready queue. This actio which is performed by the scheduler is called as cotext switch. Cotext switch leads to the wastage of time, memory ad leads to scheduler overhead. These drawbacks are elimiated i the modified versio of roud robi described i the ext sectios. III. MODIFIED ROUND ROBIN ALGORITHMS FOR REAL TIME EMBEDDED SYSTEM A. Shortest roud Robi Architecture The proposed architecture focuses o the drawbacks of simple roud robi architecture which gives equal priority to all the processes (processes are scheduled i first come first serve maer) Because of this drawback roud robi architecture is ot efficiet for processes with smaller CPU burst. This results i the icrease i waitig time ad respose time of processes which results i the decrease i the system throughput. The proposed architecture elimiates the defects of implemetig a simple roud robi architecture i by schedulig of processes based o the CPU burst, A dedicated small used to reduce the burde of the mai is assiged for rearragig of processes i the ascedig order based o the CPU burst of the process (lower to higher) The proposed architecture has greater waitig time respose time ad throughput thereby improvig the system performace. The process schedulig i proposed architecture is show i figure

3 P 1 25 P 2 5 P 3 15 P 4 8 P 5 10 Dedicated small Figure 3.1 Process schedulig i shortest roud robi P 2 5 P 4 8 P 5 10 P 3 15 (IJCSIS) Iteratioal Joural of Computer Sciece ad Iformatio Security, small dedicated which calculates the ew time slice Time slice dedicated to the correspodig tasks. The output of small dedicated will be the task id o, CPU burst ad the P 1 calculated time slice these criteria are give to the mai Mai. These dedicated time slice are differet ad are 25 exclusively allocated for each tasks ad the tasks execute o the based o these time slicig. Thus the proposed architecture is superior to existig simple roud robi architecture ad ca be implemeted i soft real time systems. B. Itelliget time slice for Roud robi i soft real time schedulig The proposed architecture focuses o the drawbacks of simple roud robi architecture which are cotext switch, equal priority to all the tasks Because of these drawbacks roud robi architecture is ot suitable for softreal time systems. I soft real time systems the missig of task deadlies are ot catastrophic but have a egligible effects o the system which results i degradatio of system performace. The proposed architecture elimiates the defects of implemetig a simple roud robi architecture i softreal time system by itroducig a cocept called itelliget time slicig which depeds o three aspects they are priority, average CPU burst, cotext switch avoidace time. The proposed architecture allows the user is allowed to assig priority to the system. A assumptio is made o average CPU burst which are reasoable to the system. A dedicated small used to reduce the burde of the mai is assiged for calculatig the time slice. The calculated time slice will be differet ad idepedet for each tasks ad the tasks are fed ito the ready queue ad these tasks execute i the mai with their idividual time slices. The proposed architecture ca be implemeted i softreal time because of greater respose time ad throughput ad the users ca allocate priority to every idividual task. The itelliget time slice are calculated by the dedicated small as show i figure.4.1 Time Slice Itelliget Time Slice Calculatio A ew way of itelliget time slice calculatio has bee proposed which allocates the frame exclusively for each task based o priority, shortest CPU burst time ad cotext switch avoidace time. Let the origial time slice (OTS) is the time slice to be give to ay process if it deserves o special cosideratio. Itelliget time slice = Origial Time Slice(OTS)+ Priority Compoet (PC)+ Shortess Compoet for CPU burst time (SC)+ Cotext Switch Compoet(CSC) equatio 1 Priority compoet (PC) is assiged by the user depedig upo the priority which is iversely proportioal to the priority umber (higher the priority, greater the PC). Shortess compoet (SC) is assiged iversely proportioal to the legth of the ext CPU burst for the process. Shortest compoet should be lesser tha assumed CPU burst (ATS). Cotext Switch Compoet(CSC) is calculated as follows: o Calculate the Computed Compoet (CC): Priority Compoet (PC) ad Shortess Compoet (SC) are added to the Origial Time Slice (OTS). Computed compoet (CC) = Priority Compoet(PC) + Shortess Compoet (SC) + Origial Time Slice (OTS) Task 1. Cpu burst Priority Dedicated small Task 1. Itelliget time slice Mai o CC is deducted from the Assumed CPU burst (ATS). Let the result be called balace CPU burst. Balaced CPU burst = Assumed Time Slice(ATS) Computed Compoet (CC) Figure 3.2 Itelliget time slice geeratio. The priority, average CPU burst ad cotext switch avoidace time alog with origial time slice is give to the If this balace CPU burst is less tha OTS, it will be cosidered as Cotext Switch Compoet (CSC). IV. CASE STUDY 63

4 (IJCSIS) Iteratioal Joural of Computer Sciece ad Iformatio Security, Five processes has bee defied (with its priority), these five processes are scheduled i roud robi ad also i the proposed architecture. The cotext switch, waitig time, tur aroud time has bee calculated ad the results were compared. The process id, burst time ad priority are defied as show i table 4.1 TABLE 4.1 INPUT COMPONENT FOR THE PROCESSOR Process ID CPU burst time (millisecods) Priority A. Roud robi architecture Time slice = 4m.sec. The above five processes has bee scheduled usig simple Roud Robi architecture. The time slice of four millisecods has bee used. I roud robi algorithm o process is allocated CPU for more tha oe time slice i a row. If the CPU process exceeds oe time slice, the cocer process will be preempted ad put ito the ready queue. The process is preempted after the first time quatum ad the CPU is give to the ext process which is i the ready queue (process P2), similarly schedules all the process ad completes the first cycle I the secod cycle process P2 requires oe millisecod time slice (does t require four millisecods time slice), so it quits before its time quatum expires. The CPU is give to ext process P3. I the same way all other processes i the system are scheduled oce each process have received oe time slice the CPU is retured to process P1 for additioal time slice. The process time slicig i simple Roud Robi architecture is show i figure.5.1 P1 P2 P3 P4 P5 P1 P2 P P4 P5 P1 P3 P5 P1 P P1 P1 P Time Iterval Figure 4.1 Time slicig i Roud Robi architecture B. Shortest roud robi architecture The figure 4.2 shows the schedulig of five processes usig the proposed architecture P2 P4 P5 P3 P1 P2 P4 P P3 P1 P5 P3 P1 P3 P P1 P1 P Time Iterval Figure 4.2 Proposed architecture The above five process has bee scheduled by the proposed architecture with time slice of four millisecods. process P2 is allocated first to the sice it has the smallest CPU burst. It executes its time slice of 4 millisecods ad is pre empted by the. The is the allocated to ext process with smallest CPU burst process P4. i the same way completes the cycle by allocatig oe uit time slice to all the process. I the secod cycle the process p2 has oly oe millisecod to execute, after completig the executio of process p2 the is pre empted ad allocated to process P4 ad the cycle is repeated i roud robi fashio till all the tasks complete their CPU burst. C. Itelliget time slice for roud robi architecture The above five processes has bee scheduled usig proposed architecture. Itelliget time slice has bee calculated usig the equatio-1 ad the calculated itelliget time slice is show i table 4.2 TABLE 4.2 CALCULATION OF INTELLIGENT TIME SLICE FOR ROUND ROBIN ARCHITECTURE Process CPU Calculated time slice (millisecods) ID burst OTS PC SC CSC Itelliget time slice

5 (IJCSIS) Iteratioal Joural of Computer Sciece ad Iformatio Security, The itelliget time slice of process P1 is same as the origial time slice of four millisecods ad time slice of four millisecods is assiged to process P1. After the executio of four millisecods time slice the CPU is allocated to process P2. Sie the CPU burst of process P2 is lesser tha the assumed CPU burst (ATS), oe millisecods of SC has bee icluded. The process P3 has the highest priority, so priority compoet is added ad the total of five millisecods is allocated to process P3. The Balaced CPU burst for process P4 is leaser tha OTS, cotext switch compoet is added ad a total of eight millisecod time slice is give to process P4. Process P5 is give a total of five millisecods with oe millisecod of priority compoet is added to origial time slice. After executig a cycle the will agai be allocated to process P1 for the ext cycle ad cotiuously schedules i the same maer. The process time slicig i proposed architecture is show i figure 4.3 TABLE 4.3 COMPARISON ROUND ROBIN SHORTEST ROUND ROBIN Algorithm Waitig time i millisecods Tur aroud time i millisecods Simple roud robi Shortest roud robi Itelliget time slice for roud robi P1 P2 P3 P4 P P1 P3 P5 P1 P Figure 4.3 Time slicig i Proposed architecture 2 Waitig time ad tur aroud time has bee calculated usig the formula give below ad the results were compared. Waitig time is calculated by i= 1 P1 P1 P Time Iterval wt i wt waitig time of process. No. of process. Tur aroud time is calculated by i= 1 tt i tt tured aroud time of process. No. of process. The computed results are tabulated ad tabulated i table 4.2 V. CONCLUSION AND FUTURE WORKS A comparative study of roud robi architecture shortest roud robi ad itelliget time slice for roud robi architecture is made. It is cocluded that the proposed architectures are superior as it has less waitig, respose times, usually less preemptio ad cotext switchig thereby reducig the overhead ad savig of memory space. Future work ca be based o this architectures modified ad implemeted for hard real time system where hard deadlie systems require partial outputs to prevet catastrophic evets. VI. REFERENCES [1] Barbara Korousic Seljak (1994) Task schedulig policies for real-time systems Joural o MICROPROCESSOR AND MICROSYSTEMS, VOL 18, NO. 9, pg [2] Reidir J. bril ad Pieter J.L. Cuijpers (2006) Aalysis of hierchial fixed priority preemptive schedulig TU/e, CS-Report 06-36, [3] Richard roehi (1995) Desigig a fairer roud robi schedulig algorithm SIGCOMM 95 Cambridge, MA USA 0 ACM. [4] Marco.J,. Meziat.D,. Alarcos.B Dificit roud robi alterated : a ew schedulig algorithm _ E.P Alcalá de Heares, Spai. pdf [5] Burs.A (1994) Fixed priority schedulig with deadlie prior to completio Real-Time systems Research Group Departmet of computer sciece uiversity of york, UK. [6] Shreedhar. M, George Varghese (1996) Efficiet fair queuig usig deficit roud robi IEEE/ACM 65

6 (IJCSIS) Iteratioal Joural of Computer Sciece ad Iformatio Security, TRANSACTIONS ON NETWORKING VOL 4, NO3, pg [7] Viet.L.Do ad Keeth Y.Yu (2003) A Efficiet Frame based schedulig Algorithm: Credit roud robi Sa Diego, IEEE. [8] Klaus H. Ecker, (1996) Solvig Hard Real-Time Schedulig Problems o a Sigle Processor: IEEE Proceedigs of the 4th WPDRTS. [9] Sara. R,Biyabai, Joh A. Stakovic, Krithi Ramamitham (1988) The Itegratio of Deadlie ad Criticaless i Hard Real-Time Schedulig Sara R IEEE. [10] Sha, L., Abdelzaher, T, Arze, K., Cervi, A., Baker, T.P., Burs, A., Buttazzo, G., Caccamo, M., Lehoczky, J., ad Mok, (2004) A. Real time schedulig theory: A historical perspective. Real-Time Systems, 28(2): pdf [11] Ripoll I. et al. (2003 ) RTOS state of the art aalysis. Techical report, OCERA Project. [12] Erico Bii ad Giorgio C. Buttazzo (2004) Schedulability Aalysis of Periodic Fixed Priority Systems joural o IEEE TRANSACTIONS ON COMPUTERS VOL 53 NO.11, pg [13] Zhi Qua ad Jog-Moo Chag (2003) A Statistical Framework for EDF Schedulig joural o IEEE COMMUNICATION LETTERS VOL 7 NO.10, pg [14] Houssie Chetto ad Marylie Chetto (1989) Some Results of Earliest Deadlie Schedulig Algorithm joural o IEEE TRANSACTION ON SOFTWARE ENGINEERING. VOL 15. NO.10, pg About the authors Mr. C.Yaashuwath completed his B.Tech. degree i Iformatio techology at BSA CRESCENT Egieerig College Cheai, He completed M.E. i Embedded System Techologies at VEL TECH Egieerig College Cheai Dr. R. Ramesh pursued his B.E. degree i Electrical ad Electroics Egieerig at Uiversity of Madras, Cheai, ad completed his M.E. degree i Power Systems Egieerig at Aamalai Uiversity, Chidambaram. He received his Ph.D. degree from Aa Uiversity Cheai ad has bee a faculty of Electrical ad Electroics Egieerig Departmet of College of Egieerig Guidy, Aa Uiversity Cheai sice His areas of iterest are Real-time Distributed Embedded Cotrol, O-lie power system aalysis ad Web services. 66