1024MB DDR2 SDRAM SO-DIMM

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1024MB DDR2 SDRAM SO-DIMM Apacer Memory Product Specification 1024MB DDR2 SDRAM SO-DIMM based on 128Mx8,8Banks, 1.8V DDR2 SDRAM with SPD Features Performance range ( Bandwidth: 5.3 GB/sec ) Part Number Max Freq. (Clock) Speed Grade 75.073AR.G04 333MHz(3ns@CL5) 667Mbps JEDECstandard 1.8V ± 0.1V Power Supply VDDQ = 1.8V± 0.1V Internal Bank: 8 Bank Posted CAS Programmable CAS Latency: 3, 4, 5 Programmable Additive Latency: 0, 1, 2, 3 and 4 Write Latency(WL) = Read Latency(RL) -1 Burst Length: 4, 8(Interleave/nibble sequential) Programmable Sequential / Interleave Burst Mode Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) Off-Chip Driver(OCD) Impedance Adjustment On Die Termination Refresh and Self Refresh Average Refesh Period 7.8us Serial presence detect with EEPROM Compliance with RoHS Compliance with CE Operating Temperature Rang: Industrial -40 C TC 95 C -40 C TA 85 C Refresh: auto-refresh, self-refresh Average refresh period 7.8us at 0 C TC 85 C 3.9us at 85 C TC 95 C

Description This module is 128M bit x 64 x1rank Double Data Rate SDRAM high density memory modules based on first generation of 1024MB DDR2 SDRAM respectively. It consists of eight CMOS 128M x 8 bit with 8banks Double Data Rate SDRAMs in 60Ball FBGA packages mounted on a 200pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR2 SDRAM. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Industrial Temperature The industrial temperature option, if offered, has two simultaneous requirements: ambient temperature surrounding the device cannot be less than 40 C or greater than +85 C, and the case temperature cannot be less than 40 C or greater than +95 C. JEDEC specifications require the refresh rate to double when TC exceeds +85 C; this also requires use of the high-temperature self refresh option. Notes: MAX operating case temperature TC is measured in the center of the package Device functionality is not guaranteed if the device exceeds maximum TC during operation. Both temperature TA and TC specifications must be satisfied. Operating ambient temperature surrounding the package.

Pin Configurations (Front side/back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 V REF 2 V SS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 3 V SS 4 DQ4 53 V SS 54 V SS 103 V DD 104 V DD 153 DQ43 154 DQ47 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 V SS 156 V SS 7 DQ1 8 V SS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52 9 V SS 10 DM0 59 V SS 60 V SS 109 WE 110 S0 159 DQ49 160 DQ53 11 DQS0 12 V SS 61 DQ24 62 DQ28 111 V DD 112 V DD 161 V SS 162 V SS 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC, TEST 164 CK1 15 V SS 16 DQ7 65 V SS 66 V SS 115 NC/S1 116 A13 165 V SS 166 CK1 17 DQ2 18 V SS 67 DM3 68 DQS3 117 V DD 118 V DD 167 DQS6 168 V SS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6 21 V SS 22 DQ13 71 V SS 72 V SS 121 V SS 122 V SS 171 V SS 172 V SS 23 DQ8 24 V SS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 V SS 28 V SS 77 V SS 78 V SS 127 V SS 128 V SS 177 V SS 178 V SS 29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CK0 81 V DD 82 V DD 131 DQS4 132 V SS 181 DQ57 182 DQ61 33 V SS 34 V SS 83 NC 84 NC 133 V SS 134 DQ38 183 V SS 184 V SS 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 V DD 88 V DD 137 DQ35 138 V SS 187 V SS 188 DQS7 39 V SS 40 V SS 89 A12 90 A11 139 V SS 140 DQ44 189 DQ58 190 V SS 41 V SS 42 V SS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 V SS 193 V SS 194 DQ63 45 DQ17 46 DQ21 95 V DD 96 V DD 145 V SS 146 DQS5 195 SDA 196 V SS 47 V SS 48 V SS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 49 DQS2 50 NC 99 A3 100 A2 149 V SS 150 V SS 199 V DD SPD 200 SA1 Pin Description Pin Name Function Pin Name Function CK0,CK1 Clock s, positive line SDA SPD Data /Output CK0,CK1 Clock s, negative line SA1,SA0 SPD address CKE0,CKE1 Clock Enables DQ0~DQ63 Data /Output RAS Row Address Strobe DM0~DM7 Data Masks CAS Column Address Strobe DQS0~DQS7 Data strobes WE Write Enable DQS0~DQS7 Data strobes complement S0,S1 Chip Selects TEST Logic Analyzer specific test pin (No connect on So-DIMM) A0~A9, A11~A13 Address s V DD Core and I/O Power A10/AP Address /Autoprecharge V SS Ground BA0-BA2 SDRAM Bank Address V REF /Output Reference ODT0,ODT1 On-die termination control V DD SPD SPD Power SCL Serial Presence Detect(SPD) Clock NC Spare pins, No connect

/Output Functional Description Symbol Type Function CK0 CK1 CK0 CK1 CKE0 CKE1 S0 S1 RAS, CAS, WE The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivat ing the clocks, CKE low initiates the Power Down mode or the Self Refesh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0, Rank 1 is selected by S1. Ranks are also called Physical banks. When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0~BA2 Selects which DDR2 SDRAM internal bank is activated. ODT0~ODT1 A0~A9, A10/AP, A11~A13 Asserts on die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register Set (EMRS). During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0 BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0 BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA0 BAn inputs. If AP is low, then BA0 BAn are used to define which bank to precharge. DQ0~DQ63 In/Out Data /Output pins. DM0~DM7 DQS0~DQS7 DQS0~DQS7 In/Out The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. V DD,V DD SPD,V SS Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module. SDA SCL In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be con nected to V DD to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to V DD to act as a pull up. SA0~SA1 Address pins used to select the Serial Presence Detect base address. TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(so DIMMs).

Functional Block Diagram S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D4 DQS1 DQS1 DM1 DQS5 DQS5 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D1 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D5 DQS2 DQS2 DM2 DQS6 DQS6 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D6 DQS3 DQS3 DM3 DQS7 DQS7 DM7 DM NU/ CS DQS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D7 SCL WP BA0 - BA2 A0 - A12 RAS CAS CKE0 WE ODT0 V Serial PD DDSPD V DD /V DDQ SDA A0 A1 A2 VREF SA0 SA1 SA2 V SS BA0-BA2 : DDR2 SDRAMs D0 - D7 A0-A12 : DDR2 SDRAMs D0 - D7 RAS : DDR2 SDRAMs D0 - D7 CAS : DDR2 SDRAMs D0 - D7 CKE : DDR2 SDRAMs D0 - D7 WE : DDR2 SDRAMs D0 - D7 ODT : DDR2 SDRAMs D0 - D7 Serial PD D0 - D7 D0 - D7 D0 - D7 Clock *CK0/CK0 *CK1/CK1 *CK2/CK2 * Clock Wiring DDR2 SDRAMs 2 DDR2 SDRAMs 3 DDR2 SDRAMs 3 DDR2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms " 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms " 5%.

Physical Dimensions 67.60 mm 3.8 mm max 20 00 mm SPD 30 mm 1.1mm max 1.8 mm 2.7 mm 4.0 mm 0.60 mm 1.00 mm Left key position : Reserved Right key position : V DD = V DDQ = 1.8 V Tolerances:+-0.15mm unless otherwise specified

1Gb: x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H256M4 32 Meg x 4 x 8 banks MT47H128M8 16 Meg x 8 x 8 banks MT47H64M16 8 Meg x 16 x 8 banks Features V DD = +1.8V ±0.1V, V DDQ = +1.8V ±0.1V JEDEC-standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option 4n-bit prefetch architecture Duplicate output strobe (RDQS) option for x8 DLL to align DQ and DQS transitions with CK 8 internal banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency - 1 t CK Selectable burst lengths (BL): 4 or 8 Adjustable data-output drive strength 64ms, 8192-cycle refresh On-die termination (ODT) Industrial temperature (IT) option Automotive temperature (AT) option RoHS-compliant Supports JEDEC clock jitter specification Options 1 Marking Configuration 256 Meg x 4 (32 Meg x 4 x 8 banks) 256M4 128 Meg x 8 (16 Meg x 8 x 8 banks) 128M8 64 Meg x 16 (8 Meg x 16 x 8 banks) 64M16 FBGA package (Pb-free) x16 84-ball FBGA (8mm x 12.5mm) HR Rev. G, H FBGA package (Pb-free) x4, x8 60-ball FBGA (8mm x 11.5mm) HQ Rev. G FBGA package (Pb-free) x4, x8 60-ball FBGA (8mm x 10mm) Rev. H CF FBGA package (lead solder) x16 84-ball FBGA (8mm x 12.5mm) Rev. G, H FBGA package (lead solder) x4, x8 60-ball FBGA (8mm x 11.5mm) Rev. G HW HV FBGA package (lead solder) x4, x8 60-ball FBGA (8mm x 10mm) Rev. H JN Timing cycle time 1.875ns @ CL = 7 (DDR2-1066) -187E 2.5ns @ CL = 5 (DDR2-800) -25E 2.5ns @ CL = 6 (DDR2-800) -25 3.0ns @ CL = 4 (DDR2-667) -3E 3.0ns @ CL = 5 (DDR2-667) -3 3.75ns @ CL = 4 (DDR2-533) -37E Self refresh Standard None Low-power L Operating temperature Commercial (0 C T C 85 C) None Industrial ( 40 C T C 95 C; IT 40 C T A 85 C) Automotive ( 40 C T C, T A 105ºC) AT Revision :G/:H Note: 1. Not all options listed can be combined to define an offered product. Use the Part Catalog Search on www.micron.com for product offerings and availability. PDF: 09005aef821ae8bf 1GbDDR2.pdf Rev. V 6/10 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

1Gb: x4, x8, x16 DDR2 SDRAM Features Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade CL = 3 CL = 4 CL = 5 CL = 6 CL = 7 t RC (ns) -187E 400 533 667 800 1066 54-25E 400 533 800 800 n/a 55-25 400 533 667 800 n/a 55-3E 400 667 667 n/a n/a 54-3 400 533 667 n/a n/a 55-37E 400 533 n/a n/a n/a 55 Table 2: Addressing Parameter 256 Meg x 4 128 Meg x 8 64 Meg x 16 Configuration 32 Meg x 4 x 8 banks 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address A[13:0] (16K) A[13:0] (16K) A[12:0] (8K) Bank address BA[2:0] (8) BA[2:0] (8) BA[2:0] (8) Column address A[11, 9:0] (2K) A[9:0] (1K) A[9:0] (1K) Figure 1: 1Gb DDR2 Part Numbers Example Part Number: MT47H128M8CF-25 MT47H Configuration Package Speed Revision - { : :G/:H Revision Configuration 256 Meg x 4 128 Meg x 8 64 Meg x 16 256M4 128M8 64M16 L IT AT Low power Industrial temperature Automotive temperature Package Pb-free 84-ball 8mm x 12.5mm FBGA 60-ball 8mm x 11.5mm FBGA 60-ball 8mm x 10.0mm FBGA Lead solder 84-ball 8mm x 12.5mm FBGA HR HQ CF HW -187E -25E -25-3E -3-37E Speed Grade t CK = 1.875ns, CL = 7 t CK = 2.5ns, CL = 5 t CK = 2.5ns, CL = 6 t CK = 3ns, CL = 4 t CK = 3ns, CL = 5 t CK = 3.75ns, CL = 4 60-ball 8mm x 10mm FBGA JN 60-ball 8mm x 11.5mm FBGA HV Note: 1. Not all speeds and configurations are available in all packages. PDF: 09005aef821ae8bf 1GbDDR2.pdf Rev. V 6/10 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

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