DDR SDRAM UNBUFFERED DIMM

Transcription

1 DDR SDRAM UNBUFFERED DIMM 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM MT9VDDT672A 28MB MT9VDDT3272A 256MB MT9VDDT6472A 52MB For the latest data sheet, please refer to the Micron Web site: Features JEDEC-standard 84-pin dual in-line memory module (DIMM) Fast data transfer rate: PC32 CAS Latency 3 Utilizes 4 MT/s DDR SDRAM components Supports ECC error detection and correction 28MB (6 Meg x 72), 256MB (32 Meg x 72), 52MB (64 Meg x 72) VDD= VD= +2.6V VDDSPD = +2.3V to +3.6V +2.6V I/O (SSTL_2 compatible) Commands entered on each positive CK edge S edge-aligned with data for READs; centeraligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (S) transmitted/ received with data i.e., source-synchronous data capture Differential clock inputs (CK and CK#) Four internal device banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 5.6µs (28MB), 7.825µs (256MB, 52MB) maximum average periodic refresh interval Serial Presence-Detect (SPD) with EEPROM Programmable READ CAS latency Gold edge contacts Figure : 84-Pin DIMM (MO-26) Standard.25in. (3.75mm) OPTIONS MARKING Package 84-pin DIMM (standard) G 84-pin DIMM (lead-free) Y Frequency/CAS Latency 5ns, 4 MT/s (2 MHz), CL = 3-4B PCB.25in. (3.75mm) None Table : Address Table 28MB 256MB 52MB Refresh Count 4K 8K 8K Row Addressing 4K (A A) 8K (A A2) 8K (A A2) Device Bank Addressing 4 (BA, BA) 4 (BA, BA) 4 (BA, BA) Device Configuration 28Mb (6 Meg x 8) 256Mb (32 Meg x 8) 52Mb (64 Meg x 8) Column Addressing K (A A9) K (A A9) 2K (A A9, A) Module Rank Addressing (S#) (S#) (S#) pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 24 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

2 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 2: Part Numbers and Timing Parameters PART NUMBER MODULE DENSITY CONFIGURATION MODULE BANDWIDTH MEMORY CLOCK/ DATA RATE LATENCY (CL - t RCD - t RP) MT9VDDT672AG-4B 28MB 6 Meg x GB/s 5ns/4 MT/s MT9VDDT672AY-4B 28MB 6 Meg x GB/s 5ns/4 MT/s MT9VDDT3272AG-4B 256MB 32 Meg x GB/s 5ns/4 MT/s MT9VDDT3272AY-4B 256MB 32 Meg x GB/s 5ns/4 MT/s MT9VDDT6472AG-4B 52MB 64 Meg x GB/s 5ns/4 MT/s MT9VDDT6472AY-4B 52MB 64 Meg x GB/s 5ns/4 MT/s NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272AG-4BA. pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 2 24 Micron Technology, Inc.

3 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 3: Pin Assignment (84-Pin DIMM Front) Table 4: Pin Assignment (84-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL VREF S8 7 VDD 2 25 S2 48 A 7 NC 3 VSS 26 VSS 49 CB A9 5 VSS S CB3 74 VSS A7 52 BA 75 CK2# 7 VDD 3 VD CK VD 77 VD 9 NC 32 A S6 NC S VSS 34 VSS VSS 8 VSS S3 59 BA 82 NC 4 S 37 A VD 38 VDD CK VD 85 VDD 7 CK# WE# 86 S7 8 VSS 4 A VSS 65 CAS# A 66 VSS 89 VSS 2 CKE 44 CB 67 S5 9 NC 22 VD 45 CB SDA VDD SCL NOTE: Pin 5 is No Connect (28MB), and A2 (256MB, 52MB). FRONT VIEW Figure 2: 84-Pin DIMM Pinouts PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 93 VSS 6 VSS 39 VSS DM8 63 NC A 4 A 64 VD 96 VD 9 DM2 42 CB DM 2 VDD 43 VD CB7 67 NC A8 45 VSS 68 VDD VSS DM6 NC 24 VSS NC 25 A6 48 VDD NC DM4 72 VD 4 VD NC VD DM3 52 VSS DM 3 A VSS 8 VDD RAS# 77 DM VSS VD NC 34 CB4 57 S# 8 VD 2 VD 35 CB5 58 NC 8 SA 3 NC 36 VD 59 DM5 82 SA CK 6 VSS 83 SA2 5 NC/A2 38 CK# VDDSPD U U U2 U3 U4 U5 U6 U7 U8 U9 PIN PIN 52 PIN 53 PIN 92 BACK VIEW Indicates a VDD pin Indicates a VSS pin No Components This Side PIN 84 PIN 45 PIN 44 PIN 93 pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 3 24 Micron Technology, Inc.

4 Table 5: Pin Descriptions 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Pin numbers may not correlate with symbols; ; Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 63, 65, 54 WE#, CAS#, RAS# Input Command Inputs: WE#, RAS#, and CAS# (along with S#) define the command being entered. 6, 7, 75, 76, 37, 38 CK, CK#, CK, CK#, CK2, CK2# Input Clocks: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (s and S) is referenced to the crossings of CK and CK#. 2 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) internal clock signals, device input buffers, and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE has been brought HIGH, it is an SSTL_2 input only. 57 S# Input Chip Select: S# enables (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 52, 59 BA, BA Input Bank Addresses: BA and BA define to which device bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. 27, 29, 32, 37, 4, 43, 48, 5 (256MB, 52MB), 8, 22, 25, 3, 4 44, 45, 49, 5, 34, 35, 42, 44 97, 7, 9, 29, 49, 59, 69, 77 A A (28MB) A A2 (256MB, 52MB) Input CB CB7 Input/Output Data I/Os: Check bits. Address Inputs: Sampled during the ACTIVE command (row-address) and READ/WRITE command (columnaddress, with A defining auto precharge) to select one location out of the memory array in the respective device device bank. A is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one device bank (A LOW) or all device banks (A HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. DM DM7 Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM lines do not affect READ operation. 5, 4, 25, 36, 56, 67, 78, 86 S-S7 Input/Output Data Strobe: Output with READ data, input with WRITE data. S is edge-aligned with READ data, centered in WRITE data. Used to capture data. pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 4 24 Micron Technology, Inc.

5 Table 5: Pin Descriptions (Continued) 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Pin numbers may not correlate with symbols; ; Refer to Pin Assignment Tables on page 3 for more information 2, 4, 6, 8, 2, 3, 9, 2, 23, 63 Input/Output Data I/Os: Data bus. 24, 28, 3, 33, 35, 39, 4, 53, 55, 57, 6, 6, 64, 68, 69, 72, 73, 79, 8, 83, 84, 87, 88, 94, 95, 98, 99, 5, 6, 9,, 7, 2, 3, 33, 46, 47, 5, 5, 53, 55, 6, 62, 65, 66, 7, 7, 74, 75, 78, SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 8, 82, 83 SA SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 9 SDA Input/Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. VREF Supply SSTL_2 reference voltage. 7, 5, 22, 3, 38, 54, 62, 7, VDD, VD Supply Power Supply: +2.6V ±.V. 77, 85, 96, 4, 8, 2, 2, 28, 36, 43, 48,56, 64, 68, 72, 8 3,, 8, 26, 34, 42, 5, 58, VSS Supply Ground. 66, 74, 8, 89, 93,, 6, 24, 32, 39, 45, 52, 6, VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V. This supply is isolated from the VDD/VD supply. 9,, 7, 82, 9,, 2, NC No Connects. 3, 3, 5 (28MB), 63, 67, 73, 58 DNU Do Not Use: These pins are not connected on this module but are assigned pins on other modules in this product family. pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 5 24 Micron Technology, Inc.

6 NOTE: BA, BA A-A (28MB) A-A2 (256MB, 52MB) RAS# CAS# WE# CKE 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Figure 3: Functional Block Diagram S# S DM S DM S2 DM2 S3 DM3 S8 DM CB CB CB2 CB3 CB4 CB5 CB6 CB7 DM CS# S U DM CS# S U2 DM CS# S U3 S7 DM7 DM CS# S DM CS# S U4 59 U DM CS# S U9. All resistor values are 22Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at BA, BA: DDR SDRAMs A-A: DDR SDRAMs A-A2: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs WE#: DDR SDRAMs CKE: DDR SDRAMs CK CK# 2 4.5pF S4 DM4 S5 DM5 S6 DM6 VD VDD VREF VSS SCL WP SDRAM X 3 CK2 CK2# VDDSPD 2 4.5pF CK CK# DM CS# S U5 DM CS# S U6 DM CS# S U7 2 SDRAM X 3 4.5pF SERIAL PD U A A A2 SA SA SA2 SDRAM X 3 SPD/EEPROM SDRAMs SDRAMs SDRAMs SDRAMs SDA Standard modules use the following DDR SDRAM devices: MT46V6M8TG (28MB); MT46V32M8TG (256MB); MT6V64M8TG (52MB) Lead-free modules use the following DDR SDRAM devices: MT46V6M8TG (28MB); MT46V32M8TG (256MB); MT6V64M8TG (52MB) pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 6 24 Micron Technology, Inc.

7 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM General Description The MT9VDDT672A, MT9VDDT3272A, and MT9VDDT6472A are high-speed CMOS, dynamic random-access, 28MB, 256MB, and 52MB memory modules organized in a x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. Double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (S) is transmitted externally, along with data, for use in data capture at the receiver. S is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. S is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of S, and output data is referenced to both edges of S, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA, BA select device bank; A A (28MB) or A A2 (256MB, 52MB) select device row. The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 28Mb, 256Mb, or 52Mb DDR SDRAM component data sheet. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using a 2,48-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 28 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 28 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I 2 C bus using the DIMM s SCL (clock) and SDA (data) signals, together with SA (2:), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of DDR SDRAM devices. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4, Mode Register Definition Diagram, on page 8. The mode register is programmed via the MODE REGISTER SET command (with BA = and BA = ) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4 A6 specify the CAS latency, and A7 A (28MB) or A7 A2 (256MB, 52MB) specify the operating mode. pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 7 24 Micron Technology, Inc.

8 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A Ai when the burst length is set to two, by A2 Ai when the burst length is set to four and by A3 Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration; see note 5 of Table 6, Burst Definition Table, on page 9). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 9. Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 3, 2.5, or 2 clocks, as shown in Figure 5, CAS Latency Diagram, on page 9. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency (CL) Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 A (28MB), or A7 A2 (256MB, 52MB) each set to zero, and bits A A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9 A (28MB), or A7 and A9 A2 (256MB, 52MB) each set to zero, bit A8 set to one, and bits A A6 set to the desired values. Figure 4: Mode Register Definition Diagram 28MB Module BA BA A A 3 2 * * * M3 and M2 (BA and BA) must be, to select the base mode register (vs. the extended mode register). 256MB, 52MB Modules BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A * * Operating Mode CAS Latency BT Burst Length * M4 and M3 (BA and BA) must be, to select the base mode register (vs. the extended mode register). A9 A8 A7 A6 A5 A4 A3 A2 A A Operating Mode CAS Latency BT Burst Length M6 M5 M4 M3 M2 M M M9 M8 M7 M6-M Valid Valid - M2 M M CAS Latency Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved Address Bus Mode Register (Mx) Address Bus Mode Register (Mx) Burst Length M3 = M3 = Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 8 24 Micron Technology, Inc.

9 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 6: Burst Definition Table Figure 5: CAS Latency Diagram BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED A A A A2 A A NOTE:. For a burst length of two, A Ai select the two-dataelement block; A selects the first access within the block. 2. or a burst length of four, A2 Ai select the four-data-element block; A A select the first access within the block. 3. For a burst length of eight, A3 Ai select the eight-dataelement block; A A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (28MB, 256MB) i = 9, (52MB) Table 7: CAS Latency (CL) Table ALLOWABLE OPERATING FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 CL = 3-4B 75 f f f 2 CK# CK COMMAND S CK# CK COMMAND S CK# CK COMMAND S T T T2 T2n T3 T3n READ NOP NOP NOP T T T2 T2n T3 T3n READ NOP NOP NOP CL = 2.5 T T T2 T2n T3 T3n READ NOP NOP NOP CL = 2 CL = 3 Burst Length = 4 in the cases shown Shown with nominal t AC, t SCK, and t SQ TRANSITIONING DATA DON T CARE Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REG- ISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7 A (28MB), or A7 A2 (256MB, 52MB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition Diagram, on page. The extended mode register is programmed via the LOAD MODE REGIS- TER command to the mode register (with BA = and pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 9 24 Micron Technology, Inc.

10 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM BA = ) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA/BA both low) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 2 clock cycles must occur before a READ command can be issued. Figure 6: Extended Mode Register Definition Diagram 28MB Module BA BA A A MB, 52MB Modules BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Operating Mode DS DLL Operating Mode DS DLL E E Address Bus Extended Mode Register (Ex) Address Bus Extended Mode Register (Ex) DLL Enable Disable Drive Strength Normal E2 E E E9 E8 E7 E6 E5 E4 E3 E2 2 E, E Valid Operating Mode Reserved Reserved NOTE:. BA and BA (E3 and E2 for 28MB or E4 and E3 for 256MB, 52MB) must be, to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported. pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 24 Micron Technology, Inc.

11 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description of commands and operations, refer to the 28Mb, 256Mb, or 52Mb DDR SDRAM component data sheets. Table 8: Commands Truth Table DESELECT and NOP are functionally interchangeable; all states and sequences not shown are illegal or reserved NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES DESELECT (NOP) H X X X X NO OPERATION (NOP) L H H H X ACTIVE (Select bank and activate row) L L H H Bank/Row 2 READ (Select bank and column, and start READ burst) L H L H Bank/Col 3 WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3 BURST TERMINATE L H H L X 4 PRECHARGE (Deactivate row in bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X 6, 7 LOAD MODE REGISTER L L L L Op-Code 8 NOTE:. DESELECT and NOP are functionally interchangeable. 2. BA BA provide device bank address and A A (28MB) or A A2 (256MB, 52MB) provide device row address. 3. BA BA provide device bank address; A A9 (28MB, 256MB) or A A9, A (52MB) provide device column address; A HIGH enables the auto precharge feature (nonpersistent), and A LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 5. A LOW: BA BA determine which device bank is precharged. A HIGH: all device banks are precharged and BA BA are Don t Care. 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls device row addressing; all inputs and I/Os are Don t Care except for CKE. 8. BA-BA select either the mode register or the extended mode register (BA =, BA = select the mode register; BA =, BA = select extended mode register; other combinations of BA BA are reserved). A A (28MB) or A A2 (256MB, 52MB) provide the op-code to be written to the selected mode register. Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) DM S WRITE Enable L Valid WRITE Inhibit H X pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 24 Micron Technology, Inc.

12 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Voltage on VDD Supply Relative to VSS V to +3.6V Voltage on VD Supply Relative to VsSS V to +3.6V Voltage on VREF and Inputs Relative to VSS V to +3.6V Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on I/O Pins Relative to VSS V to VD +.5V Operating Temperature, T A (ambient) C to +7 C Storage Temperature (plastic) C to +5 C Short Circuit Output Current mA Table : DC Electrical Characteristics and Operating Conditions Notes: 5, 4; notes appear on pages 8 2; C T A +7 C; VDD = VD = +2.6V ±.V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage VD V 32, 36 I/O Supply Voltage VD V 32, 36, 39 I/O Reference Voltage VREF.49 x VD.5 x VD V 6, 39 I/O Termination Voltage (system) VTT VREF -.4 VREF +.4 V 7, 39 Input High (Logic ) Voltage VIH(DC) VREF +.5 VDD +.3 V 25 Input Low (Logic ) Voltage VIL(AC) -.3 VREF -.5 V 25 INPUT LEAKAGE CURRENT: Any input V VIN VDD, VREF pin V VIN.35V (All other pins not under test = V) Command/Address, RAS#, CAS#, WE#, -8 8 µa CKE, S# IL CK, CK# -6 6 µa DM -2 2 µa OUTPUT LEAKAGE CURRENT:, S IOZ -5 5 µa 47 (s are disabled; V VOUT VD) OUTPUT LEVELS: IOH -6.8 ma 33, 36 High Current (VOUT = VD -.373V, minimum VREF, minimum VTT) Low Current (VOUT =.373V, maximum VREF, maximum VTT) IOL 6.8 ma 47 Table : AC Input Operating Conditions Notes: 5, 4; notes appear on pages 8 2; C T A +7 C; VDD = VD = +2.6V ±.V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Input High (Logic ) Voltage VIH(AC) VREF +.3 V 2, 25, 35 Input Low (Logic ) Voltage VIL(AC) VREF -.3 V 2, 25, 35 I/O Reference Voltage VREF(AC).49 x VD.5 x VD V 6 pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 2 24 Micron Technology, Inc.

13 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 2: IDD Specifications and Conditions 28MB DRAM components only Notes: 5, 8,, 2, 48; notes appear on pages 8 2; C T A +7 C; VDD = VD = +2.6V ±.V PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; t RC = t RC (MIN); t CK = t CK (MIN);, DM, and S inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 2; t RC = t RC (MIN); t CK = t CK (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = t CK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for, S, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle SYMBOL MAX -4B UNITS NOTES IDD,35 ma 2, 42 IDD,25 ma 2, 42 IDD2P 27 ma 2, 28, 44 IDD2F 45 ma 45 IDD3P 225 ma 2, 28, 44 IDD3N 45 ma 2, 4 IDD4R,25 ma 2, 42 IDD4W,395 ma 2 AUTO REFRESH CURRENT t REFC = t RFC (MIN) IDD5 2,6 ma 2, 44 t REFC = 5.625µs IDD5A 54 ma 24, 44 SELF REFRESH CURRENT: CKE.2V Standard IDD6 36 ma 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, t RC = t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active, READ, or WRITE commands. IDD7 3,95 ma 2, 43 pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 3 24 Micron Technology, Inc.

14 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 3: IDD Specifications and Conditions 256MB DRAM components only Notes: 5, 8,, 2; notes appear on pages 8 2; C T A +7 C; VDD = VD = +2.6V ±.V PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; t RC = t RC (MIN); t CK = t CK (MIN);, DM, and S inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t RC = t RC (MIN); t CK = t CK (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = t CK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for, S, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle SYMBOL MAX -4B UNITS NOTES IDD,25 ma 2, 42 IDD,53 ma 2, 42 IDD2P 36 ma 2, 28, 44 IDD2F 54 ma 45 IDD3P 36 ma 2, 28, 44 IDD3N 63 ma 2, 4 IDD4R,8 ma 2, 42 IDD4W,755 ma 2 AUTO REFRESH CURRENT t REFC = t RFC (MIN) IDD5 2,34 ma 2, 44 t REFC = 7.825µs IDD5A 54 ma 24, 44 SELF REFRESH CURRENT: CKE.2V Standard IDD6 36 ma 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, t RC = t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active, READ, or WRITE commands. IDD7 3,645 ma 2, 43 pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 4 24 Micron Technology, Inc.

15 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 4: IDD Specifications and Conditions 52MB DRAM components only Notes: 5, 8,, 2; notes appear on pages 8 2; C T A +7 C; VDD = VD = +2.6V ±.V PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; t RC = t RC (MIN); t CK = t CK (MIN);, DM, and S inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t RC = t RC (MIN); t CK = t CK (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = t CK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for, S, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle SYMBOL MAX -4B UNITS NOTES IDD,395 ma 2, 42 IDD,665 ma 2, 42 IDD2P 45 ma 2, 28, 44 IDD2F 495 ma 45 IDD3P 45 ma 2, 28, 44 IDD3N 54 ma 2, 4 IDD4R,7 ma 2, 42 IDD4W,755 ma 2 AUTO REFRESH CURRENT t REFC = t RFC (MIN) IDD5 3,5 ma 2, 44 t REFC = 7.825µs IDD5A 99 ma 24, 44 SELF REFRESH CURRENT: CKE.2V Standard IDD6 45 ma 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, t RC = t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active, READ, or WRITE commands. IDD7 4,5 ma 2, 43 pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 5 24 Micron Technology, Inc.

16 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 5: Capacitance Note: ; notes appear on pages 8 2 PARAMETER SYMBOL MIN MAX UNITS Input/Output Capacitance: s, Ss CIO pf Input Capacitance: Command and Address, S# CI pf Input Capacitance: CK, CK# CI pf Input Capacitance: CKE CI pf Table 6: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 8, 2 5, 29, 3; notes appear on page 8 2; C T A +7 C; VDD = VD = +2.6V ±.V AC CHARACTERISTICS -4B PARAMETER SYMBOL MIN MAX UNITS NOTES Access window of s from CK/CK# t AC ns CK high-level width t CH t CK 26 CK low-level width t CL t CK 26 Clock cycle time CL = 3 t CK (3) ns 4, 46 CL = 2.5 t CK (2.5) 6 3 ns 4, 46 CL = 2 t CK (2) ns 4, 46 and DM input hold time relative to S t DH.4 ns 23, 27 and DM input setup time relative to S t DS.4 ns 23, 27 and DM input pulse width (for each input) t DIPW.75 ns 27 Access window of S from CK/CK# t SCK ns S input high pulse width t SH.35 t CK S input low pulse width t SL.35 t CK S- skew, S to last valid, per group, per access t SQ.4 ns 22, 23 Write command to first S latching transition t SS t CK S falling edge to CK rising - setup time t DSS.2 t CK S falling edge from CK rising - hold time t DSH.2 t CK Half clock period t HP t CH, t CL ns 3 Data-out high-impedance window from CK/CK# t HZ +.7 ns 6, 38 Data-out low-impedance window from CK/CK# t LZ -.7 ns 6, 39 Address and control input hold time ( V/ns) t IH F.6 ns 2 Address and control input setup time ( V/ns) t IS F.6 ns 2 Address and control input hold time (.5 V/ns) t IH S.6 ns 2 Address and control input setup time (.5 V/ns) t IS S.6 ns 2 Address and Control input pulse width (for each input) t IPW 2.2 ns LOAD MODE REGISTER command cycle time t MRD 2 ns -S hold, S to first to go non-valid, per access t QH t HP - t QHS ns 22, 23 Data hold skew factor t QHS.5 ns ACTIVE to PRECHARGE command t RAS 4 7, ns 3 ACTIVE to READ with Auto precharge command t RAP 5 ns ACTIVE to ACTIVE/AUTO REFRESH command period t RC 55 ns AUTO REFRESH command period t RFC 7 ns 46 pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 6 24 Micron Technology, Inc.

17 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 6: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 5, 8, 2 5, 29, 3; notes appear on page 8 2; C T A +7 C; VDD = VD = +2.6V ±.V AC CHARACTERISTICS -4B PARAMETER SYMBOL MIN MAX UNITS NOTES ACTIVE to READ or WRITE delay t RCD 5 ns PRECHARGE command period t RP 5 ns S read preamble t RPRE.9. t CK 38 S read postamble t RPST.4.6 t CK ACTIVE bank a to ACTIVE bank b command t RRD ns S write preamble t WPRE.25 t CK S write preamble setup time t WPRES ns 8, 9 S write postamble t WPST.4.6 t CK 7 Write recovery time t WR 5 ns Internal WRITE to READ command delay t WTR 2 t CK Data valid output window na t QH - t SQ ns 22 REFRESH to REFRESH command interval 28MB t 4.6 µs REFC 256MB, 52MB 7.3 µs 2 Average periodic refresh interval 28MB t 5.6 µs REFI 256MB, 52MB 7.8 µs 2 Terminating voltage delay to VDD t VTD ns Exit SELF REFRESH to non-read command t XSNR 75 ns Exit SELF REFRESH to READ command t XSRD 2 t CK pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 7 24 Micron Technology, Inc.

18 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Notes. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: Output (VOUT) VTT 5Ω Reference Point 3pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to.5v in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VD/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VD/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 3 for -4B with the outputs open. 9. Enables on-chip refresh and address counters.. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate.. This parameter is sampled. VDD = +2.6V ±.V, VD = +2.6V ±.V, VREF = VSS, f = 2 MHz, T A = 25 C, VOUT (DC) = VD/2, VOUT (peak to peak) =.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 2. Slew rates less than.5v/ns are not allowed. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 3. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 4. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE.3 x VD is recognized as LOW. 5. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 6. t HZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 7. The intent of the Don t Care state after completion of the postamble is the S-driven signal should either be high, low, or high-z and that any signal transition within the input switching region must follow valid input requirements. That is, if S transitions high [above VIH DC (MIN)] then it must not transition low (below VIHDC) prior to t SH (MIN). 8. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 9. It is recommended that S be valid (HIGH or LOW) on or before the WRITE command. The case shown (S going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, S could be HIGH during this time, depending on t SS. 2. MIN ( t RC or t RFC) for IDD measurements is the smallest multiple of t CK that meets the minimum absolute value for the respective parameter. tras (MAX) for IDD measurements is the largest multiple of t CK that meets the maximum absolute value for t RAS. 2. The refresh period 64ms. This equates to an average refresh rate of 5.625µs (28MB) 7.825µs (256MB, 52MB). However, an AUTO REFRESH command must be asserted at least once every 4.6µs (28MB) or 7.3µs (256MB, 52MB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: t HP ( t CK/2), t SQ, and t QH pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 8 24 Micron Technology, Inc.

19 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM ( t QH = t HP - t QHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. 23. Each byte lane has a corresponding S. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period ( t RFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b)reach at least the target AC level. c)after the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. CK and CK# input slew rate must be V/ns ( 2V/ns if measured differentially). 27. and DM input slew rates must not deviate from S by more than percent. /DM/S slew rates less than.5 V/ns are not allowed. If slew rate exceeds 4 V/ns, functionality is uncertain. 28. VDD must not vary more than 4 percent if CKE is not active while any device bank is active. 29. The clock is allowed up to ±5ps of jitter. Each timing parameter is allowed to vary by the same amount. 3. t HP (MIN) is the lesser of t CL minimum and t CH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 3. READs and WRITEs with auto precharge are not allowed to be issued until t RAS (MIN) can be satisfied prior to the internal precharge command being issued. Figure 7: Pull-Down Characteristics 32. Any positive glitch must be less than /3 of the clock cycle and not more than +4mV or 2.9V, whichever is less. Any negative glitch must be less than /3 of the clock cycle and not exceed either - 3mV or 2.4V, whichever is more positive. The DC average cannot go below 2.5V minimum. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 7, Pull-Down Characteristics. b)the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 7, Pull-Down Characteristics. c)the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Up Characteristics. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Up Characteristics. e)the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between.7 and.4, for device drain-to-source voltages from.v to.v, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ± percent, for device drain-to-source voltages from.v to.v. Figure 8: Pull-Up Characteristics 6 IOUT (ma) Maximum Nominal high Nominal low IOUT (ma) Maximum Nominal high Nominal low 4 Minimum -4-6 Minimum VOUT (V) VD - VOUT (V) pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 9 24 Micron Technology, Inc.

20 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM 34. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 35. VIH overshoot: VIH (MAX) = VD+.5V for a pulse width 3ns and the pulse width can not be greater than /3 of the cycle rate. VIL undershoot: VIL (MIN) = -.5V for a pulse width 3ns and the pulse width can not be greater than /3 of the cycle rate. 36. VDD and VD must track each other. 37. t HZ (MAX) will prevail over t SCK (MAX) + t RPST (MAX) condition. t LZ (MIN) will prevail over t SCK (MIN) + t RPRE (MAX) condition. 38. t RPST end point and t RPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving ( t RPST), or begins driving ( t RPRE). 39. During initialzation, VD, VTT, and VREF must be equal to or less than VDD +.3V. Alternatively, VTT may be.35v maximum during power up, even if VDD/VD are.v, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 4. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 4. For -4B modules, IDD3N is specified to be 35mA per DDR SDRAM device at MHz. 42. Random addressing changing and 5 percent of data changing at every transfer. 43. Random addressing changing and percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 45. IDD2N specifies the, S and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is worst case. 46. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 2 clock cycles. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 2 24 Micron Technology, Inc.

21 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Initialization To ensure device operation the DRAM must be initialized as described below:. Simultaneously apply power to VDD and VD. 2. Apply VREF and then VTT power. 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at least 2µs. 6. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. 7. Perform a PRECHARGE ALL command. 8. Wait at least t RP time, during this time NOPs or DESELECT commands must be given. 9. Using the LMR command program the Extended Mode Register (E = to enable the DLL and E = for normal drive or E = for reduced drive, E2 through En must be set to ; where n = most significant bit).. Wait at least t MRD time, only NOPs or DESELECT commands are allowed.. Using the LMR command program the Mode Register to set operating parameters and to reset the DLL. Note at least 2 clock cycles are required between a DLL reset and any READ command. 2. Wait at least t MRD time, only NOPs or DESELECT commands are allowed. 3. Issue a PRECHARGE ALL command. 4. Wait at least t RP time, only NOPs or DESELECT commands are allowed. 5. Issue an AUTO REFRESH command (Note this may be moved prior to step 3). 6. Wait at least t RFC time, only NOPs or DESELECT commands are allowed. 7. Issue an AUTO REFRESH command (Note this may be moved prior to step 3). 8. Wait at least t RFC time, only NOPs or DESELECT commands are allowed. 9. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = ). If a LMR command is issued the same operating parameters should be utilized as in step. 2. Wait at least t MRD time, only NOPs or DESELECT commands are allowed. 2. At this point the DRAM is ready for any valid command. Note 2 clock cycles are required between step (DLL Reset) and any READ command. Figure 9: Initialization Flow Diagram Step VDD and VD Ramp 2 Apply VREF and VTT 3 CKE must be LVCMOS Low 4 Apply stable CLOCKs 5 Wait at least 2us 6 Bring CKE High with a NOP command 7 PRECHARGE ALL 8 Assert NOP or DESELECT for t RP time 9 Configure Extended Mode Register Assert NOP or DESELECT for t MRD time Configure Load Mode Register and reset DLL 2 Assert NOP or DESELECT for t MRD time 3 PRECHARGE ALL 4 Assert NOP or DESELECT for t RP time 5 Issue AUTO REFRESH command 6 Assert NOP or DESELECT commands for t RFC 7 Issue AUTO REFRESH command 8 Assert NOP or DESELECT for t RFC time 9 Optional LMR command to clear DLL bit 2 Assert NOP or DESELECT for t MRD time 2 DRAM is ready for any valid command pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN 2 24 Micron Technology, Inc.

22 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure, Data Validity, and Figure, Definition of Start and Stop). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure : Data Validity SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure, Definition of Start and Stop). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. Figure : Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 2: Acknowledge Response from Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN Micron Technology, Inc.

23 Table 7: EEPROM Device Select Code Most significant bit (b7) is sent first 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b b Memory Area Select Code (two arrays) SA2 SA SA RW Protection Register Select Code SA2 SA SA RW Table 8: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE Current Address Read VIH or VIL START, Device Select, RW = Random Address Read VIH or VIL START, Device Select, RW =, Address VIH or VIL restart, Device Select, RW = Sequential Read VIH or VIL Similar to Current or Random Address Read Byte Write VIL START, Device Select, RW = Page Write VIL 6 START, Device Select, RW = Figure 3: SPD EEPROM Timing Diagram t F t HIGH t R SCL t LOW t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO SDA IN t AA t DH t BUF SDA OUT UNDEFINED pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN Micron Technology, Inc.

24 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Table 9: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDD V INPUT HIGH VOLTAGE: Logic ; All inputs VIH VDD x.7 VDD +.5 V INPUT LOW VOLTAGE: Logic ; All inputs VIL - VDD x.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA VOL.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI µa OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO µa STANDBY CURRENT: SCL = SDA = VDD -.3V; All other inputs = VDD OR VSS ISB 3 µa POWER SUPPLY CURRENT: SCL clock frequency = KHz ICC 2 ma Table 2: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid t AA.2.9 µs Time the bus must be free before a new transition can start t BUF.3 µs Data-out hold time t DH 2 ns SDA and SCL fall time t F 3 ns 2 Data-in hold time t HD:DAT µs Start condition hold time t HD:STA.6 µs Clock HIGH period t HIGH.6 µs Noise suppression time constant at SCL, SDA inputs t I 5 ns Clock LOW period t LOW.3 µs SDA and SCL rise time t R.3 µs 2 SCL clock frequency f SCL 4 KHz Data-in setup time t SU:DAT ns Start condition setup time t SU:STA.6 µs 3 Stop condition setup time t SU:STO.6 µs WRITE cycle time t WRC ms 4 NOTE:. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time ( t WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN Micron Technology, Inc.

25 Table 2: Serial Presence-Detect Matrix / : Serial Data, driven to HIGH / driven to LOW 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM BYTE DESCRIPTION ENTRY (VERSION) MT9VDDT672A MT9VDDT3272A MT9VDDT6472A Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type SDRAM DDR Number of Row Addresses on Assembly 2 or 3 C D D 4 Number of Column Addresses on or A A B Assembly 5 Number of Physical Ranks on DIMM 6 Module Data Width Module Data Width (Continued) 8 Module Voltage Interface Levels SSTL 2.5V SDRAM Cycle Time, t CK (CAS Latency = 5ns (-4B) ) SDRAM Access from Clock, t AC (CAS.7ns (-4B) Latency = 3) Module Configuration Type ECC Refresh Rate/Type 5.62µs, 7.8µs/SELF SDRAM Device Width (Primary DDR SDRAM) 4 Error-checking DDR SDRAM Data Width 5 Minimum Clock Delay, Back-to-Back clock Random Column Access 6 Burst Lengths Supported 2, 4, 8 E E E 7 Number of Banks on DDR SDRAM Device 8 CAS Latencies Supported 3, 2.5, 2 C C C 9 CS Latency 2 WE Latency SDRAM Module Attributes Unbuffered/Diff Clock 22 SDRAM Device Attributes: General Fast/Concurrent AP C C C 23 SDRAM Cycle Time, t CK (CAS Latency = 2.5) 24 SDRAM Access from CK, t AC (CAS Latency = 2.5) 25 SDRAM Cycle Time, t CK (CAS Latency = 2) 26 SDRAM Access from CK, t AC (CAS Latency = 2) 6ns (for PC27 system compatibility).7ns (for PC 27 system compatibility) 7.5ns (for PC 2 and PC 6 system compatibility).75ns (for PC 2 and PC 6 system compatibility) Minimum Row Precharge Time, t RP 5ns (-4B) 3C 3C 3C 28 Minimum Row Active to Row Active, ns (-4B) t RRD 29 Minimum RAS# to CAS# Delay, t RCD 5ns (-4B) 3C 3C 3C pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN Micron Technology, Inc.

26 Table 2: Serial Presence-Detect Matrix (Continued) / : Serial Data, driven to HIGH / driven to LOW 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM BYTE DESCRIPTION ENTRY (VERSION) MT9VDDT672A MT9VDDT3272A MT9VDDT6472A 3 Minimum RAS# Pulse Width, t RAS 4ns (-4B) Module Rank Density 28MB, 256MB, MB 32 Address And Command Setup Time, t IS.6ns (-4B) Address And Command Hold Time, t IH.6ns (-4B) Data/ Data Mask Input Setup Time, t DS.4ns (-4B) Data/ Data Mask Input Hold Time, t DH.4ns (-4B) Reserved 4 Min Active Auto Refresh Time, t RC 55ns (-4B) Minimum Auto Refresh to Active/ Auto 7ns (-4B) Refresh Command Period, t RFC 43 SDRAM Device Max Cycle Time, t CKMAX 2ns (-4B) SDRAM Device Max S- Skew.4ns (-4B) Time, t SQ 45 SDRAM Device Max Read Data Hold.5ns (-4B) Skew Factor, t QHS 46 Reserved 47 DIMM Height 48 6 Reserved 62 SPD Revision Release. 63 Checksum for Bytes -62-4B 6F 92 D3 64 Manufacturer s JEDEC ID Code MICRON 2C 2C 2C 65-7 Manufacturer s JEDEC ID Code (Continued) FF FF FF 72 Manufacturing Location 2 C C C 73-9 Module Part Number (ASCII) Variable Data Variable Data Variable Data 9 PCB Identification Code Identification Code (Continued) 93 Year of Manufacture in BCD Variable Data Variable Data Variable Data 94 Week of Manufacture in BCD Variable Data Variable Data Variable Data Module Serial Number Variable Data Variable Data Variable Data Manufacturer-Specific Data (RSVD) pdf: 95aef8a43e7d, source: 95aef8a43d77 DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN Micron Technology, Inc.

27 28MB, 256MB, 52MB (x72, ECC, SR), PC32 84-Pin DDR SDRAM UDIMM Figure 4: 84-Pin DIMM Dimensions FRONT VIEW (33.5) (33.2).25 (3.8) MAX.79 (2.) R (4X) U U2 U3 U4 U5 U6 U7 U8 U9 U.255 (3.88).245 (3.62).98 (2.5) D (2X).7 (7.78) TYP..9 (2.3) TYP..9 (2.3) TYP. PIN.5 (.27) TYP..4 (.2) TYP..25 (6.35) TYP..35 (.9) R PIN (.37).46 (.7) 4.75 (2.65) BACK VIEW NO COMPONENTS THIS SIDE NOTE: PIN 84.5 (3.8) PIN 93.5 (3.8) TYP..95 (49.53) All dimensions in inches (millimeters); MAX MIN or typical where noted (64.77).394 (.) TYP. Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 8 S. Federal Way, P.O. Box 6, Boise, ID , Tel: [email protected], Internet: Customer Comment Line: Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. pdf: 95aef8a43e7d, source: 95aef8a43d77. DDA9C6_32_64x72AG.fm - Rev. B 9/4 EN Micron Technology, Inc