DDR3 SDRAM UDIMM MT16JTF25664AZ 2GB MT16JTF51264AZ 4GB MT16JTF1G64AZ 8GB. Features. 2GB, 4GB, 8GB (x64, DR) 240-Pin DDR3 UDIMM.

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1 DDR3 SDRAM UDIMM MT6JTF5664AZ GB MT6JTF564AZ 4GB MT6JTFG64AZ 8GB GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Features Features DDR3 functionality and operations supported as per component data sheet 40-pin, unbuffered dual in-line memory module (UDIMM) Fast data transfer rates: PC3-4900, PC3-800, PC3-0600, PC3-8500, or PC GB (56 Meg x 64), 4GB (5 Meg x 64), 8GB ( Gig x 64) V DD = V D =.5V ±0.75V V DDSPD = V Reset pin for improved system stability Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Dual rank 8 internal device banks for concurrent operation Fixed burst length (BL) of 8 and burst chop (BC) of 4 via the mode register Adjustable data-output drive strength Serial presence-detect (SPD) EEPROM Gold edge contacts Halogen-free Addresses are mirrored for second rank Fly-by topology Terminated control, command, and address bus Figure : 40-Pin UDIMM (MO-69 R/C B) Module height: 30.0mm (.8in) Options Marking Operating temperature Commercial (0 C T A +70 C) None Industrial ( 40 C T A +85 C) I Package 40-pin DIMM (halogen-free) Z Frequency/CAS CL = 3 (DDR3-866) CL = (DDR3-600) CL = 9 (DDR3-333) CL = 7 (DDR3-066) -G Note:. Contact Micron for industrial temperature module offerings. Table : Key Timing Parameters Speed Grade Industry Nomenclature CL = 3 CL = Data Rate (MT/s) CL = 0 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 -G9 PC G6 PC G4 PC G PC G0 PC B PC t RCD (ns) t RP (ns) t RC (ns) PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN 008 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

2 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Features Table : Addressing Parameter GB 4GB 8GB Refresh count 8K 8K 8K Row address 6K A[3:0] 3K A[4:0] 64K A[5:0] Device bank address 8 BA[:0] 8 BA[:0] 8 BA[:0] Device page size per bank KB KB KB Device configuration Gb (8 Meg x 8) Gb (56 Meg x 8) 4Gb (5 Meg x 8) Column address K A[9:0] K A[9:0] K A[9:0] Module rank address S#[:0] S#[:0] S#[:0] Table 3: Part Numbers and Timing Parameters GB Base device: MT4J8M8, Gb DDR3 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate CL- t RCD- t RP (Clock Cycles) MT6JTF5664A(I)Z-G9 GB 56 Meg x GB/s.07ns/866 MT/s MT6JTF5664A(I)Z-G6 GB 56 Meg x 64.8 GB/s.5ns/600 MT/s -- MT6JTF5664A(I)Z-G4 GB 56 Meg x GB/s.5ns/333 MT/s MT6JTF5664A(I)Z-G GB 56 Meg x GB/s.87ns/066 MT/s Table 4: Part Numbers and Timing Parameters 4GB Base device: MT4J56M8, Gb DDR3 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate CL- t RCD- t RP (Clock Cycles) MT6JTF564A(I)Z-G9 4GB 5 Meg x GB/s.07ns/866 MT/s MT6JTF564A(I)Z-G6 4GB 5 Meg x 64.8 GB/s.5ns/600 MT/s -- MT6JTF564A(I)Z-G4 4GB 5 Meg x GB/s.5ns/333 MT/s MT6JTF564A(I)Z-G 4GB 5 Meg x GB/s.87ns/066 MT/s Table 5: Part Numbers and Timing Parameters 8GB Base device: MT4J5M8, 4Gb DDR3 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate CL- t RCD- t RP (Clock Cycles) MT6JTFG64A(I)Z-G9 8GB Gig x GB/s.07ns/866 MT/s MT6JTFG64A(I)Z-G6 8GB Gig x 64.8 GB/s.5ns/600 MT/s -- MT6JTFG64A(I)Z-G4 8GB Gig x GB/s.5ns/333 MT/s MT6JTFG64A(I)Z-G 8GB Gig x GB/s.87ns/066 MT/s Data sheets for the base device parts can be found on Micron s Web site.. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT6JTF564AZ-G6K. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN 008 Micron Technology, Inc. All rights reserved.

3 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Pin Assignments Pin Assignments Table 6: Pin Assignments 40-Pin UDIMM Front 40-Pin UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol V REF A A 3 6 V DD DM3 8 V DD DM S3# 63 CK 93 S5# NC 83 V DD 3 NC 4 34 S3 64 CK# 94 S CK V DD 95 5 DM CK0# S0# V DD NC V DD S V REFCA NC NC NC 88 A NC 69 V DD NC 89 V DD NC 70 A BA BA NC 9 V DD DM6 8 4 NC 7 V DD 0 S6# NC 9 RAS# NC NC 73 WE# 03 S S0# CAS# DM 64 NC 94 V DD S# 45 NC 75 V DD NC 65 NC 95 ODT S 46 NC 76 S# A ODT NC 97 V DD NC 78 V DD RESET# 98 NC NC 79 NC CKE CKE V DD DM7 6 5 V DD 8 3 S7# 4 7 NC/A NC 7 5 BA 8 33 S7 4 7 NC/A NC DM 73 V DD 03 DM S# 54 V DD 84 S4# NC 74 A 04 NC S 55 A 85 S A A V DD V DDSPD V DD SA A SA A SCL A SDA 9 59 A SA V DD V DD V TT A V TT. Pin 7 is NC for GB and 4GB, A5 for 8GB.. Pin 7 is NC for GB, A4 for 4GB and 8GB. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

4 Pin Descriptions Table 7: Pin Descriptions Symbol Type Description The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A0) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A0 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A0 LOW, bank selected by BAx) or all banks (A0 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR, MR, or MR3) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the and S pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins:, S, S#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I C bus. SCL Input Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I C bus. CBx I/O Check bits: Used for system error detection and correction. x I/O Data input/output: Bidirectional data bus. Sx, Sx# I/O GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Pin Descriptions Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

5 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Pin Descriptions Table 7: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sensor/spd EEPROM on the I C bus. TSx, TSx# Err_Out# EVENT# Output Output (open drain) Output (open drain) Redundant data strobe (x8 devices only): TS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TS is enabled, DM is disabled and TS and TS# provide termination resistance; otherwise, TS# are no function. Parity error output: Parity error found on the command and address bus. Temperature event:the EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. V DD Supply Power supply:.5v ±0.075V. The component V DD and V D are connected to the module V DD. V DDSPD Supply Temperature sensor/spd EEPROM power supply: V. V REFCA Supply Reference voltage: Control, command, and address V DD /. V REF Supply Reference voltage:, DM V DD /. Supply Ground. V TT Supply Termination voltage: Used for control, command, and address V DD /. NC No connect: These pins are not connected on the module. NF No function: These pins are connected within the module, but provide no functionality. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

6 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Map Map Table 8: Component-to-Module Map Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U 0 9 U U U U U U U PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

7 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Map Table 8: Component-to-Module Map (Continued) Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U U U U U U U U PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

8 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Functional Block Diagram Functional Block Diagram Figure : Functional Block Diagram S# S0# S0# S0 DM0 S# S DM S# S DM S3# S3 DM DM CS# S S# U DM CS# S S# U DM CS# S S# U3 DM CS# S S# U4 DM CS# S S# DM CS# S S# DM CS# S S# U7 DM CS# S S# U6 DM CS# S S# U5 DM CS# S S# U4 S4# S4 DM4 S5# S5 DM5 S6# S6 DM6 S7# S7 DM U5 U6 U3 DM CS# S S# DM CS# S S# U7 U DM CS# S S# DM CS# S S# U8 U DM CS# S S# DM CS# S S# U0 BA[:0] A[5/4:0] RAS# CAS# WE# CKE0 CKE ODT0 ODT RESET# CKE[:0], A[5/4:0], RAS#, CAS#, WE#, S#[:0], ODT[:0], BA[:0] CK[:0] CK#[:0] V DDSPD V DD V TT V REFCA V REF SCL CK0 CK0# CK CK# BA[:0]: DDR3 SDRAM A[5/4/3:0]: DDR3 SDRAM RAS#: DDR3 SDRAM CAS#: DDR3 SDRAM WE#: DDR3 SDRAM CKE0: Rank 0 CKE: Rank ODT0: Rank 0 ODT: Rank RESET#: DDR3 SDRAM Command, address, and clock line terminations DDR3 SDRAM DDR3 SDRAM U9 SPD EEPROM WP A0 A A SA0 SA SA Rank 0 = U U8 Rank = U0 U7 Rank 0 Rank SDA V TT SPD EEPROM V DD DDR3 SDRAM Address, command, and control termination DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM Note:. The ball on each DDR3 component is connected to an external 40Ω resistor that is tied to ground. Used for the calibration of the component s on-die termination and output driver. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

9 General Description GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM General Description DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: S, S# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR3. Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 56-byte EEPROM. The first 8 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 8 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I C bus using the DIMM s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to, permanently disabling hardware write protection. For further information refer to Micron technical note TN-04-4, "Memory Module Serial Presence-Detect." PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

10 Electrical Specifications Table 9: Absolute Maximum Ratings GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD V DD supply voltage relative to V V IN, V OUT Voltage on any pin relative to V Table 0: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage V I VTT Termination reference current from V TT ma V TT I I I OZ Termination reference voltage command address bus Input leakage current; Any input 0V V IN V DD ; V REF input 0V V IN 0.95V (All other pins not under test = 0V) Output leakage current; 0V V OUT V D ; s and ODT are disabled Address inputs RAS#, CAS#, WE#, BA S#, CKE, ODT, CK, CK# x V DD 0.5 x V DD 0.57 x V DD V µa DM 4 0 4, S, S# µa I VREF V REF leakage current; V REF = valid V REF level µa T A T C Module ambient operating temperature DDR3 SDRAM component case operating temperature Commercial 0 70 C, 3 Industrial C Commercial 0 95 C, 3, 4 Industrial C. V TT termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins.. T A and T C are simultaneous requirements. 3. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron s Web site. 4. The refresh rate is required to double when 85 C < T C 95 C. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

11 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. Component specifications are available on Micron s web site. Module speed grades correlate with component speed grades, as shown below. Table : Module and Component Speed Grades DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -G G9-07 -G6-5 -G4-5E -G -87E -G C -5E -80B -5 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN 008 Micron Technology, Inc. All rights reserved.

12 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM I DD Specifications I DD Specifications Table : DDR3 I DD Specifications and Conditions GB (Die Revision G) Values are for the MT4J8M8 DDR3 SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Symbol Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD ma Precharge power-down current: Slow exit I DDP ma Precharge power-down current: Fast exit I DDP ma Precharge quiet standby current I DDQ ma Precharge standby current I DDN ma Precharge standby ODT current I DDNT ma Active power-down current I DD3P ma Active standby current I DD3N ma Burst read operating current I DD4R ma Burst write operating current I DD4W ma Refresh current I DD5B ma Self refresh temperature current: MAX T C = 85 C I DD ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET ma All banks interleaved read current I DD ma Reset current I DD ma. One module rank in the active I DD ; the other rank in I DDP0 (slow exit).. All ranks in this I DD condition. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN 008 Micron Technology, Inc. All rights reserved.

13 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM I DD Specifications Table 3: DDR3 I DD Specifications and Conditions 4GB (Die Revision M) Values are for the MT4J56M8 DDR3 SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD ma Precharge power-down current: Slow exit I DDP ma Precharge power-down current: Fast exit I DDP ma Precharge quiet standby current I DDQ ma Precharge standby current I DDN ma Precharge standby ODT current I DDNT ma Active power-down current I DD3P ma Active standby current I DD3N ma Burst read operating current I DD4R ma Burst write operating current I DD4W ma Refresh current I DD5B ma Self refresh temperature current: MAX T C = 85 C I DD ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET ma All banks interleaved read current I DD ma Reset current I DD ma. One module rank in the active I DD ; the other rank in I DDP0 (slow exit).. All ranks in this I DD condition. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

14 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM I DD Specifications Table 4: DDR3 I DD Specifications and Conditions 4GB (Die Revision K) Values are for the MT4J56M8 DDR3 SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD ma Precharge power-down current: Slow exit I DDP ma Precharge power-down current: Fast exit I DDP ma Precharge quiet standby current I DDQ ma Precharge standby current I DDN ma Precharge standby ODT current I DDNT ma Active power-down current I DD3P ma Active standby current I DD3N ma Burst read operating current I DD4R ma Burst write operating current I DD4W ma Refresh current I DD5B ma Self refresh temperature current: MAX T C = 85 C I DD ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET ma All banks interleaved read current I DD ma Reset current I DD ma. One module rank in the active I DD ; the other rank in I DDP0 (slow exit).. All ranks in this I DD condition. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

15 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM I DD Specifications Table 5: DDR3 I DD Specifications and Conditions 8GB (Die Revision D) Values are for the MT4J5M8 DDR3 SDRAM only and are computed from values specified in the 4Gb (5 Meg x 8) component data sheet Parameter Symbol Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD ma Precharge power-down current: Slow exit I DDP ma Precharge power-down current: Fast exit I DDP ma Precharge quiet standby current I DDQ ma Precharge standby current I DDN ma Precharge standby ODT current I DDNT ma Active power-down current I DD3P ma Active standby current I DD3N ma Burst read operating current I DD4R ma Burst write operating current I DD4W ma Refresh current I DD5B ma Self refresh temperature current: MAX T C = 85 C I DD ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET ma All banks interleaved read current I DD ma Reset current I DD ma. One module rank in the active I DD ; the other rank in I DDP0 (slow exit).. All ranks in this I DD condition. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

16 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM I DD Specifications Table 6: DDR3 I DD Specifications and Conditions 8GB (Die Revisions E and J) Values are for the MT4J5M8 DDR3 SDRAM only and are computed from values specified in the 4Gb (5 Meg x 8) component data sheet Parameter Symbol Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD ma Precharge power-down current: Slow exit I DDP ma Precharge power-down current: Fast exit I DDP ma Precharge quiet standby current I DDQ ma Precharge standby current I DDN ma Precharge standby ODT current I DDNT ma Active power-down current I DD3P ma Active standby current I DD3N ma Burst read operating current I DD4R ma Burst write operating current I DD4W ma Refresh current I DD5B ma Self refresh temperature current: MAX T C = 85 C I DD ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET ma All banks interleaved read current I DD ma Reset current I DD ma. One module rank in the active I DD ; the other rank in I DDP0 (slow exit).. All ranks in this I DD condition. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

17 Serial Presence-Detect EEPROM For the latest SPD data, refer to Micron's SPD page: Table 7: Serial Presence-Detect EEPROM DC Operating Conditions GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Serial Presence-Detect EEPROM All voltages referenced to V DDSPD Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD V Input low voltage: Logic 0; All inputs V IL 0.45 V DDSPD x 0.3 V Input high voltage: Logic ; All inputs V IH V DDSPD x 0.7 V DDSPD +.0 V Output low voltage: I OUT = 3mA V OL 0.4 V Input leakage current: V IN = GND to V DD I LI 0..0 µa Output leakage current: V OUT = GND to V DD I LO µa Table 8: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes Clock frequency t SCL khz Clock pulse width HIGH time t HIGH 0.6 µs Clock pulse width LOW time t LOW.3 µs SDA rise time t R 300 µs SDA fall time t F ns Data-in setup time t SU:DAT 00 ns Data-in hold time t HD:DI 0 µs Data-out hold time t HD:DAT ns Data out access time from SCL LOW t AA:DAT µs Start condition setup time t SU:STA 0.6 µs 3 Start condition hold time t HD:STA 0.6 µs Stop condition setup time t SU:STO 0.6 µs Time the bus must be free before a new transition can start t BUF.3 µs WRITE time t W 0 ms. Guaranteed by design and characterization, not necessarily tested.. To avoid spurious start and stop conditions, a minimum delay is placed between the falling edge of SCL and the falling or rising edge of SDA. 3. For a restart condition, or following a WRITE cycle. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.

18 GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Module Dimensions Module Dimensions Figure 3: 40-Pin DDR3 UDIMM Front view (5.56) 33.0 (5.44) 4.0 (0.57) MAX 0.9 (0.035) TYP 0.50 (0.0) R (4X) 0.75 (0.03) R (8X).50 (0.098) D (X) U U U3 U4 U9 U5 U6 U7 U8 7.3 (0.68) TYP 3.3 (0.9) TYP (.0) 9.85 (.75).30 (0.09) TYP.0 (0.087) TYP.45 (0.057) TYP Pin (.5) TYP 0.76 (0.030) R.0 (0.039) TYP 0.80 (0.03) TYP 9.5 (0.374) TYP Pin 0.37 (0.054).7 (0.046) 3.0 (4.84) TYP 5.0 (0.59) 4X TYP Back view.0 (0.039) R (8X) 45, 4X 5. (0.) TYP U0 U U U3 U4 U5 U6 U7 3. (0.) X TYP 3.0 (0.8) 4X TYP 3.05 (0.) TYP Pin 40 Pin 5.0 (0.97) TYP 7.0 (.79) TYP 47.0 (.85) TYP. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions S. Federal Way, P.O. Box 6, Boise, ID , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef837cddd jtf6c56_5_gx64az.pdf - Rev. I 04/3 EN Micron Technology, Inc. All rights reserved.