PC1600 and PC2100 DDR SDRAM Unbuffered DIMM Design Specification Revision 1.1 June 29, 2001

Transcription

1 PC1600 and PC2100 DDR DRAM Unbuffered DIMM Design pecification Revision 1.1 June 29, 2001

2 Table of Contents PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Table of Contents Table of Contents...2 Product Description...3 Product Family Attributes... 3 Environmental Requirements...5 Architecture...5 Absolute Maximum Ratings... 5 Pin Description... 5 Input/Output Functional Description Pin DDR DRAM DIMM Pin Assignments... 7 Block Diagram: Raw Card Version A, x Block Diagram: Raw Card Version A, x Block Diagram: Raw Card Version B, x Block Diagram: Raw Card Version B, x Block Diagram: Raw Card Version C, x Block Diagram: Raw Card Version C, x Logical Clock Net tructures Component Details...15 Pin Assignments for 64Mb, 128Mb, 256Mb and 512Mb DDR DRAM Planar Components DDR DRAM Component pecifications Unbuffered DIMM Details...16 DRAM Module Configurations (Reference Designs) DDR Unbuffered Design File Releases Input Loading Matrix Component Types and Placement Example Raw Card A Component Placement Example Raw Card B Component Placement Example Raw Card C Component Placement DIMM Wiring Details...20 ignal Groups General Net tructure Routing Guidelines Explanation of Net tructure Diagrams Net tructure Example Clock Net tructures ignal Net tructures Cross ection Recommendations Decoupling Page 2 Revision 1.1

3 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Table of Contents Design Target...35 Address setup/hold flight times Clock kew Contributions (tkew) erial PD Definition...36 erial Presence Detect Example Raw Card Version B erial Presence Detect Component pecification Product Label...38 DIMM Mechanical pecifications...39 implified Mechanical Drawing with Keying Positions Clocking Timing Methodology...40 Unbuffered DIMM Differential Clock Reference Net Revision Log...41 Revision 1.1 Page 3

4 1. Product Description PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 1. Product Description This specification defines the electrical and mechanical requirements for 184-pin, 2.5 Volt (V DD )/ 2.5 Volt (V DDQ ), Unbuffered, Double Data Rate, ynchronous DRAM Dual In-Line Memory Modules (DDR DRAM DIMMs).These DDR DIMMs are intended for use as main memory when installed in PCs. The DDR DIMMs must permit operation with a new address every clock cycle in PC1600 and PC2100 environments. Reference design examples are included which provide an initial basis for Unbuffered DDR DIMM designs. Modifications to these reference designs may be required to meet all system timing, signal integrity and thermal requirements for PC1600 and PC2100 support. All Unbuffered DIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. This specification largely follows the JEDEC defined 184-pin Unbuffered DDR DRAM DIMM product. (Refer to JEDEC standard JED21-C, ection , at Product Family Attributes DIMM Organization x64, x72 ECC Notes DIMM Dimensions (max) 5.256" x 1.256" x 0.157" Pin Count 184 DDR DRAMs upported Capacity erial PD Voltage Options Interface 64Mb, 128Mb, 256Mb, 512Mb 32MB - 1GB Consistent with JEDEC JC 42.5 Item 849A 2.5 Volt V DD /V DDQ 2.3 Volt to 3.6 Volt V DD PD TL_2 All DDR modules use a common V DD - V DDQ power plane. They are tied together on the DIMM, but by standard definition are supported on the pinout to accommodate future enhancements. Note 1: V DD PD is not tied to V DD or V DDQ on the DDR DIMM. Page 4 Revision 1.1

5 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 2. Environmental Requirements 2. Environmental Requirements 184-pin Unbuffered DDR DRAM DIMMs are intended for use in standard office environments that have limited capacity for heating and air conditioning. Absolute Maximum Ratings ymbol Parameter Rating Units Notes T OPR Operating Temperature (ambient) 0 to +55 C 1 H OPR Operating Humidity (relative) 10 to 90 % 1 T TG torage Temperature -50 to +100 C 1 H TG torage Humidity (without condensation) 5 to 95 % 1 Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2 1. tresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. Architecture Pin Description Pin Name Description Pin Name Description A0 - A13 DRAM address bus CK0 - CK2 DRAM clock (positive lines of 3 differential pairs) BA0 - BA1 DRAM bank select CK0 - CK2 DRAM clock (negative lines of these three pairs) DQ0 - DQ63 DIMM memory data bus CL IIC serial bus clock for EEPROM CB0 - CB7 DIMM ECC check bits DA IIC serial bus data line for EEPROM /RA DRAM row address strobe A0 - A2 IIC slave address select for EEPROM /CA DRAM column address strobe V DD * DRAM positive power supply /WE DRAM write strobe V DDQ * DRAM I/O Driver positive power supply /0 - /1 DRAM chip select lines (Phys. banks 0 and 1) VREF DRAM I/O reference supply CKE0 - CKE1 DRAM clock enable lines V Power supply return (ground) DQ0 - DQ8 DRAM low data strobes V DD PD erial EEPROM positive power supply (2.3 Volts to 3.6 Volts)--VDDPD is not connected to V DD or V DDQ (0-8)/DQ(9-17) DRAM low data masks/high data strobes (x4, 2 Phys. banks) pare pins (no connect) V DD ID V DD identification flag *The VDD and VDDQ pins are tied to the single power-plane on these designs. ee page 35. Revision 1.1 Page 5

6 3. Architecture PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Input/Output Functional Description ymbol Type Polarity Function CK0 - CK2 (TL) Positive Edge The positive line of the differential pair of system clock inputs. All the DDR DRAM addr/cntl inputs are sampled on the rising edge of their associated clocks. CK0 - CK2 (TL) Negative Edge The negative line of the differential pair of system clock inputs. CKE0, CKE1 (TL) Active High Activates the DRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the elf Refresh mode. 0, 1 (TL) Active Low RA, CA, WE (TL) Active Low V REF upply Reference voltage for TL2 inputs. Enables the associated DRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CA, RA, and WE define the operation to be executed by the DRAM. V DDQ upply Power supply for the DDR DRAM output buffers to provide improved noise immunity. For all current DDR unbuffered DIMM designs, V DDQ shares the same power plane as V DD pins. BA0,1 (TL) elects which DRAM bank of four is activated. A0 - A9 A10/AP, A11-A13 (TL) During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-12 defines the column address (CA0-CA12) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge. DQ0 - DQ63, CB0 - CB7 (TL) Data and Check Bit Input/Output pins. 0-8 (TL) Active High Masks write data when high, issued concurrently with input data. Both and DQ have a write latency of one clock once the write command is registered into the DRAM. V DD, V upply Power and ground for the DDR DRAM input buffers, and core logic. V DD and V DDQ pins are tied to a single combined V DD /V DDQ plane on these modules. DQ0-DQ8 (TL) Negative and Positive Edge Data strobe for input and output data. For the x16, LDQ corresponds to the data on DQ0-7, VDQs corresponds to the data on DQ8-15. A0-2 DA CL These signals are tied at the system planar to either V or V DD to configure the serial PD EEPROM address range. This bidirectional pin is used to transfer data into or out of the PD EEPROM. A resistor must be connected from the DA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the PD EEPROM. A resistor may be connected from the CL bus time to V DD to act as a pullup. V DD PD upply Power supply for PD EEPROM. This supply is separate from the V DD /V DDQ power plane. EEPROM supply is operable from 2.3V to 3.6V. Page 6 Revision 1.1

7 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 3. Architecture 184-Pin DDR DRAM DIMM Pin Assignments Front ide (left side 1-52, right side 53-92) Back ide (left side , right side ) Front ide (left side 1-52, right side 53-92) Back ide (left side , right side ) Pin # x64 x72 x64 x72 x64 x72 x64 x72 Pin # Pin # Pin # Non-Parity ECC Non-Parity ECC Non-Parity ECC Non-Parity ECC 1 VREF VREF 93 V V 48 A0 A /DQ17 2 DQ0 DQ0 94 DQ4 DQ4 49 CB2 141 A10 A10 3 V V 95 DQ5 DQ5 50 V V 142 CB6 4 DQ1 DQ1 96 VDDQ VDDQ 51 CB3 143 VDDQ VDDQ 5 DQ0 DQ0 97 0/DQ9 0/DQ9 52 BA1 BA1 144 CB7 6 DQ2 DQ2 98 DQ6 DQ6 KEY KEY 7 V DD V DD 99 DQ7 DQ7 53 DQ32 DQ V V 8 DQ3 DQ3 100 V V 54 V DDQ V DDQ 146 DQ36 DQ DQ33 DQ DQ37 DQ DQ4 DQ4 148 V DD V DD 11 V V 103 (FETEN) (FENTEN) 57 DQ34 DQ /DQ13 4/DQ13 12 DQ8 DQ8 104 V DDQ V DDQ 58 V V 150 DQ38 DQ38 13 DQ9 DQ9 105 DQ12 DQ12 59 BA0 BA0 151 DQ39 DQ39 14 DQ1 DQ1 106 DQ13 DQ13 60 DQ35 DQ V V 15 V DDQ V DDQ 107 1/DQ10 1/DQ10 61 DQ40 DQ DQ44 DQ44 16 CK1 CK1 108 V DD V DD 62 V DDQ V DDQ 154 /RA /RA 17 /CK1 /CK1 109 DQ14 DQ14 63 /WE /WE 155 DQ45 DQ45 18 V V 110 DQ15 DQ15 64 DQ41 DQ VDDQ VDDQ 19 DQ10 DQ CKE1 CKE1 65 /CA /CA 157 /0 /0 20 DQ11 DQ V DDQ V DDQ 66 V V 158 /1 /1 21 CKE0 CKE0 113 BA2 BA2 67 DQ5 DQ /DQ14 5/DQ14 22 V DDQ V DDQ 114 DQ20 DQ20 68 DQ42 DQ V V 23 DQ16 DQ A12 A12 69 DQ43 DQ DQ46 DQ46 24 DQ17 DQ V V 70 V DD V DD 162 DQ47 DQ47 25 DQ2 DQ2 117 DQ21 DQ21 71, /2, /2 163, /3, /3 26 V V 118 A11 A11 72 DQ48 DQ V DDQ V DDQ 27 A9 A /DQ11 2/DQ11 73 DQ49 DQ DQ52 DQ52 28 DQ18 DQ VDD VDD 74 V V 166 DQ53 DQ53 29 A7 A7 121 DQ22 DQ22 75 /CK2 /CK2 167 A13 A13 30 V DDQ V DDQ 122 A8 A8 76 CK2 CK2 168 V DD V DD 31 DQ19 DQ DQ23 DQ23 77 V DDQ V DDQ 169 6/DQ15 6/DQ15 32 A5 A5 124 V V 78 DQ6 DQ6 170 DQ54 DQ54 33 DQ24 DQ A6 A6 79 DQ50 DQ DQ55 DQ55 34 V V 126 DQ28 DQ28 80 DQ51 DQ V DDQ V DDQ 35 DQ25 DQ DQ29 DQ29 81 V V DQ3 DQ3 128 VDDQ VDDQ 82 VDDID VDDID 174 DQ60 DQ60 37 A4 A /DQ12 3/DQ12 83 DQ56 DQ DQ61 DQ61 38 V DD V DD 130 A3 A3 84 DQ57 DQ V V 39 DQ26 DQ DQ30 DQ30 85 V DD V DD 177 7/DQ16 7/DQ16 40 DQ27 DQ V V 86 DQ7 DQ7 178 DQ62 DQ62 41 A2 A2 133 DQ31 DQ31 87 DQ58 DQ DQ63 DQ63 42 V V 134 CB4 88 DQ59 DQ V DDQ V DDQ 43 A1 A1 135 CB5 89 V V 181 A0 A0 44 CB0 136 V DDQ V DDQ A1 A1 45 CB1 137 CK0 CK0 91 DA DA 183 A2 A2 46 V DD V DD 138 /CK0 /CK0 92 CL CL 184 VDDPD VDDPD 47 DQ8 139 V V = No Connect NU = Not Useable Revision 1.1 Page 7

8 3. Architecture PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Block Diagram: Raw Card Version A, x72 (Populated as 1 physical bank of x8 DDR DRAMs) BA0 - BA1 A0 - A13 DQ0 0/DQ9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 1/DQ10 DQ2 2/DQ11 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ3 3/DQ12 DQ8 8/DQ17 RA CA CKE0 WE DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 0 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 D0 D1 D2 D3 BA0-BA1: DRAMs D0 - D8 A0-A13: DRAMs D0 - D8 RA: DRAMs D0 - D8 CA: DRAMs D0 - D8 CKE: DRAMs D0 - D8 WE: DRAMs D0 - D8 D8 DQ DQ DQ DQ DQ V DD PD V DD /V DDQ V REF DQ4 4/DQ13 DQ5 5/DQ14 DQ6 6/DQ15 CL DQ7 7/DQ16 WP A0 erial PD A1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 A2 A0 A1 A2 PD D0 - D8 D0 - D8 V D0 - D8 V DDID trap: see Note 4 DA D4 D5 D6 D7 DQ DQ DQ DQ * Clock Wiring Clock Input DRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 3 DRAMs 3 DRAMs 3 DRAMs * Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQ//CKE/ relationships must be maintained as shown. 3. DQ, DQ, /DQ resistors: 22 Ohms ± 5%. 4. V DDID strap connections (for memory device V DD, V DDQ ): TRAP OUT (OPEN): V DD = V DDQ TRAP IN (V ): V DD V DDQ. Page 8 Revision 1.1

9 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 3. Architecture Block Diagram: Raw Card Version A, x64 (Populated as 1 physical bank of x8 DDR DRAMs) BA0 - BA1 A0 - A13 RA CA CKE0 WE DQ0 0/DQ9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 1/DQ10 DQ2 2/DQ11 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ3 3/DQ12 CL WP A0 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 erial PD A1 0 DQ15 A2 A0 A1 A2 D0 D1 D2 D3 DA BA0-BA1: DRAMs D0 - D7 A0-A13: DRAMs D0 - D7 RA: DRAMs D0 - D7 CA: DRAMs D0 - D7 CKE: DRAMs D0 - D7 WE: DRAMs D0 - D7 DQ DQ DQ DQ V DD PD V DD /V DDQ V REF DQ4 4/DQ13 DQ5 5/DQ14 DQ6 6/DQ15 DQ7 7/DQ16 * Clock Wiring Clock Input DRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 2 DRAMs 3 DRAMs 3 DRAMs * Wire per Clock Loading Table/Wiring Diagrams DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 PD D0 - D7 D0 - D7 V D0 - D7 V DDID trap: see Note 4 D4 D5 D6 D7 DQ DQ DQ DQ Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQ//CKE/ relationships must be maintained as shown. 3. DQ, DQ, /DQ resistors: 22 Ohms ± 5%. 4. V DDID strap connections (for memory device V DD, V DDQ ): TRAP OUT (OPEN): V DD = V DDQ TRAP IN (V ): V DD V DDQ. Revision 1.1 Page 9

10 3. Architecture PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Block Diagram: Raw Card Version B, x64 (Populated as 2 physical banks of x8 DDR DRAMs) DQ0 0/DQ9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 1/DQ10 DQ2 2/DQ11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ3 3/DQ12 V DD PD BA0 - BA1 A0 - A13 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D0 D2 D3 A0-A13: DRAMs D0 - D15 D8 D10 D11 DQ4 4/DQ13 DQ5 5/DQ14 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ7 7/DQ16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 V DD /V DDQ D0 - D15 erial PD V REF D0 - D15 CL V D0 - D15 WP DA V DDID trap: see Note 4 A0 A1 A2 A0 A1 A2 Notes: CKE1 RA CA CKE0 WE 0 CKE: DRAMs D8 - D15 RA: DRAMs D0 - D15 CA: DRAMs D0 - D15 CKE: DRAMs D0 - D7 WE: DRAMs D0 - D15 DQ DQ DQ BA0-BA1: DRAMs D0 - D15 1 DQ DQ DQ DQ6 6/DQ15 D4 D6 D7 DQ DQ DQ DQ DQ DQ DQ8 DQ40 DQ9 D1 DQ41 D9 D5 D13 DQ10 DQ42 DQ11 DQ43 DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 PD * Clock Wiring Clock Input DRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 4 DRAMs 6 DRAMs 6 DRAMs * Wire per Clock Loading Table/Wiring Diagrams DQ D12 D14 D15 DQ DQ DQ 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQ//CKE/ relationships must be maintained as shown. 3. DQ, DQ, /DQ resistors: 22 Ohms ± 5%. 4. V DDID strap connections (for memory device V DD, V DDQ ): TRAP OUT (OPEN): V DD = V DDQ TRAP IN (V ): V DD V DDQ Page 10 Revision 1.1

11 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 3. Architecture Block Diagram: Raw Card Version B, x72 (Populated as 2 physical banks of x8 DDR DRAMs) DQ0 0/DQ9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 1/DQ10 DQ2 2/DQ11 D0 D9 DQ DQ DQ DQ DQ8 DQ40 DQ9 D1 DQ41 D10 D5 D14 DQ10 DQ42 DQ11 DQ43 DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ3 3/DQ12 DQ8 8/DQ17 BA0 - BA1 A0 - A13 CKE1 RA CA CKE0 WE DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 0 D2 D3 A0-A13: DRAMs D0 - D17 CKE: DRAMs D9 - D17 RA: DRAMs D0 - D17 CA: DRAMs D0 - D17 CKE: DRAMs D0 - D8 WE: DRAMs D0 - D17 D8 DQ DQ DQ DQ BA0-BA1: DRAMs D0 - D17 1 CL D11 D12 D17 WP A0 DQ DQ DQ DQ4 4/DQ13 DQ5 5/DQ14 DQ6 6/DQ15 V DD /V DDQ DQ V REF erial PD A1 DQ7 7/DQ16 V DD PD V V DDID A2 A0 A1 A2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 trap: see Note 4 Notes: DA D4 D6 PD D7 D0 - D17 D0 - D17 D0 - D17 DQ DQ DQ D13 D15 D16 * Clock Wiring Clock Input DRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 DQ DQ DQ 6 DRAMs 6 DRAMs 6 DRAMs * Wire per Clock Loading Table/Wiring Diagrams 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQ//CKE/ relationships must be maintained as shown. 3. DQ, DQ, /DQ resistors: 22 Ohms ± 5%. 4. V DDID strap connections (for memory device V DD, V DDQ ): TRAP OUT (OPEN): V DD = V DDQ TRAP IN (V ): V DD V DDQ Revision 1.1 Page 11

12 3. Architecture PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Block Diagram: Raw Card Version C, x64 (Populated as 1 physical bank of x16 DDR DRAMs) 0 DQ1 1/DQ10 DQ0 0/DQ9 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQ L UDQ U I/O 8 I/O D0 DQ5 5/DQ14 DQ4 4/DQ13 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQ L UDQ U I/O 8 I/O D2 DQ3 3/DQ12 DQ2 2/DQ11 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQ L UDQ U I/O 8 I/O D1 DQ7 7/DQ16 DQ6 6/DQ15 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQ L UDQ U I/O 8 I/O D3 V DD PD V DD /V DDQ V REF V BA0 - BA1 A0 - A13 RA CA CKE0 WE PD D0 - D3 D0 - D3 D0 - D3 BA0-BA1: DRAMs D0 - D3 A0-A13: DRAMs D0 - D3 RA: DRAMs D0 - D3 CA: DRAMs D0 - D3 CKE: DRAMs D0 - D3 WE: DRAMs D0 - D3 CL WP A0 erial PD A1 A2 A0 A1 A2 DA * Clock Wiring Clock Input DRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 2 DRAMs 2 DRAMs * Wire per Clock Loading Table/Wiring Diagrams V DDID trap: see Note 4 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQ//CKE/ relationships must be maintained as shown. 3. DQ, DQ, /DQ resistors: 22 Ohms ± 5%. 4. V DDID strap connections (for memory device V DD, V DDQ ): TRAP OUT (OPEN): V DD = V DDQ TRAP IN (V ): V DD V DDQ 5. BA, Ax, RA, CA, WE resistors: 7.5 Ohms ± 5% Page 12 Revision 1.1

13 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 3. Architecture Block Diagram: Raw Card Version C, x72 (Populated as 1 physical bank of x16 DDR DRAMs) 0 DQ1 1/DQ10 DQ0 0/DQ9 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQ L UDQ U I/O 8 I/O D0 DQ5 5/DQ14 DQ4 4/DQ13 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQ L UDQ U I/O 8 I/O D2 BA0 - BA1 A0 - A13 RA CA CKE0 WE DQ3 3/DQ12 DQ2 2/DQ11 100K V CC DQ8 8/DQ17 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 100K NU NU NU NU NU NU NU NU CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 LDQ L UDQ U I/O 8 I/O LDQ L UDQ U I/O 8 I/O BA0-BA1: DRAMs D0 - D4 D1 D4 CL DQ7 7/DQ16 DQ6 6/DQ15 WP A0 erial PD A0-A13: DRAMs D0 - D4 V DD PD PD RA: DRAMs D0 - D4 CA: DRAMs D0 - D4 V DD /V DDQ D0 - D4 CKE: DRAMs D0 - D4 V REF D0 - D4 WE: DRAMs D0 - D4 V D0 - D4 V DDID trap: see Note 4 A1 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 A2 A0 A1 A2 LDQ L UDQ U I/O 8 I/O DA D3 * Clock Wiring Clock Input DRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 1 DRAMs 2 DRAMs 2 DRAMs * Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQ//CKE/ relationships must be maintained as shown. 3. DQ, DQ, /DQ resistors: 22 Ohms ± 5%. 4. V DDID strap connections (for memory device V DD, V DDQ ): TRAP OUT (OPEN): V DD = V DDQ TRAP IN (V ): V DD V DDQ 5. BA, Ax, RA, CA, WE resistors: 7.5 Ohms ± 5% Revision 1.1 Page 13

14 3. Architecture PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Logical Clock Net tructures 6 DRAM Loads DRAM1 CK DIMM Connector CK R = 120Ω ± 5% DRAM2 DRAM3 DRAM4 4 DRAM Loads DRAM1 DRAM5 DRAM6 DIMM Connector R = 120Ω ± 5% DRAM2 Cap. 3 DRAM Loads DRAM1 Cap. DRAM5 DIMM Connector R = 120Ω ± 5% Cap. DRAM3 DRAM6 Cap. DRAM5 2 DRAM Loads DRAM1 1 DRAM Loads Cap. Cap. DIMM Connector R = 120Ω ± 5% Cap. Cap. Cap. DIMM Connector R = 120Ω ± 5% Cap. DRAM3 DRAM5 Cap. Cap. Cap. Cap. Cap. = 1/2 DDR DRAM input capacitance; 1.5pF ± 20% Page 14 Revision 1.1

15 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 4. Component Details 4. Component Details Pin Assignments for 64Mb, 128Mb, 256Mb and 512Mb DDR DRAM Planar Components (Top View) V DD DQ0 V DDQ DQ1 V Q DQ2 V DDQ DQ3 V Q V DDQ V DD WE CA RA C BA0 BA1 A10/AP A0 A1 A2 A3 V DD V DD DQ0 V DDQ DQ1 DQ2 V Q DQ3 DQ4 V DDQ DQ5 DQ6 V Q DQ7 V DDQ LDQ V DD L WE CA RA C BA0 BA1 A10/AP A0 A1 A2 A3 V DD V DQ15 V Q DQ14 DQ13 V DDQ DQ12 DQ11 V Q DQ10 DQ9 V DDQ DQ8 V Q UDQ V REF V U CLK CLK CKE /A12 1 A11 A9 A8 A7 A6 A5 A4 V V DQ7 V Q DQ6 V DDQ DQ5 V Q DQ4 V DDQ V Q DQ V REF V CLK CLK CKE /A12 1 A11 A9 A8 A7 A6 A5 A4 V 4Mb x 16, 8Mb x 16, 16Mb x 16, 32Mb x 16 8Mb x 8, 16Mb x 8, 32Mb x 8, 64Mb x 8 Notes: 1. A12 is utilized on the 256Mbit and 512Mbit DDR DRAM devices. Revision 1.1 Page 15

16 5. Unbuffered DIMM Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification DDR DRAM Component pecifications The DDR DRAM components used with this DIMM design specification are intended to be consistent with JEDEC ballots JC A. DDR DRAM component specification violations also violate the DDR DRAM Unbuffered DIMM specifications. 5. Unbuffered DIMM Details DRAM Module Configurations (Reference Designs) Raw Card Version DIMM Capacity DIMM Organization DRAM Density DRAM Organization # of DRAMs DRAM Package Type # of Physical Banks # of Banks in DRAM # Address bits row/col A B C 64 MB 128MB 256MB 512MB 128MB 256MB 512MB 1GB 32MB 64MB 128MB 256MB 8Mx64 64Mbit 8Mx lead TOP /9 8Mx72 64Mbit 8Mx lead TOP /9 16Mx64 128Mbit 16Mx lead TOP /10 16Mx72 128Mbit 16Mx lead TOP /10 32Mx64 256Mbit 32Mx lead TOP /10 32Mx72 256Mbit 32Mx lead TOP /10 64Mx64 512Mbit 64Mx lead TOP /11 64Mx72 512Mbit 64Mx lead TOP /11 16Mx64 64Mbit 8Mx lead TOP /10 16Mx72 64Mbit 8Mx lead TOP /10 32Mx64 128Mbit 16Mx lead TOP /10 32Mx72 128Mbit 16Mx lead TOP /10 64Mx64 256Mbit 32Mx lead TOP /10 64Mx72 256Mbit 32Mx lead TOP /10 128Mx64 512Mbit 64Mx lead TOP /11 128Mx72 512Mbit 64Mx lead TOP /11 4Mx64 64Mbit 4Mx lead TOP /8 4Mx72 64Mbit 4Mx lead TOP /8 8Mx64 128Mbit 8Mx lead TOP /9 8Mx72 128Mbit 8Mx lead TOP /9 16Mx64 256Mbit 16Mx lead TOP /10 16Mx72 256Mbit 16Mx lead TOP /10 32Mx64 512Mbit 32Mx lead TOP /10 32Mx72 512Mbit 32Mx lead TOP /10 Page 16 Revision 1.1

17 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 5. Unbuffered DIMM Details Input Loading Matrix ignal Names Input Device R/C A R/C B R/C C Clock (CK0 - CK2) DRAM CKE0/CKE1/Chipselects DRAM Addr/RA/CA/BA/WE DRAM DQ/CB/DQ/ DRAM CL/DA/A EEPROM DRAMs or equivalent using padding capacitors DDR Unbuffered Design File Releases Reference design file updates will be released as needed. This DDR Unbuffered DIMM specification will reflect the most recent design files, but may also be updated to reflect clarifications to the specification only; in these cases the design files will not be updated. The following table outlines the most recent design file releases. Note: Future design file releases will include both a date and a revision label. All changes to the design file are also documented within the read-me file. Raw Card Version pecification Revision Applicable Gerber File Notes A B C 1.0 A0 Production ready 1.1 A0 Production ready 1.0 B1 Production ready 1.1 B1 Production ready 1.0 C1 Production ready 1.1 C2 Production ready Revision 1.1 Page 17

18 5. Unbuffered DIMM Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Component Types and Placement Components shall be positioned on the PCB to meet the minimum and maximum trace lengths required for DDR DRAM signals. Bypass capacitors for DDR DRAM devices must be located near the device power pins. The following layouts suggest placement for the Raw Card Versions A, B and C. Exact spacing is not provided, but should be based on manufacturing contraints and signal routing constraints imposed by this design guide. Example Raw Card A Component Placement FRONT N/A for x PD (2X) MAX IDE (2) / / Page 18 Revision 1.1

19 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 5. Unbuffered DIMM Details Example Raw Card B Component Placement FRONT N/A for x64 PD (2X) (2) BACK MAX IDE N/A for x64 (Front) / / Note: All dimensions are typical unless otherwise stated millimeters inches Example Raw Card C Component Placement FRONT N/A for x PD (2X) MAX IDE (2) / /-.004 Revision 1.1 Page 19

20 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details ignal Groups This specification categorizes DDR DRAM timing-critical signals into five groups. The following table summarizes the signals contained in each group.. ignal Group ignals In Group Raw Card Version Page Clock CK [3:0] A, B, C 22 Data DQ [63:0]; CB [7:0]; DQ [8:0], [8:0] A, B, C 23 Chip elect Clock Enable [0,1] A, B 26 [0,1] C 27 CKE [0,1] A, B 27 CKE [0,1] C 30 Address/Control General Net tructure Routing Guidelines Ax, BAx, RA, CA, WE A,B 29 Ax, BAx, RA, CA, WE C 33 Net structures and lengths must satisfy signal quality and setup/hold time requirements for the memory interface. Net structure diagrams for each signal group are shown in the following sections. Each diagram is accompanied by a trace length table that lists the minimum and maximum allowable lengths for each trace segment and/or net. The general routing requirements are as follows Route all signal traces including differential clocks using 4/6 rules, i.e., 4 mil traces and 6 mil minimum spacing between adjacent traces. No test points are required. Page 20 Revision 1.1

21 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details Explanation of Net tructure Diagrams The net structure routing diagrams provide a reference design example for each raw card version. These designs provide an initial basis for registered DIMM designs. The diagrams should be used to determine individual signal wiring on a DIMM for any supported configuration. Only transmission lines (represented as cylinders and labeled with trace length designators TL ) represent physical trace segments. All other lines are zero in length. To verify DIMM functionality, a full simulation of all signal integrity and timing is required. The given net structures and trace lengths are not inclusive for all solutions. Once the net structure has been determined, the permitted trace lengths for the net structure can be read from the table below each net structure routing diagram. ome configurations require the use of multiple net structure routing diagrams to account for varying load quantities on the same signal. All diagrams define one load as one DRAM input. Net tructure Example A 128MB double-sided ECC DIMM using 64Mbit 8Mx8 DDR DRAM devices would have a data net structure as shown in the following diagram. TL2 DIMM Connector TL0 22 ohms ± 5% TL1 TL2 Revision 1.1 Page 21

22 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Clock Net tructures CK[3:0] DRAM clock signals must be carefully routed to meet the following requirements: ignal quality Rise/fall time DRAM component edge skew Motherboard chipset clock edge skew. Net tructure Routing for Clocks TL2 DIMM Conector CLK CLK TL0 R1 ± 5% TL1 TL2 TL2 Trace Lengths for Clock Net tructures Raw Card TL0 TL1 TL2 R1 Min Max Min Max Min Max Min Max Ohms Notes A,B ,2 C ,2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch 2. Logical clock structures on page 15 must be followed. In some cases the loads will be equivalent capacitors. Page 22 Revision 1.1

23 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details ignal Net tructures DQ[63:0], CB[7:0], DQ [8:0] and [8:0] Net tructure Routing for Data (Raw Card Versions A and C) DIMM Connector TL0 R1 ± 5% TL1 Trace Lengths for DQ, CB and DQ Net tructures (Raw Card Versions A and C) Raw Card TL0 TL1 Total R1 Min Max Min Max Min Max Ohms Notes A ,2 C ,2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1. Trace Lengths for Net tructures (Raw Card Versions A and C) Raw Card TL0 TL1 Total R1 Min Max Min Max Min Max Ohms Notes A ,2 C ,2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1. Revision 1.1 Page 23

24 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Net tructure Routing for Data (Raw Card Version B) TL2 DIMM Connector TL0 R1 ± 5% TL1 TL2 Trace Lengths for DQ, CB, and DQ Net tructures (Raw Card Version B) Raw Card TL0 TL1 TL2 Total R1 Min Max Min Max Min Max Min Max Ohms Notes B ,2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1 + TL2. Trace Lengths for Net tructures (Raw Card Version B) Raw Card TL0 TL1 TL2 Total R1 Min Max Min Max Min Max Min Max Ohms Notes B ,2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1 + TL2. Page 24 Revision 1.1

25 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details Net tructure Routing for Chip elect (Raw Card Version A) TL4 TL1 TL4 DIMM Connector TL0 (ECC) TL2 Trace Lengths for Chip elect Net tructures (0) Raw Card TL0 TL1 TL2 TL4 Notes Min Max Min Max Min Max Min Max Min Max Min Max Min Max A All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. Revision 1.1 Page 25

26 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Net tructure Routing for Chip elect (Raw Card Version B) TL4 TL1 TL4 DIMM Connector TL0 (ECC) TL2 Trace Lengths for Chip elect Net tructures (0, 1) Raw Card TL0 TL1 TL2 TL4 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Notes B ,2 1. All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. 2. DRAMs shown alternate between the front and back of the DIMM. Page 26 Revision 1.1

27 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details Net tructure Routing for Chip elect (Raw Card Version C) TL4 DIMM Connector TL0 TL1 TL2 (ECC) TL4 Trace Lengths for Chip elect Net tructures (0) Raw Card TL0 TL1 TL2 TL4 Min Max Min Max Min Max Min Max Min Max Min Max Notes C All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. Revision 1.1 Page 27

28 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Net tructure Routing for Clock Enable (Raw Card Version A) TL4 TL1 TL4 DIMM Connector TL0 (ECC) TL2 Trace Lengths for Clock Enable Net tructures (CKE0) Raw Card TL0 TL1 TL2 TL4 Notes Min Max Min Max Min Max Min Max Min Max Min Max Min Max A All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. Page 28 Revision 1.1

29 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details Net tructure Routing for Clock Enable (Raw Card Version B) TL4 TL1 TL4 DIMM Connector TL0 (ECC) TL2 Trace Lengths for Clock Enable Net tructures (CKE0, CKE1) Raw Card TL0 TL1 TL2 TL4 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Notes B ,2 1. All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. 2. DRAMs shown alternate between the front and back of the DIMM. Revision 1.1 Page 29

30 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Net tructure Routing for Clock Enable (Raw Cards Version C) TL4 DIMM Connector TL0 TL1 TL2 (ECC) TL4 Trace Lengths for Clock Enable Net tructures (CKE0) Raw Card TL0 TL1 TL2 TL4 Min Max Min Max Min Max Min Max Min Max Min Max Notes C All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. Page 30 Revision 1.1

31 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details Net tructure Routing for Address and Control (Raw Card Version A) A, BA, RA, CA, WE for Raw Card Version A TL4 TL1 TL4 DIMM Connector TL0 (ECC) TL2 Trace Lengths for Address and Control Net tructures Raw Card TL0 TL1 TL2 TL4 Notes Min Max Min Max Min Max Min Max Min Max Min Max Min Max A All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. Revision 1.1 Page 31

32 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Net tructure Routing for Address and Control (Raw Card Version B) A, BA, RA, CA, WE for Raw Card Version A DRAM DRAM TL4 DRAM DRAM TL2 TL1 TL4 DRAM DRAM DRAM DRAM DIMM Connector TL0 DRAM (ECC) DRAM DRAM TL1 TL4 DRAM DRAM TL2 DRAM DRAM TL4 DRAM DRAM DRAM (ECC) Trace Lengths for Address and Control Net tructures Raw Card TL0 TL1 TL2 TL4 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Notes B All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. Page 32 Revision 1.1

33 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 6. DIMM Wiring Details Net tructure Routing for Address and Control (Raw Card Version C) A, BA, RA, CA, WE for Raw Card Version A DIMM Connector TL0 R1 ± 5% TL1 TL2 (ECC) TL4 Trace Lengths for Address and Control Net tructures Raw Card TL0 TL1 TL0 + TL1 TL2 TL4 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max R1 Ohms Notes C All distances are given in inches and should be kept within a tolerance of ± 0.01 inches. 2. The total length of nets TL0 and TL1 must be within this limit. Revision 1.1 Page 33

34 6. DIMM Wiring Details PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Cross ection Recommendations The DIMM printed circuit board design uses six-layers of glass epoxy material. PCBs must contain full ground plane and full power plane layers. The PCB stackup must be designed with 4 mil wide traces. The voltage Layer 5 is tied to all VDD and VDDQ pins on the DIMM edge connector. Note: The PCB edge connector contacts shall be gold-plated and not chamfered. PCB Electrical pecifications Parameter Min Max Units Trace velocity: 0 (outer layers) ns/ft Trace velocity: 0 (inner layers) ns/ft Trace impedance: Z0 (all layers) Ohms Example Layer tackup for 4 mil Traces ignal Layer 1 ignal Layer 3 ignal Layer 4 ignal Layer 6 Ground Layer 2 Voltage Layer 5 Decoupling The common reference Gerbers available to this specification provide decoupling, local and distributed, for the DRAMs, signal returns, and EEPROMs. It is recommended that the location, number, and wiring for these decoupling capacitors not be changed from the reference Gerbers. Page 34 Revision 1.1

35 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 7. Design Target 7. Design Target The timing for Unbuffered DDR DIMMs is critical. The following analysis should be used in order to guarantee robustly operating DIMMs. Address setup/hold flight times ymbol Parameter Time (ns) et-up Time (ns) Hold Notes t CO Clock to output (open circuit).75ns -.75ns t PD Maximum time for the signal to propagate through the actual nets 4.6ns 1.05ns 1, 2 t KEW Clock jitter and skew of the DIMM, system board and clock buffer.425ns -.35ns t imultaneous witch adder.6ns NA 3 t I DRAM setup/hold 1ns.75ns (t IH ) Other brd x-talk,....1ns NA Total 7.475ns.7ns Note: 1. For set-up, 1V/ns driver, 22 ohm series R motherboard, 2 DIMM w/18 DRAMs each, 3" board trace lead-in, 60 ohm motherboard. 2. For hold, 1V/ns driver, 22 ohm series R motherboard, 1 DIMM w/4 DRAMs, 3" board trace lead-in, 60 ohm motherboard. 3. O + II (Intersymbol Interference) + other connector and board noise effects. Clock kew Contributions (t KEW ) t KEW for etup Units t KEW for Hold Units Buffer kew.15 ns Buffer kew.15 ns Board kew.10 ns Board kew.10 ns DIMM kew.10 ns DIMM kew.10 ns Jitter (Cyc - Cyc).075 ns Total.35 ns Total.425 ns Revision 1.1 Page 35

36 8. erial PD Definition PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 8. erial PD Definition The erial Presence Detect function MUT be implemented on the DDR DRAM Unbuffered DIMM. The component used and the data contents must adhere to the most recent version of the JEDEC DDR Module erial Presence Detect pecifications. Please refer to this document for all technical specifications and requirements of the erial Presence Detect devices (Refer to JEDEC ballot JC item 894A for PD field definitions). The following table is intended to be an example of the PD data for a 256MB (32M x 72), 184-pin unbuffered DRAM DDR DIMM using two physical banks of 16 Meg x 8 DDR200 devices with 12/10/2 addressing and CA latencies of 2 and 2.5. erial Presence Detect Example Raw Card Version B (Part 1 of 2) 32 Meg x 72 DDR Byte # Description PD Entry Value erial PD Data Entry Notes 0 Number of erial PD Bytes Written during Production Total number of bytes in erial PD Device Fundamental Memory Type DRAM DDR 07 3 Number of Row Addresses on Assembly 12 0C 4 Number of Column Addresses on Assembly 10 0A 5 Number of Physical Banks on DIMM Data Width of Assembly x Data Width of Assembly (continued) x Voltage Interface Level of this Assembly TL 2.5V 04 9 DRAM Device Cycle Time at Maximum CL (CLX = 2.5) 8.0ns DRAM Device Access Time from Clock at CL = 2.5 ±0.8ns DIMM Configuration Type ECC Refresh Rate/Type 15.6µs/R Primary DRAM Device Width x Error Checking DRAM Device Width x DRAM Device Attributes: Minimum Clock Delay, Random Column Access 1 Clock DRAM Device Attributes: Burst Lengths upported 2, 4, 8 0E 17 DRAM Device Attributes: Number of Device Banks DRAM Device Attributes: CA Latency 2, 2.5 0C 19 DRAM Device Attributes: C Latency DRAM Device Attributes: WE Latency DRAM Module Attributes Differential Clock DRAM Device Attributes: General VDD ±0.2V Minimum Clock Cycle at CLX-0.5 (CL = 2) 10.0ns A0 24 Maximum Data Access Time ( t AC) from Clock at CLX-0.5 (CL = 2) ±0.8ns Minimum Clock Cycle Time at CLX-1 (CL = 1.5) N/A 00 Page 36 Revision 1.1

37 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 8. erial PD Definition erial Presence Detect Example Raw Card Version B (Part 2 of 2) 32 Meg x 72 DDR Byte # Description PD Entry Value erial PD Data Entry Notes 26 Maximum Data Access Time ( t AC) from Clock at CLX-1 (CL = 1.5) N/A Minimum Row Precharge Time ( t RP) 20.0ns Minimum Row Active to Row Active Delay ( t RRD) 15.0ns 3C 29 Minimum RA to CA Delay ( t RCD) 20.0ns Minimum Active to Precharge Time ( t RA) 50.0ns Module Bank Density 128MB Address and Command etup Time before Clock 1.1ns B0 33 Address and Command Hold Time after Clock 1.1ns B0 34 Data/Data Mask Input etup Time before Clock 0.6ns Data/Data Mask Input Hold Time after Clock 0.6ns Reserved Undefined PD Revision Checksum for Bytes 0-62 Checksum Data cc Manufacturers JEDEC ID Code 72 Module Manufacturing Location Module Part Number Module Revision Code Module Manufacturing Date Year/Week Code yyww 2, Module erial Number erial Number ssssssss Reserved Undefined Open for Customer Use Undefined cc = Checksum Data byte, 00-FF (Hex). 2. ww = Binary coded decimal week code, (Decimal) (Hex). 3. yy = Binary coded decimal year code, (Decimal) (Hex). 4. ss = erial number data byte, 00-FF (Hex). 5. Unused bytes are set to the value "00". 6. Unused bits in attribute bytes are set to "0". erial Presence Detect Component pecification The DIMM vendor should ensure that the lower 128 bytes are software write protectable. A write to the PD with address " A2 A1 A0 0", where A(2:0) are the PD addresses on the DIMM connector, will prevent all future writes to the lower 128 bytes of the PD. The software write protect feature is "write once", but should be done by the BIO at each power up, to prevent corruption of the lower 128 bytes of the PD. Revision 1.1 Page 37

38 9. Product Label PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 9. Product Label The following label should be applied to all 184pin Unbuffered DDR DIMMs, to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A minimum font size of 8 points should be used, and the number can be printed in one or more rows on the label. Format: PCwwwwm-aabcd-ef Where: wwww: Module Bandwidth 1600: 1.6GB/sec 2100: 2.1GB/sec m: Module Type R = Registered DIMM U = Unbuffered DIMM (no registers on DIMM) aa: DRAM CA Latency, with no decimal point (25 = 2.5CK CA Latency) b: DRAM minimum t RCD specification (in clocks) c: DRAM minimum t RP specification (in clocks) d: JEDEC PD Revision used on this DIMM e: Gerber file used for this design (if applicable) A: Reference design for R/C "A" is used for this assembly B: Reference design for R/C "B" is used for this assembly C: Reference design for R/C "C" is used for this assembly Z: None of the "Reference" designs were used on this assembly f: Revision number of the reference design used: 1: 1st revision (1st release) 2: 2nd revision (2nd release) 3: 3rd revision (3rd release) Z: Not Applicable Note: The Gerber reference designs provide as foundations for a module PCB. Manufacturers may make minor modifications to aid in manufacturability but are discouraged from making electrical changes to the design. Example: PC1600U B1 is a PC1600 DDR Unbuffered DIMM with CL = 2.5 t RCD = 3, t RP = 3 using the latest JEDEC PD Revision 0.0 and produced based on the "B" raw card Gerber, 1st release. Page 38 Revision 1.1

39 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 10. DIMM Mechanical pecifications 10. DIMM Mechanical pecifications JEDEC has standardized detailed mechanical information for the 184 Pin DIMM family. This information can be accessed on the worldwide web as follows: 1. Go to 2. Click on Free tandards and Docs. 3. croll down and double click on Publication Under Outlines/Registrations, click on Microelectronics Outlines. 5. croll down and select MO-206 to download the PDF for this product family. implified Mechanical Drawing with Keying Positions FRONT N/A for x64 PD Voltage Key Note: The key timing in this example defines the DIMM as a 2.5V VDD/VDDQ DDR DIMM. *The key position defines the voltage for the DIMM: Center = 1.8 Volt VDDQ; Left = 2.5 Volt VDDQ; Right = 3.3 Volt VDDQ. Revision 1.1 Page 39

40 11. Clocking Timing Methodology PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 11. Clocking Timing Methodology The clock to DRAM delay is intended to be optimized for high speed operation, while permitting a variety of component layout options. This delay should be modeled by the module supplier, to ensure accuracy, if a raw card other than one of the "reference designs" is utilized. The clock proposed "Reference Net" below is provided for use during module simulation to ensure an accurate clock delay. Unbuffered DIMM Differential Clock Reference Net DIMM Conector CLK CLK 120Ω ± 5% Z 0 = 60.0 Ohms t 0 = 2.2ns/ft.367 Notes: 1. Capacitor value equals 1/2 the nominal DRAM input capacitance; 1.5pF ± 20%. 2. Lengths in inches. Page 40 Revision 1.1

41 PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification 12. Revision Log 12. Revision Log Revision Info Page of Revision Description of Change Revision 1.1 All Added PC1600/PC2100 to header Revision Changed Revision number and date Revision Renumbered and adjusted TOC titles Revision Adjusted Voltage Options Revision Updated VDD PD pin description Revision Updated VDD, VDD PD V function; added VDD PD row Revision Updated Pins 103 and 167 [JC ] Revision Corrected numbering on all I/Os on DRAMs Revision Added series resistors to the Ax, BAx, RA, CA, and W [JC ] Revision Reordered loads and updated note Revision Added pecification Revision and Raw Card C Applicable Gerber File [JC ] Revision Corrected dimensions on Raw Card C Revision Clarified ingle Bank DQ Topology; reworded title; adjusted Raw Card C TL0 Max and TL1 Min [JC ] Revision Removed 1 from Trace Lengths title Revision Added ECC to Net tructure Routing Diagrams Revision Added to bottom DRAM pin Revision Removed CKE1 from Trace Lengths title Revision Updated Raw Card C Trace Lengths [JC ] Revision Added Decoupling section Revision Corrected Byte # 24 Revision Updated Byte # 63 and added erial Presence Detect Component pecification paragraph Revision Clarified Note 1 definition of capacitance Revision 1.1 Page 41

42 12. Revision Log PC1600/PC2100 DDR DRAM Unbuffered DIMM Design pecification Page 42 Revision 1.1