DDR2 SDRAM UDIMM MT16HTF6464AY 512MB MT16HTF12864AY 1GB MT16HTF25664AY 2GB MT16HTF51264AY 4GB. Features
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1 DDR SDRAM UDMM MT6HTF6464AY 5MB MT6HTF864AY GB MT6HTF5664AY GB MT6HTF564AY 4GB 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Features Features 40-pin, unbuffered dual in-line memory module Fast data transfer rates: PC-8500, PC-6400, PC-5300, PC-400, or PC-300 5MB (64 Meg x 64), GB (8 Meg x 64), GB (56 Meg x 64), 4GB (5 Meg x 64) V DD = V D.8V V DDSPD =.7 3.6V JEDEC-standard.8V /O (SSTL_8-compatible) Differential data strobe (S, S#) option 4n-bit prefetch architecture Multiple internal device banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRTE latency = READ latency - t CK Programmable burst lengths (BL): 4 or 8 Adjustable data-output drive strength 64ms, 89-cycle refresh On-die termination (ODT) Serial presence detect (SPD) with EEPROM Gold edge contacts Dual rank Figure : 40-Pin UDMM (MO-37 R/C B and E) Module height: 30.0mm (.8in) Options Marking Operating temperature Commercial (0 C T A +70 C) None ndustrial ( 40 C T A +85 C) Package 40-pin DMM (lead-free) Y CL = 7 (DDR-066) 3 CL = 5 (DDR-800) CL = 6 (DDR-800) CL = 5 (DDR-667) -667 CL = 4 (DDR E CL = 3 (DDR-400) 5-40E Notes:. Contact Micron for industrial temperature module offerings.. CL = CAS (READ) latency. 3. Available only in GB, Rev. E devices. 4. Not available in 5MB, 4GB module density. 5. Not recommended for new designs. Table : Key Timing Parameters Speed Grade ndustry Nomenclature Data Rate (MT/s) CL = 7 CL = 6 CL = 5 CL = 4 CL = 3 -GA PC E PC PC PC E PC E PC t RCD (ns) t RP (ns) t RC (ns) htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.
2 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Features Table : Addressing Parameter 5MB GB GB 4GB Refresh count 8K 8K 8K 8K Row address 8K A[:0] 6K A[3:0] 6K A[3:0] 3K A[4:0] Device bank address 4 BA[:0] 4 BA[:0] 8 BA[:0] 8 BA[:0] Device configuration 56Mb (3 Meg x 8) 5Mb (64 Meg x 8) Gb (8 Meg x 8) Gb (56 Meg x 8) Column address K A[9:0] K A[9:0] K A[9:0] K A[9:0] Module rank address S#[:0] S#[:0] S#[:0] S#[:0] Table 3: Part Numbers and Timing Parameters 5MB Modules (End of Life) Base device: MT47H3M8, 56Mb DDR SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT6HTF6464A()Y-667 5MB 64 Meg x GB/s 3.0ns/667 MT/s MT6HTF6464A()Y-53E 5MB 64 Meg x GB/s 3.75ns/533 MT/s MT6HTF6464A()Y-40E 5MB 64 Meg x GB/s 5.0ns/400 MT/s Table 4: Part Numbers and Timing Parameters GB Modules Base device: MT47H64M8, 5Mb DDR SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT6HTF864A()Y-80E GB 8 Meg x GB/s.5ns/800 MT/s MT6HTF864A()Y-800 GB 8 Meg x GB/s.5ns/800 MT/s MT6HTF864A()Y-667 GB 8 Meg x GB/s 3.0ns/667 MT/s MT6HTF864A()Y-56E GB 8 Meg x GB/s 3.75ns/533 MT/s MT6HTF864A()Y-40E GB 8 Meg x GB/s 5.0ns/400 MT/s htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
![S#[:0] S#[:0] S#[:0] Table 3: Part Numbers and Timing Parameters 5MB Modules (End of Life) Base device: MT47H3M8, 56Mb DDR SDRAM Part Number Module Density Configuration Module Bandwidth Memory](/docs-images/46/21253001/images/page_2.jpg "Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT6HTF6464A()Y-667 5MB 64 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT6HTF6464A()Y-53E 5MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT6HTF6464A()Y-40E 5MB 64 Meg x 64 3.")
3 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Features Table 5: Part Numbers and Timing Parameters GB Modules Base device: MT47H8M8, Gb DDR SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT6HTF5664A()Y-80E GB 56 Meg x GB/s.5ns/800 MT/s MT6HTF5664A()Y-800 GB 56 Meg x GB/s.5ns/800 MT/s MT6HTF5664A()Y-667 GB 56 Meg x GB/s 3.0ns/667 MT/s MT6HTF5664A()Y-53E GB 56 Meg x GB/s 3.75ns/533 MT/s MT6HTF5664A()Y-40E GB 56 Meg x GB/s 5.0ns/400 MT/s Table 6: Part Numbers and Timing Parameters 4GB Modules Base device: MT47H56M8, Gb DDR SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT6HTF564A()Y-667 4GB 5 Meg x GB/s 3.0ns/667 MT/s MT6HTF564A()Y-53E 4GB 5 Meg x GB/s 3.75ns/533 MT/s Notes:. The data sheet for the base device can be found on Micron s Web site.. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT6HTF5664AY-667E. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 3 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
4 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Pin Assignments Pin Assignments Table 7: Pin Assignments 40-Pin UDMM Front 40-Pin UDMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol V REF A V D DM5 3 6 V D 9 S5# A3 NC A 93 S A V DD V DD DM0 55 DM3 85 CK S0# 36 S3# NC 56 NC 86 CK0# 6 7 S0 37 S3 67 V DD V DD NC A V DD V DD A BA 0 CK 4 7 BA0 0 SA 3 6 NC 9 V D CK# 8 4 NC 7 V D 0 NC NC 9 RAS# NC 73 WE# S0# 3 DM CAS# 04 S6# 34 DM 64 NC 94 V D 4 NC 5 S# 45 NC 75 V D 05 S6 35 NC 65 NC 95 ODT0 5 6 S 46 NC 76 S# NC/A ODT CK 67 NC 97 V DD NC 48 NC 78 V D CK# 68 NC NC 49 NC V D V D CKE CKE V DD 0 DM4 3 DM V DD 83 S4# 3 S7# NC 03 NC 33 NC NC/BA 84 S4 4 S NC/A NC V D V D DM 76 A S# 57 A NC 77 A S 58 A V DD V DDSPD 9 59 V DD SDA A SA A SCL A SA Notes:. Pin 54 is NC for 5MB and GB, or BA for GB and 4GB.. Pin 74 is NC for 5MB, GB, and GB, or A4 for 4GB. 3. Pin 96 is NC for 5MB, or A3 for GB, GB, and 4GB. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 4 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
5 Pin Descriptions Table 8: Pin Descriptions Symbol Type Description The pin description table below is a comprehensive list of all possible pins for all DDR modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Ax nput Address inputs: Provide the row address for ACTVE commands, and the column address and auto precharge bit (A0) for READ/WRTE commands, to select one location out of the memory array in the respective bank. A0 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A0 LOW, bank selected by BAx) or all banks (A0 HGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx nput Bank address inputs: Define the device bank to which an ACTVE, READ, WRTE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR, MR, and MR3) is loaded during the LOAD MODE command. CKx, CK#x nput Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx nput Clock enable: Enables (registered HGH) and disables (registered LOW) internal circuitry and clocks on the DDR SDRAM. DMx, nput Data mask (x8 devices only): DM is an input mask signal for write data. nput data is masked when DM is sampled HGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the and S pins. ODTx nput On-die termination: Enables (registered HGH) and disables (registered LOW) termination resistance internal to the DDR SDRAM. When enabled in normal operation, ODT is only applied to the following pins:, S, S#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_n nput Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# nput Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# nput Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and are High-Z. S#x nput Chip select: Enables (registered LOW) and disables (registered HGH) the command decoder. SAx nput Serial address inputs: Used to configure the SPD EEPROM address range on the C bus. SCL nput Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the C bus. CBx /O Check bits. Used for system error detection and correction. x /O Data input/output: Bidirectional data bus. Sx, S#x /O 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Pin Descriptions Data strobe: Travels with the and is used to capture at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. S# is only used when differential data strobe mode is enabled via the LOAD MODE command. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 5 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
6 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Pin Descriptions Table 8: Pin Descriptions (Continued) Symbol Type Description SDA /O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the C bus. RSx, RS#x Err_Out# Output Output (open drain) Redundant data strobe (x8 devices only): RS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RS is enabled, RS is output with read data only and is ignored during write data. When RS is disabled, RS becomes data mask (see DMx). RS# is only used when RS is enabled and differential data strobe mode is enabled. Parity error output: Parity error found on the command and address bus. V DD /V D Supply Power supply:.8v ±0.V. The component V DD and V D are connected to the module V DD. V DDSPD Supply SPD EEPROM power supply:.7 3.6V. V REF Supply Reference voltage: V DD /. Supply Ground. NC No connect: These pins are not connected on the module. NF No function: These pins are connected within the module, but provide no functionality. NU Not used: These pins are not used in specific module configurations/operations. RFU Reserved for future use. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 6 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
7 Functional Block Diagram 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Functional Block Diagram Figure : Functional Block Diagram (-GA, -80E, -800, -667, -53E, -40E) Raw Card E S# S0# S0# S0 DM0 S4# S4 DM4 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U U U5 U3 S# S DM S5# S5 DM5 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U U U6 U S# S DM S6# S6 DM6 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U3 U U7 U S3# S3 DM3 S7# S7 DM7 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U4 U U8 U0 U9 BA[:0] A[4:0] RAS# CAS# WE# BA[/:0]: DDR SDRAM A[4/3/:0]: DDR SDRAM RAS#: DDR SDRAM CAS#: DDR SDRAM WE#: DDR SDRAM SCL V DDSPD V DD /V D SPD EEPROM SDA WP A0 A A SA0 SA SA SPD EEPROM DDR SDRAM CK0 CK0# CK CK# U4, U5, U3, U4 U U3, U5 U7 CKE0 CKE CKE0: U U8 CKE: U0 U7 V REF DDR SDRAM DDR SDRAM, EEPROM CK CK# U6 U8, U0 U ODT0 ODT0: U U8 ODT ODT: U0 U7 htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 7 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
8 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Functional Block Diagram Figure 3: Functional Block Diagram (-53E, -40E) Raw Card B S# S0# S0# S0 DM0 S4# S4 DM4 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U U U6 U4 S# S DM S5# S5 DM5 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U U U7 U3 S# S DM S6# S6 DM6 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U3 U U8 U S3# S3 DM3 S7# S7 DM7 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U4 U U9 U BA[:0] A[3:0] RAS# CAS# WE# BA[/:0]: DDR SDRAM A[3/:0]: DDR SDRAM RAS#: DDR SDRAM CAS#: DDR SDRAM WE#: DDR SDRAM SCL U0 SPD EEPROM WP A0 A A SA0 SA SA SDA CK0 CK0# U4, U6, U4, U6 CKE0 CKE0: U U4, U6 U9 V DDSPD SPD EEPROM CK CK# U U3, U7 U9 CKE ODT0 CKE: U U4, U6 U9 ODT0: U U4, U6 U9 V DD /V D V REF DDR SDRAM DDR SDRAM DDR SDRAM, EEPROM CK CK# U7 U9, U U3 ODT ODT: U U4, U6 U9 htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 8 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
9 General Description DDR SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 4 or 8-bank DDR SDRAM devices. DDR SDRAM modules use DDR architecture to achieve high-speed operation. DDR architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the /O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the /O pins. DDR modules use two sets of differential signals: S, S# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. A bidirectional data strobe (S, S#) is transmitted externally, along with data, for use in data capture at the receiver. S is a strobe transmitted by the DDR SDRAM device during READs and by the memory controller during WRTEs. S is edge-aligned with data for READs and center-aligned with data for WRTEs. DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. nput data is registered on both edges of S, and output data is referenced to both edges of S, as well as to both edges of CK. Serial Presence-Detect EEPROM Operation 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM General Description DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 56-byte EEPROM. The first 8 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 8 bytes of storage are available for use by the customer. System READ/WRTE operations between the master (system logic) and the slave EEPROM device occur via a standard C bus using the DMM s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to, permanently disabling hardware write protection. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 9 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
10 Electrical Specifications Table 9: Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet are not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD /V D V DD /V D supply voltage relative to V V N, V OUT Voltage on any pin relative to V nput leakage current; Any input 0V V N V DD ; V REF input 0V V N 0.95V; (All other pins not under test = 0V) OZ Output leakage current; 0V V OUT ; and ODT are disabled Address inputs, RAS#, CAS#, WE#, BA µa S#, CKE, ODT CK0, CK0# 0 0 CK, CK#, CK, CK# DM 0 0, S, S# 0 0 µa VREF V REF leakage current; V REF = valid V REF level 3 3 µa T A Module ambient operating temperature Commercial 0 70 C T C 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Electrical Specifications ndustrial C DDR SDRAM component operating temperature Commercial 0 85 C ndustrial C Notes:. The refresh rate is required to double when T C exceeds 85 C.. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron s Web site. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 0 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
11 DRAM Operating Conditions 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DRAM Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades. Table 0: Module and Component Speed Grades DDR components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Design Considerations Component Speed Grade -GA -87E -80E -5E E -37E -40E -5E Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
12 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications DD Specifications Table : DDR DD Specifications and Conditions 5MB Values shown for MT47H3M8 DDR SDRAM only and are computed from values specified in the 56Mb (3 Meg x 8) component data sheet Parameter Symbol E -40E Units Operating one bank active-precharge current: t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching DD ma DD ma Operating one bank active-read-precharge current: OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data pattern is same as DD4W Precharge power-down current: All device banks idle; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[] = 0 Slow PDN exit MR[] = Active standby current: All device banks open; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK ( DD ); REFRESH command at every t RFC ( DD ) interval; CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.V; Other control and address bus inputs are floating; Data bus inputs are floating DDP ma DDQ ma DDN ma DD3P ma DD3N ma DD4W ma DD4R ma DD ma DD ma htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
13 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table : DDR DD Specifications and Conditions 5MB (Continued) Values shown for MT47H3M8 DDR SDRAM only and are computed from values specified in the 56Mb (3 Meg x 8) component data sheet Parameter Symbol E -40E Units Operating bank interleave read current: All device banks interleaving reads; OUT = 0mA; BL = 4, CL = CL ( DD ), AL = t RCD ( DD ) - t CK ( DD ); t CK = t CK ( DD ), t RC = t RC ( DD ), t RRD = t RRD ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching DD ma Notes:. Value calculated as one module rank in this operating condition; all other module ranks in DDP (CKE LOW) mode.. Value calculated reflects all module ranks in this operating condition. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 3 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
14 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table : DDR DD Specifications and Conditions GB Values shown for MT47H64M8 DDR SDRAM only and are computed from values specified in the 5Mb (64 Meg x 8) component data sheet Parameter Operating one bank active-precharge current: t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data pattern is same as DD4W Precharge power-down current: All device banks idle; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[] = 0 Slow PDN exit MR[] = Active standby current: All device banks open; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK ( DD ); REFRESH command at every t RFC ( DD ) interval; CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.V; Other control and address bus inputs are floating; Data bus inputs are floating Symbol -80E/ E -40E Units DD ma DD ma DDP ma DDQ ma DDN ma DD3P ma DD3N ma DD4W ma DD4R ma DD ma DD6 ma htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 4 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
15 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table : DDR DD Specifications and Conditions GB (Continued) Values shown for MT47H64M8 DDR SDRAM only and are computed from values specified in the 5Mb (64 Meg x 8) component data sheet Parameter Operating bank interleave read current: All device banks interleaving reads; OUT = 0mA; BL = 4, CL = CL ( DD ), AL = t RCD ( DD ) - t CK ( DD ); t CK = t CK ( DD ), t RC = t RC ( DD ), t RRD = t RRD ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Symbol -80E/ E -40E Units DD ma Notes:. Value calculated as one module rank in this operating condition; all other module ranks in DDP (CKE LOW) mode.. Value calculated reflects all module ranks in this operating condition. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 5 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
16 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table 3: DDR DD Specifications and Conditions (Die Revision A) GB Values shown for MT47H8M8 DDR SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Symbol E -40E Units Operating one bank active-precharge current: t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching DD ma DD ma Operating one bank active-read-precharge current: OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data pattern is same as DD4W Precharge power-down current: All device banks idle; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[] = 0 Slow PDN exit MR[] = Active standby current: All device banks open; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK ( DD ); REFRESH command at every t RFC ( DD ) interval; CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.V; Other control and address bus inputs are floating; Data bus inputs are floating DDP ma DDQ ma DDN ma DD3P ma DD3N ma DD4W ma DD4R ma DD ma DD6 ma htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 6 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
17 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table 3: DDR DD Specifications and Conditions (Die Revision A) GB (Continued) Values shown for MT47H8M8 DDR SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Symbol E -40E Units Operating bank interleave read current: All device banks interleaving reads; OUT = 0mA; BL = 4, CL = CL ( DD ), AL = t RCD ( DD ) - t CK ( DD ); t CK = t CK ( DD ), t RC = t RC ( DD ), t RRD = t RRD ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching DD ma Notes:. Value calculated as one module rank in this operating condition; all other module ranks in DDP (CKE LOW) mode.. Value calculated reflects all module ranks in this operating condition. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 7 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
18 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table 4: DDR DD Specifications and Conditions (Die Revision E) GB Values shown for MT47H8M8 DDR SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Operating one bank active-precharge current: t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data pattern is same as DD4W Precharge power-down current: All device banks idle; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[] = 0 Slow PDN exit MR[] = Active standby current: All device banks open; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK ( DD ); REFRESH command at every t RFC ( DD ) interval; CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.V; Other control and address bus inputs are floating; Data bus inputs are floating Symbol -GA -80E/ E -40E Units DD ma DD ma DDP ma DDQ ma DDN ma DD3P ma DD3N ma DD4W ma DD4R ma DD ma DD6 ma htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 8 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
19 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table 4: DDR DD Specifications and Conditions (Die Revision E) GB (Continued) Values shown for MT47H8M8 DDR SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Operating bank interleave read current: All device banks interleaving reads; OUT = 0mA; BL = 4, CL = CL ( DD ), AL = t RCD ( DD ) - t CK ( DD ); t CK = t CK ( DD ), t RC = t RC ( DD ), t RRD = t RRD ( DD ), t RCD = t RCD DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Symbol -GA -80E/ E -40E Units DD ma Notes:. Value calculated as one module rank in this operating condition; all other module ranks in DDP (CKE LOW) mode.. Value calculated reflects all module ranks in this operating condition. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 9 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
20 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table 5: DDR DD Specifications and Conditions 4GB Values shown for MT47H56M8 DDR SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol E Units Operating one bank active-precharge current: t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RC = t RC ( DD ), t RAS = t RAS MN ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address DD ma DD ma bus inputs are switching; Data pattern is same as DD4W Precharge power-down current: All device banks idle; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; t CK = t CK ( DD ); CKE is HGH, S# is HGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; t CK = t CK ( DD ); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[] = 0 Slow PDN exit MR[] = Active standby current: All device banks open; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read, OUT = 0mA; BL = 4, CL = CL ( DD ), AL = 0; t CK = t CK ( DD ), t RAS = t RAS MAX ( DD ), t RP = t RP ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: t CK = t CK ( DD ); REFRESH command at every t RFC ( DD ) interval; CKE is HGH, S# is HGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.V; Other control and address bus inputs are floating; Data bus inputs are floating DDP 8 8 ma DDQ ma DDN ma DD3P ma DD3N ma DD4W ma DD4R ma DD ma DD6 8 8 ma htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 0 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
21 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM DD Specifications Table 5: DDR DD Specifications and Conditions 4GB (Continued) Values shown for MT47H56M8 DDR SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol E Units Operating bank interleave read current: All device banks interleaving reads; OUT = 0mA; BL = 4, CL = CL ( DD ), AL = t RCD ( DD ) - t CK ( DD ); t CK = t CK ( DD ), t RC = t RC ( DD ), t RRD = t RRD ( DD ), t RCD = t RCD ( DD ); CKE is HGH, S# is HGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching DD ma Notes:. Value calculated as one module rank in this operating condition; all other module ranks in DDP (CKE LOW) mode.. Value calculated reflects all module ranks in this operating condition. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
22 Serial Presence-Detect Table 6: SPD EEPROM Operating Conditions 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD V nput high voltage: logic ; All inputs V H V DDSPD 0.7 V DDSPD V nput low voltage: logic 0; All inputs V L 0.6 V DDSPD 0.3 V Output low voltage: OUT = 3mA V OL 0.4 V nput leakage current: V N = GND to V DD L 0. 3 µa Output leakage current: V OUT = GND to V DD LO µa Standby current SB.6 4 µa Power supply current, READ: SCL clock frequency = 00 khz CCR 0.4 ma Power supply current, WRTE: SCL clock frequency = 00 khz CCW 3 ma Table 7: SPD EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid t AA µs Time bus must be free before a new transition can start t BUF.3 µs Data-out hold time t DH 00 ns SDA and SCL fall time t F 300 ns SDA and SCL rise time t R 300 ns Data-in hold time t HD:DAT 0 µs Start condition hold time t HD:STA 0.6 µs Clock HGH period t HGH 0.6 µs Noise suppression time constant at SCL, SDA inputs t 50 µs Clock LOW period t LOW.3 µs SCL clock frequency t SCL 400 khz Data-in setup time t SU:DAT 00 ns Start condition setup time t SU:STA 0.6 µs 3 Stop condition setup time t SU:STO 0.6 µs WRTE cycle time t WRC 0 ms 4 Notes:. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = and the falling or rising edge of SDA.. This parameter is sampled. 3. For a restart condition or following a WRTE cycle. 4. The SPD EEPROM WRTE cycle time ( t WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRTE cycle, the EEPROM bus interface circuit is disabled, SDA remains HGH due to pullup resistance, and the EEPROM does not respond to its slave address. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
23 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Module Dimensions Module Dimensions Figure 4: 40-Pin DDR UDMM (-GA, -80E, -800, -667, -53E, -40E) Raw Card E Front view (5.56) 33.0 (5.44) 4.0 (0.57) MAX.0 (0.079) R (4X) U U U3 U4 U5 U6 U7 U (.) 9.85 (.75).5 (0.098) D (X) U (0.7).3 (0.09). (0.087).0 (0.039) Pin.0 (0.039) (.78) 0.8 (0.03) 0.76 (0.03) R 0.0 (0.394) Pin 0.37 (0.054).7 (0.046) 3.0 (4.84) Back view U0 U U U3 U4 U5 U6 U (0.) Pin 40 Pin 5.0 (0.97) 55.0 (.65) 63.0 (.48) Notes:. All dimensions are in millimeters (inches); MAX/MN or typical () where noted.. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 3 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
24 5MB, GB, GB, 4GB (x64, DR) 40-Pin DDR UDMM Module Dimensions Figure 5: 40-Pin DDR UDMM (-53E, -40E) Raw Card B Front view (5.56) 33.0 (5.44) 4.0 (0.57) MAX.0 (0.079) R (4X) U U U3 U4 U6 U7 U8 U (.) 9.85 (.75).5 (0.098) D (X) U (0.7).3 (0.09). (0.087).0 (0.039) Pin.0 (0.039) (.78) 0.80 (0.03) 0.76 (0.030) R 0.0 (0.394) Pin 0.37 (0.054).7 (0.046) 3.0 (4.84) Back view U U U3 U4 U6 U7 U8 U (0.) Pin 40 Pin 5.0 (0.97) 55.0 (.65) 63.0 (.48) Notes:. All dimensions are in millimeters (inches); MAX/MN or typical () where noted.. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions S. Federal Way, P.O. Box 6, Boise, D , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, nc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. htf6c64_8_56x64ay.pdf - Rev. G 3/0 EN 4 Micron Technology, nc. reserves the right to change products or specifications without notice. 003 Micron Technology, nc. All rights reserved.
DDR2 SDRAM UDIMM MT18HTF6472AY 512MB MT18HTF12872AY 1GB MT18HTF25672AY 2GB MT18HTF51272AY 4GB. Features
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-80E PC2-6400 800 800 533 400 12.5 12.5 55-667 PC2-5300 667 533 400 15 15 55-53E PC2-4200 533 400 15 15 55
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