Standard: 64M x 8 (9 components)

Transcription

1 256MB - WD2RE256X09 512MB - WD2RE512X09 1GB - WD2RE01GX09 2GB - WD2RE02GH09 (Stacked, Preliminary*) DDR2-400, 533,667 One Rank, x Registered SDRAM DIMM Pb-free Features: 240-pin Registered ECC DDR2 SDRAM Dual-In-Line Memory Module for DDR2-400,533 and 667. JEDEC standard VDD=1.V (+/- 0.1V) power supply One rank 256MB, 512MB, 1GB, and 2GB Modules are built with 9 x DDR2 SDRAM devices in a FBGA 60, 6, or 92-ball Pb-Free package ECC error detection and correction Programmable CAS Latency of 3 and 4; Burst Length of 4 and Auto Refresh and Self Refresh Mode OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) SPD (Serial Presence Detect) with EEPROM All input/output are SSTL_1 compatible All contacts are gold plated One clock delay for register ROHS compliant Figure 1: Available profiles Standard: Low Profile (Preliminary): 1.11" 0.72" Description: The following specification covers the WD2RE256X09, WD2RE512X09, WD2RE01GX09, and WD2RE02GH09 family of One-Rank Registered ECC DDR2 modules using x FBGA SDRAMs. Please reference Figure 1 for available profiles and the product ordering guide for available options including speed grade and silicon manufacturer. Speed Grades: Speed Grade Data Rate (MHz) Clock/Data Rate Latency Module Speed CL3 CL4 CL5-400C ns/400MHz PC E ns/533MHz PC D 667 3ns/667MHz PC Address Summary Table: 256MB 512MB 1GB 2GB Module Configuration 32M x 72 64M x 72 12M x M x 72 Refresh k K K K Device Configuration 32M x (9 components) 64M x (9 components) 12M x (9 components) Row Addressing A0-A13 A0-A13 A0-A14 A0-A14 Column Addressing A0-A9 A0-A9 A0-A9 A0-A9 Module Rank M x (9 components) *Specifications are for reference purposes only and are subject to change by Wintec without notice. 1

2 One Rank, x Registered SDRAM DIMM Pb-free Pin Configuration: Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 11 VDDQ 211 DM5/DQS14 2 VSS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ2 12 A3 212 NC/DQS14# 3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 13 A1 213 VSS 4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 14 VDD 214 DQ46 5 VSS 35 VSS KEY 95 DQ DM0/DQS9 155 DM3/DQS12 KEY 215 DQ47 6 DQS0# 36 DQS3# 65 VSS 96 DQ NC/DQS9# 156 NC/DQS12# 15 CK0 216 VSS 7 DQS0 37 DQS3 66 VSS 97 VSS 127 VSS 157 VSS 16 CK0# 217 DQ52 VSS 3 VSS 67 VDD 9 DQ4 12 DQ6 15 DQ30 17 VDD 21 DQ53 9 DQ2 39 DQ26 6 NC 99 DQ DQ7 159 DQ31 1 A0 219 VSS 10 DQ3 40 DQ27 69 VDD 100 VSS 130 VSS 160 VSS 19 VDD 220 RFU 11 VSS 41 VSS 70 A10/AP 101 SA2 131 DQ CB4 190 BA1 221 RFU 12 DQ 42 CB0 71 BA0 102 NC,TEST DQ CB5 191 VDDQ 222 VSS 13 DQ9 43 CB1 72 VDDQ 103 VSS 133 VSS 163 VSS 192 RAS# 223 DM6/DQS15 14 VSS 44 VSS 73 WE# 104 DQS6# 134 DM1/DQS DM/DQS S0# 224 NC/DQS15# 15 DQS1# 45 DQS# 74 CAS# 105 DQS6 135 NC/DQS10# 165 NC/DQS17# 194 VDDQ 225 VSS 16 DQS1 46 DQS 75 VDDQ 106 VSS 136 VSS 166 VSS 195 ODT0 226 DQ54 17 VSS 47 VSS 76 S1# 107 DQ RFU 167 CB6 196 A DQ55 1 RESET# 4 CB2 77 ODT1 10 DQ51 13 RFU 16 CB7 197 VDD 22 VSS 19 NC 49 CB3 7 VDDQ 109 VSS 139 VSS 169 VSS 19 VSS 229 DQ60 20 VSS 50 VSS 79 VSS 110 DQ DQ VDDQ 199 DQ DQ61 21 DQ10 51 VDDQ 0 DQ DQ DQ CKE1 200 DQ VSS 22 DQ11 52 CKE0 1 DQ VSS 142 VSS 172 VDD 201 VSS 232 DM7/DQS16 23 VSS 53 VDD 2 VSS 113 DQS7# 143 DQ A DM4/DQS NC/DQS16# 24 DQ16 54 A16,BA2 3 DQS4# 114 DQS7 144 DQ A NC/DQS13# 234 VSS 25 DQ17 55 NC 4 DQS4 115 VSS 145 VSS 175 VDDQ 204 VSS 235 DQ62 26 VSS 56 VDDQ 5 VSS 116 DQ5 146 DM2/DQS A DQ3 236 DQ63 27 DQS2# 57 A11 6 DQ DQ NC/DQS11# 177 A9 206 DQ VSS 2 DQS2 5 A7 7 DQ35 11 VSS 14 VSS 17 VDD 207 VSS 23 VDDSPD 29 VSS 59 VDD VSS 119 SDA 149 DQ A 20 DQ SA0 30 DQ1 60 A5 9 DQ SCL 150 DQ23 10 A6 209 DQ SA1 90 DQ VSS NC - No Connect, RFU - Reserved for Future Use 1. The Test pin (Pin 102) is reserved for bus analysis and is not connected on normal memory modules 2. CKE1 and S1# pin are used for dual-rank Registered DIMM 3. A13 (Pin 196) is for 512MB and above DIMM. Pin Locations: Front View Pin Pin Back View 240-pin DIMM 2

3 One Rank, x Registered SDRAM DIMM Pb-free Functional Block Diagram: One Rank 32M x 72 (256MB), 64M x 72 (512MB), 12M x 72 (1GB), and 256M x 72 (2GB) DDR2 Registered SDRAM DIMM (x organization) RCS0# DQS0 DQS0# DM0/DQS9 DQS9# DQS4 DQS4# DM4/DQS13 DQS13# DQ[0:7] DQS1 DQS1# DM1/DQS10 DQS10# U0 DQ[32:39] DQS5 DQS5# DM5/DQS14 DQS14# U4 DQ[:15] DQS2 DQS2# DM2/DQS11 DQS11# U1 DQ[40:47] DQS6 DQS6# DM6/DQS15 DQS15# U5 DQ[16:23] DQS3 DQS3# DM3/DQS12 DQS12# U2 DQ[4:55] DQS7 DQS7# DM7/DQS16 DQS16# U6 DQ[24:31] DQS DQS# DM/DQS17 DQS17# CB[0:7] U3 U DQ[56:63] V DDSPD V DD /V DDQ V REF Vss U7 To SPD To U0 - U To U0 - U To U0 - U SERIAL PD BA0-BA1 A0-A13 RAS# CAS# WE# CKE0 ODT0 CS0#* RESET# R E G I S T E R RST# RBA0-RBA1 -> BA0-BA1 to U0 - U RA0-RA13 -> A0-A13 to U0 - U RRAS# -> RAS# to U0 - U RCAS# -> CAS# to U0 - U RWE# -> WE# to U0 - U RCKE0 -> CKE0 to U0 - U RODT0 -> ODT0 to U0 - U RS0# -> CS0# to U0 - U SCL CK0 CK0# RESET# A0 A1 A2 SA0 P L L SA1 SA2 SDA CK to U0 - U CK# to U0 - U CK to all registers CK# to all registers Note: 1. *) CS0# connects to DCS# of Register 1 and CSR# of Register 2; CSR# of Register 1 and DCS# of Register 2 connects to VDD 2. DQ/DM/DQS, address and control resistor values are 22 Ohms. 3

4 One Rank, x Registered SDRAM DIMM Pb-free Absolute Maximum Ratings: Exposure to stresses greater than these absolute maximum rating conditions for extended periods may affect reliability of the module. Symbol Parameter Min Max Units V DD V DD supply voltage relative to V SS V V DD Q V DD Q supply voltage relative to V SS V V DD L V DD L supply voltage relative to V SS V V IN, V OUT Voltage on any pin relative to V SS V T STG Storage temperature C T OPR Operating Temperature (Ambient) C T CASE DRAM Component Case Temperature C I IL Input Leakage Current; Any input 0V V IN 0.95V -5 5 µa I OL Output Leakage Current; 0V V OUT V DD Q; DQS and ODT are disabled -5 5 µa DC Operating Conditions: Parameter Symbol Min Nom Max Units Notes Supply Voltage V DD V 1 V DD L Supply Voltage V DD L V 4 I/O Supply Voltage V DD Q V 4 I/O Reference Voltage V REF 0.49 x V DD Q 0.50 x V DD Q 0.51 x V DD Q V 2 I/O Termination Voltage (system) V TT V REF - 40 V REF V REF + 40 mv 3 NOTE: 1. V DD and V DD Q must keep track of each other. V DD Q cannot exceed the value of V DD 2. V REF is expected to equal V DD Q/2 of the transmitting device and to track variations in the DC level of the same 3. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to V REF and must track variations in the DC level of V REF 4. V DD Q must tracks V DD ; and V DD L tracks V DD Input/Output Capacitance: V DD = +1.V ± 0.1V, V DD Q = +1.V ± 0.1V, V REF = V SS, f =100MHz, 0 C T CASE +5 C, V OUT (DC) = V DD Q/2 Parameter Symbol Min Max Units Input Capacitance: CK, CK CCK pf Delta Input Capacitance: CK, CK CDCK pf Input Capacitance: BA0, BA1, A0-A12, CS, RAS, CI pf CAS, WE, CKE, ODT Delta Input Capacitance: BA0, BA1, A0-A12, CS, CDI pf RAS, CAS, WE, CKE, ODT Input/Output Capacitance: DQs, DQS, DM, NF CIO pf Delta Input/Output Capacitance: DQs, DQS, DM, NF CDIO pf 4

5 Electrical Characteristics and AC Timings: DDR2-400, 533,667 One Rank, x Registered SDRAM DIMM Pb-free V DD = +1.V ± 0.1V, V DD Q = +1.V ± 0.1V, V REF = V SS, f =100MHz, 0 C T CASE +5 C, V OUT (DC) = V DD Q/2 Parameter Symbol -5 DDR DDR DDR2-667 Units MIN MAX MIN MIN MAX DQ output access time from CK/ CK tac ps DQS output access time from CK/ CK tdqsck ps CK high-level width tch tck CK low-level width tcl tck CK half period thp MIN - MIN - MIN - ps (tch, tcl) (tch, tcl) (tch, tcl) Clock cycle time tck CL=3 5,000,000 5,000 5,000,000 ps CL=4 5,000,000 3,750 3,750,000 ps CL=5 3,000,000 ps DQ and DM input hold time tdh ps DQ and DM input setup time tds ps Control & Address input pulse width for tipw tck each input DQ and DM input pulse width for each tdipw tck input Data-out high-impedance time from thz - tacmax - tacmax - tacmax ps CK/ CK Data-out low-impedance time from tlz tacmin tacmax tacmin tacmax tacmin tacmax ps CK/ CK DQS-DQ skew for DQS and associated DQ tdqsq ps signals Data hold skew factor tqhs ps Data output hold time from DQS tqh thptqhtqhtqhs - thp- - thp- ps Write command to 1 st DQS latching tdqss WL-0.25 WL+ WL- WL+ WL- WL+0. tck transition DQS input low/high pulse width tdqsl/h tck DQS falling edge to CK setup time tdss tck DQS falling edge hold time from CK tdsh tck Mode register set command cycle time tmrd tck Write preamble setup time twpres ps Write preamble twpre tck Write postamble twpst tck Read preamble trpre tck Read postamble trpst tck Active to Precharge command tras 45 70, , ,000 ns Active to Active command period trc ns Refresh to Refresh command interval trfc ns Active to Read/Write delay trcd ns Precharge command period trp ns 5

6 One Rank, x Registered SDRAM DIMM Pb-free V DD = +1.V ± 0.1V, V DD Q = +1.V ± 0.1V, V REF = V SS, f =100MHz, 0 C T CASE +5 C, V OUT (DC) = V DD Q/2 Parameter Symbol -5 DDR DDR DDR2-667 Units MIN MAX MIN MAX MIN MAX Active bank A to Active bank B command trrd ns CAS A to CAS B command period tccd tck Write recovery time twr ns Auto Precharge write recovery + Precharge tdal WR+tRP - WR+tRP - WR+tRP - tck time Internal Write to Read command delay twtr ns Internal Read to Precharge command delay trtp ns Exit precharge power down to any non-read txp tck command Exit Self-Refresh to Read command txsrd tck Exit Self-Refresh to non-read command txsnr trfc+10 - trfc+10 - trfc+10 - ns CKE minimum high and low pulse width tcke tck Average periodic refresh interval trefi µs OCD drive mode output delay toit ns CKE low to CK, CK uncertainty tdelay tis+tck - tis+tck - - tis+tck +tih +tih +tih ns Note: These parameters are applicable for all 3 chip manufacturers, Micron, Infineon, and Samsung. 6

7 One Rank, x Registered SDRAM DIMM Pb-free Physical Dimensions Standard: 1.11" Height DDR2 Registered DIMM One physical rank, 9 components x organised Pin BACK 5.250/(133.35±0.15) 0.106/(2.7) Max /(4.0) 5.171/(131.35) Register PLL 1.11/(30.0) 0.10/(2.54) 0.11/(3.0) Pin / 0.25/(6.35) / 120 (1.0) 0.050±0.004/ (1.27) 2.55/(64.77) (1.27±0.1) 1.95/(49.5) 5.014/(127.35) SIDE FRONT Note: 1. Dimensions are in inches/(mm) 2. Outline dimensions and tolerances are in accordance with the JEDEC standard 7

8 One Rank, x Registered SDRAM DIMM Pb-free Physical Dimensions Very Low Profile: 0.72" Height DDR2 Registered DIMM One physical rank, 9 components x organised Pin /(2.54) 0.11/(3.0) BACK 5.250/(133.35±0.15) PLL Pin /(6.35) / 0.05/ (1.0) (1.27) /(64.77) 1.95/(49.5) 5.014/(127.35) FRONT Register Preliminary 0.72/(1.29) 0.050±0.003/ (1.27±0.1) SIDE 0.157/ (4.0) Max Note: 1. Dimensions are in inches/(mm) 2. Outline dimensions and tolerances are in accordance with the JEDEC standard

9 Ordering Guide: DDR2-400, 533MHz, One-Rank x, Registered ECC DIMM DDR2-400, 533,667 One Rank, x Registered SDRAM DIMM Pb-free WD2RE256X09 WD2RE512X09 WD2RE01GX09 WD2RE02GH09 x yyyy(j) Zz Naming Guide: x: Profile (Blank) = Std. (1.1") V = VLP. (0.72") yyyy: Speed 400C = DDR2-400@CL3 533E = DDR2-533@CL4 (j): Option (Blank) = Std. Zz: DRAM/Die Q = Infineon P = Samsung H = Micron (Call for additional DRAM options and latest die-revision) Configuration/Availability: Density PT # Profile Speed DRAM/Die 256MB WD2RE256X09 (Std), V 400C, 533E 512MB WD2RE512X09 (Std), V 400C, 533E 1-GB WD2RE01GX09 (Std), V 400C, 533E 2-GB WD2RE02GH09 V 400C, 533E - - Zz Example: WD2RE02GH09-400C-QB 2GB DDR2-400 REG/ECC VLP 0.72 Infineon B-Die using 256Mx4 stacked to 256Mx Contact Us: Wintec Industries OEM Group 675 Sycamore Drive Milpitas, CA Ph: Fax: oemsales@wintecind.com 9

10 One Rank, x Registered SDRAM DIMM Pb-free Revision History: Revision 1.0 (December 2004) Initial Release Revision 1.1 (August 2005) ROHS version Added DRAM Case temperature T CASE Revision 1.2 (June 2007) Added 667MHz speed grade 10