DDR2 SDRAM Unbuffered DIMM MT9HTF3272A 256MB MT9HTF6472A 512MB MT9HTF12872A 1GB

Transcription

1 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Features DDR2 SDRAM Unbuffered DIMM MT9HTF3272A 256MB MT9HTF6472A 52MB MT9HTF2872A GB For the latest data sheet, please refer to the Micron Web site: Features 24-pin, unbuffered dual in-line memory module (UDIMM) Fast data transfer rates: PC2-32, PC2-42, or PC MB (32 Meg x 72), 52MB (64 Meg x 72) GB (28 Meg x 72) VDD = VD = +.8V VDDSPD = +.7V to +3.6V JEDEC standard.8v I/O (SSTL_8-compatible) Differential data strobe (S, S#) option Four-bit prefetch architecture DLL to align and S transitions with CK Multiple internal device banks for concurrent operation Programmable CAS# latency (CL) Posted CAS# additive latency (AL) WRITE latency = READ latency - t CK Programmable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8,92-cycle refresh On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Gold edge contacts Single rank Figure : Height.8in. (29.97mm) Options 24-Pin DIMM (MO-237 R/C A ) Notes:. CL = CAS (READ) Latency. 2. Not available in GB density. Marking Package 24-pin DIMM (lead-free) Y Frequency/CAS Latency CL = 5 (DDR2-667) CL = 4 (DDR2-533) -53E CL = 3 (DDR2-4) -4E PCB Height.8in. (29.97mm) pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_.fm - Rev. C 6/5 EN 23, 24, 25 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

2 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Features Table : Address Table 256MB 52MB GB Refresh Count 8K 8K 8K Row Addressing 8K (A A2) 6K (A A3) 6K (A A3) Device Bank Addressing 4 (BA, BA) 4 (BA, BA) 8 (BA, BA, BA2) Device Page Size per Bank KB KB KB Device Configuration 256Mb (32 Meg x 8) 52Mb (64 Meg x 8) Gb (28 Meg x 8) Column Addressing K (A A9) K (A-A9) K (A-A9) Module Rank Addressing (S#) (S#) (S#) Table 2: Key Timing Parameters Speed Grade Data Rate (MT/s) CL = 3 CL = 4 CL = E E t RCD (ns) t RP (ns) t RC (ns) Table 3: Part Numbers and Timing Parameters Part Number Module Densit Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - t RCD - t RP) MT9HTF3272AY MB 32 Meg x GB/s 3.ns/667 MT/s MT9HTF3272AY-53E 256MB 32 Meg x GB/s 3.75ns/533 MT/s MT9HTF3272AY-4E 256MB 32 Meg x GB/s 5.ns/4 MT/s MT9HTF6472AY MB 64 Meg x GB/s 3.ns/667 MT/s MT9HTF6472AY-53E 52MB 64 Meg x GB/s 3.75ns/533 MT/s MT9HTF6472AY-4E 52MB 64 Meg x GB/s 5.ns/4 MT/s MT9HTF2872AY-667 GB 28 Meg x GB/s 3.ns/667 MT/s MT9HTF2872AY-53E GB 28 Meg x GB/s 3.75ns/533 MT/s MT9HTF2872AY-4E GB 28 Meg x GB/s 5.ns/4 MT/s Notes:. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9HTF6472AY-4EC2. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_.fm - Rev. C 6/5 EN 2 23, 24, 25 Micron Technology, Inc. All rights reserved.

3 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Table of Contents Table of Contents Features Table of Contents List of Figures List of Tables Pin Assignments and Descriptions Functional Block Diagram General Description Serial Presence-Detect Operation Initialization Mode Register (MR) Burst Length Burst Type Operating Mode DLL Reset Write Recovery Power-Down Mode CAS Latency (CL) Extended Mode Register (EMR) DLL Enable/Disable Output Drive Strength S# Enable/Disable RS Enable/Disable Output Enable/Disable On Die Termination (ODT) Off-Chip Driver (OCD) Impedance Calibration Posted CAS Additive Latency (AL) Extended Mode Register 2 (EMR2) Extended Mode Register 3 (EMR3) Command Truth Tables Absolute Maximum Ratings DC Operating Specifications Input Electrical Characteristics and Operating Conditions IDD Specifications and Conditions IDD7 Conditions Capacitance AC Timing and Operating Conditions Notes Serial Presence-Detect SPD Clock and Data Conventions SPD Start Condition SPD Stop Condition SPD Acknowledge Module Dimensions Data Sheet Designation Revision History pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AGTOC.fm - Rev. C 6/5 EN 3 23, 24, 25 Micron Technology, Inc. All rights reserved.

4 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM List of Figures List of Figures Figure : 24-Pin DIMM (MO-237 R/C A ) Figure 2: Pin Locations Figure 3: Functional Block Diagram Figure 4: DDR2 Power-Up and Initialization Figure 5: Mode Register (MR) Definition Figure 6: CAS Latency (CL) Figure 7: Extended Mode Register Definition Figure 8: READ Latency Figure 9: Write Latency Figure : Extended Mode Register 2 (EMR2) Definition Figure : Extended Mode Register 3 (EMR3) Definition Figure 2: Data Validity Figure 3: Definition of Start and Stop Figure 4: Acknowledge Response From Receiver Figure 5: SPD EEPROM Timing Diagram Figure 6: 24-pin DIMM DDR2 Module Dimensions pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AGLOF.fm - Rev. C 6/5 EN 4 23, 24, 25 Micron Technology, Inc. All rights reserved.

5 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM List of Tables List of Tables Table : Address Table Table 2: Key Timing Parameters Table 3: Part Numbers and Timing Parameters Table 4: Pin Assignment Table 5: Pin Descriptions Table 6: Burst Definition Table 7: Commands Truth Table Table 8: Absolute Maximum DC Ratings Table 9: Recommended DC Operating Conditions Table : Input DC Logic Levels Table : Inpu Logic Levels Table 2: General IDD Parameters Table 3: IDD7 Timing Patterns 256MB and 52MB Table 4: IDD7 Timing Patterns GB Table 5: DDR2 IDD Specifications and Conditions 256MB Table 6: DDR2 IDD Specifications and Conditions 52MB Table 7: DDR2 IDD Specifications and Conditions GB Table 8: AC Operating Conditions Table 9: EEPROM Device Select Code Table 2: EEPROM Operating Modes Table 2: Serial Presence-Detect EEPROM DC Operating Conditions Table 22: Serial Presence-Detect EEPROM AC Operating Conditions Table 23: Serial Presence-Detect Matrix pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AGLOT.fm - Rev. C 6/5 EN 5 23, 24, 25 Micron Technology, Inc. All rights reserved.

6 Pin Assignments and Descriptions 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 4: Pin Assignment 24-Pin DIMM Front 24-Pin DIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol VREF A4 9 VSS 2 VSS 5 VSS 8 VD 2 DM5 2 VSS 32 VSS 62 VD 92 S5# A3 22 NC A2 93 S A 23 VSS VDD 94 VSS 24 VSS 54 VSS 84 VDD VSS 35 VSS 65 VSS DM 55 DM3 85 CK S# 36 S3# 66 VSS NC 56 NC 86 CK# 26 VSS 7 S 37 S3 67 VDD 97 VSS 27 VSS 57 VSS 87 VDD VSS 38 VSS 68 NC A VDD VDD 29 VSS A/AP VSS 3 VSS 6 VSS 9 BA 22 RFU VSS 4 VSS 7 BA SA CB4 9 VD 22 RFU CB 72 VD 2 NC CB5 92 RAS# 222 VSS CB 73 WE# 3 VSS 33 VSS 63 VSS 93 S# 223 DM6 4 VSS 44 VSS 74 CAS# 4 S6# 34 DM 64 DM8 94 VD 224 NC 5 S# 45 S8# 75 VD 5 S6 35 NC 65 NC 95 ODT 225 VSS 6 S 46 S8 76 NC 6 VSS 36 VSS 66 VSS 96 NC/A VSS 47 VSS 77 NC RFU 67 CB6 97 VDD NC 48 CB2 78 VD RFU 68 CB7 98 VSS 228 VSS 9 NC 49 CB3 79 VSS 9 VSS 39 VSS 69 VSS VSS 5 VSS VD VD NC 2 VSS 23 VSS CKE 82 VSS 2 VSS 42 VSS 72 VDD 22 DM4 232 DM7 23 VSS 53 VDD 83 S4# 3 S7# NC 23 NC 233 NC NC/BA2 84 S4 4 S NC 24 VSS 234 VSS NC 85 VSS 5 VSS 45 VSS 75 VD VSS 56 VD DM2 76 A S2# 57 A NC 77 A9 27 VSS 237 VSS 28 S2 58 A7 88 VSS 8 VSS 48 VSS 78 VDD VDDSPD 29 VSS 59 VDD SDA A SA A SCL A6 2 VSS 24 SA Note: Pin 96 is NC for 256MB, or A3 for 52MB and GB; pin 54 is NC for 256MB and 52MB, or BA2 for GB. Figure 2: Pin Locations Front View Back View U U2 U3 U4 U5 U6 U7 U8 U9 No Components This Side of Module U PIN PIN 64 PIN 65 PIN 2 PIN 24 PIN 85 PIN 84 PIN 2 Indicates a VDD or VD pin Indicates a VSS pin pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 6 23, 24, 25 Micron Technology, Inc. All rights reserved.

7 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information Pin Numbers Symbol Type Description 95 ODT Input On-Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins:, S, S#, CB, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. 37, 38, 85, 86, 22, 22 CK, CK#, CK, CK#, CK2, CK2# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (s and S/S#) is referenced to the crossings of CK and CK#. 52 CKE Input Clock Enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER- DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry, POWER-DOWN exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_8 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After Vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh operation VREF must be maintained to this input. 93 S# Input Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. 73, 74, 92 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 54 (GB), 7, 9 BA, BA, BA2 (GB) 57, 58, 6, 6, 63, 7, 76, 77, 79, 8, 82, 83, 88, 96 (GB) 25, 34, 46, 55, 64, 22, 2, 223, 232 A A2 (256MB) A A3 (52MB, GB) Input Input Bank Address Inputs: BA BA/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA BA/BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A) for Read/ Write commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A LOW, device bank selected by BA BA/BA2) or all device banks (A HIGH). The address inputs also provide the op-code during a LOAD MODE command. DM DM8 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of S. Although DM pins are input-only, the DM loading is designed to match that of and S pins. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 7 23, 24, 25 Micron Technology, Inc. All rights reserved.

8 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information Pin Numbers Symbol Type Description 3, 4, 9,, 2, 3, 2, 22, 24, 25, 3, 3, 33, 34, 39, 4, 8, 8, 86, 87, 89, 9, 95, 96, 98, 99, 7, 8,,, 6, 7, 22, 23, 28, 29, 3, 32, 4, 4, 43, 44, 49, 5, 52, 53, 58, 59, 99, 2, 25, 26, 28, 29, 24, 25, 27, 28, 226, 227, 229, 23, 235, 236 6, 7, 5, 6, 27, 28, 36, 37, 45, 46, 83, 84, 92, 93, 4, 5, 3, 4 63 I/O Data Input/Output: Bidirectional data bus. S S8, S# S8# I/O Data Strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. S# is only used when differential data strobe mode is enabled via the LOAD MODE command. 42, 43, 48, 49, 6, 62, CB CB7 I/O Check Bits. 67, 68 2 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module., 239, 24 SA SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 9 SDA Input/ Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. 53, 59, 64, 67, 69, 72, 78, VDD Supply Power Supply: +.8V ±.V. 84, 87, 89, 97, 5, 56, 62, 72, 75, 78, 7, VD Supply Power Supply: +.8V ±.V. 75, 8, 9, 94, VREF Supply SSTL_8 reference voltage. 2, 5, 8,, 4, 7, 2, 23, 26, VSS Supply Ground. 29, 32, 35, 38, 4, 44, 47, 5, 65, 66, 79, 82, 85, 88, 9, 94, 97,, 3, 6, 9,2, 5, 8, 2, 24, 27, 3, 33, 36, 39, 42, 45, 48, 5, 54, 57, 6, 63, 66, 69, 98, 2, 24, 27, 2, 23, 26, 29, 222, 225, 228, 23, 234, VDDSPD Supply Serial EEPROM positive power supply: +.7V to +3.6V. 8, 9, 42, 43, 48, 49, 54 (256MB, 52MB), 55, 68, 76, 77, 2, 26, 35, 47, 56, 6, 62, 65, 67, 68, 7, 96 (256MB), 73, 74, 23, 22, 224, 233 NC No Connect: These pins should be left unconnected. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 8 23, 24, 25 Micron Technology, Inc. All rights reserved.

9 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Functional Block Diagram Functional Block Diagram Unless otherwise noted, resistor values are 22Ω. Micron module part numbers are explained in the Module Part Numbering Guide a Modules use the following DDR2 SDRAM devices: MT47H32M8BP (256MB); MT47H64M8BT (52MB); and MT47H28M8BT (GB). Figure 3: Functional Block Diagram S# 24pF S# S DM S# S DM S2# S2 DM2 S3# S3 DM3 S8# S8 DM CB CB CB2 CB3 CB4 CB5 CB6 CB7 DM CS# S# U DM CS# S# U2 DM CS# S# U3 DM CS# S# U4 DM CS# S# U5 SCL CK CK# 67Ω 3pF S4# S4 DM4 S5# S5 DM5 S6# S6 DM6 S7# S7 DM7 U Serial PD WP A A A2 SA SA SA DDR SDRAM X 3 SDA CK CK# CK2 CK2# DM DM DM DM 67Ω 3pF 67Ω 3pF CS# S# U6 CS# S# U7 CS# S# U8 CS# S# U9 DDR SDRAM X 3 DDR SDRAM X 3 BA-BA/BA2 A-A2/A3 RAS# CAS# WE# CKE ODT 5. 24pF 24pF BA-BA/BA2: DDR2 SDRAMs A-A2/A3: DDR2 SDRAMs RAS#: DDR2 SDRAMs CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE: DDR2 SDRAMs ODT: DDR2 SDRAMs VDDSPD VDD VD VREF VSS Serial PD DDR2 SDRAMS DDR2 SDRAMS DDR2 SDRAMS DDR2 SDRAMS pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 9 23, 24, 25 Micron Technology, Inc. All rights reserved.

10 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM General Description General Description The MT9HTF3272A, MT9HTF6472A, and MT9HTF2872A DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 256MB, 52MB, and GB memory modules organized in x64 configuration. DDR2 SDRAM modules use internally configured quadbank (256MB, 52MB) or eight-bank (GB) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (S, S#) is transmitted externally, along with data, for use in data capture at the receiver. S is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. S is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of S, and output data is referenced to both edges of S, as well as to both edges of CK. Read and write accesses to DDR2 SDRAM modules are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting column location for the burst access. DDR2 SDRAM modules provide for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM devices support interrupting a burst read of eight with another read, or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR2 SDRAM devices allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_8. All full drive-strength outputs are SSTL_8-compatible. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,48-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 28 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 28 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I 2 C bus using the DIMM s SCL (clock) and SDA (data) signals, together with SA (2:), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 23, 24, 25 Micron Technology, Inc. All rights reserved.

11 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Initialization Initialization The following sequence is required for power-up and initialization and is shown in Figure 4, DDR2 Power-Up and Initialization, on page 2.. Apply power; if CKE is maintained below 2 percent of VD, outputs remain disabled. To guarantee RTT (ODT Resistance) is off, VREF must be valid and a low level must be applied to the ODT pin (all other inputs may be undefined). The time from when VDD first starts to power-up to the completion of VD must be equal to or less than 2ms. At least one of the following two sets of conditions (A or B) must be met: A. CONDITION SET A VDD, VDDL and VD are driven from a single power converter output VTT is limited to.95v MAX VREF tracks VD/2 B. CONDITION SET B Apply VDD before or at the same time as VDDL. Apply VDDL before or at the same time as VD Apply VD before or at the same time as VTT and VREF 3. The voltage difference between any VDD supply can not exceed.3v. For a minimum of 2µs after stable power and clock (CK, CK#), apply NOP or DESELECT commands and take CKE HIGH 4. Wait a minimum of 4ns, then issue a PRECHARGE ALL command. 5. Issue a LOAD MODE command to the EMR(2) register. (To issue an EMR(2) command, provide LOW to BA and BA2, provide HIGH to BA.) 6. Issue a LOAD MODE command to the EMR(3) register. (To issue an EMR(3) command, provide HIGH to BA and BA, provide LOW to BA2.) 7. Issue a LOAD MODE command to the EMR register to enable DLL. To issue a DLL ENABLE command, provide LOW to BA, BA2, and A, provide HIGH to BA. Bits E7, E8, and E9 must all be set to. 8. Issue a LOAD MODE command for DLL Reset. 2 cycles of clock input is required to lock the DLL. (To issue a DLL Reset, provide HIGH to A8 and provide LOW to BA2, BA and BA.) CKE must be HIGH the entire time. 9. Issue PRECHARGE ALL command.. Issue two or more REFRESH commands.. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program operating parameters without resetting the DLL). 2. Issue a LOAD MODE command to the EMR to enable OCD default by setting Bits E7, E8, and E9 to and set all other desired parameters. 3. Issue a LOAD MODE command to the EMR to enable OCD exit by setting Bits E7, E8, and E9 to and set all other desired parameters. The DDR2 SDRAM device is now intialized and ready for normal operation 2 clocks after DLL Reset in step 8. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 23, 24, 25 Micron Technology, Inc. All rights reserved.

12 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Initialization Figure 4: DDR2 Power-Up and Initialization VDD VDDL VD tvtd VTT VREF CK# T t CK Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm CK CKE LVCMOS LOW LEVEL 8 t CL t CL SSTL_8 LOW LEVEL 8 See note 3 ODT COMMAND NOP 2 PRE LM LM LM LM PRE REF REF LM LM LM VALID 3 DM 7 ADDRESS 9 A = CODE CODE A = CODE CODE CODE CODE CODE VALID S 7 7 High-Z High-Z Rtt High-Z DON T CARE T = 2µs (min) Power-up: VDD and stable clock (CK, CK#) Indicates a break in time scale T = 4ns (min) t RPA EMR(2) t MRD t MRD t MRD t MRD trpa t RFC t RFC See note 4 EMR(3) EMR with DLL Enable 5 MR with DLL Reset 2 cycles of CK 3 MR w/o DLL Reset t MRD t MRD t MRD EMR with OCD Default EMR with OCD Exit Normal Operation Notes:. VTT is not applied directly to the device; however, t VTD should be greater than or equal to zero to avoid device latch-up. The time from when VDD first starts to power-up to the completion of VD must be equal to or less than 2ms. One of the following two conditions (a or b) MUST be met: A. VDD, VDDL, and VD are driven from a single power converter output. VTT may be.95v maximum during power up. VREF tracks VD/2. B. Apply VDD before or at the same time as VDDL. Apply VDDL before or at the same time as VD. 2. Apply VD before or at the same time as VTT and VREF. The voltage difference between any VDD supply can not exceed.3v. 3. Either a NOP or DESELECT command may be applied cycles of clock (CK, CK#) are required before a READ command can be issued. CKE must be HIGH the entire time. 5. Two or more REFRESH commands are required. 6. Bits E7, E8, and E9 must all be set to with all other operating parameters of EMRS set as required. 7. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address. 8. DM represents all DM. S represents all S, S#, RS,and RS# (RS/RS# only functional on RDIMMs using x8 components). represents all. 9. CKE pin uses LVCMOS input levels prior to state T. After state T, CKE pin uses SSTL_8 input levels.. A should be HIGH at states Tb and Tg to ensure a PRECHARGE (all banks) command is issued.. Bits E7, E8, and E9 must be set to to set OCD default. 2. Bits E7, E8, and E9 must be set to to set OCD exit and all other operating parameters of EMRS set as required. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 2 23, 24, 25 Micron Technology, Inc. All rights reserved.

13 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Mode Register (MR) Mode Register (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM device. This definition includes the selection of a burst length, burst type, CAS latency, operating mode, DLL reset, write recovery, and power-down mode as shown in Figure 5, Mode Register (MR) Definition. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M M4) must be programmed when the LOAD MODE command is issued. The mode register is programmed via the LM command (bits BA BA/BA2 all = ) and other bits (M M3 or M M4) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The LOAD MODE command can only be issued (or reissued) when all banks are in the precharged state. The controller must wait the specified time t MRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. Burst Length Burst Type Burst length is defined by bits M M2 as shown in Figure 5, Mode Register (MR) Definition. Read and write accesses to the DDR2 SDRAM device are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2 Ai when the burst length is set to four and by A3 Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3 as shown in Figure 5, Mode Register (MR) Definition. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in Table 6, Burst Definition, on page 5. DDR2 SDRAM devices support 4-bit burst and 8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 3 23, 24, 25 Micron Technology, Inc. All rights reserved.

14 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Mode Register (MR) Figure 5: Mode Register (MR) Definition 256MB Address Bus BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus 4 3 MR 2 PD WR DLL TM CAS# Latency BT Burst Length Mode Register (Mx) 52MB Address Bus BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus 5 4 MR 3 * 2 PD WR DLL TM CAS# Latency BT Burst Length Mode Register (Mx) GB Address Bus BA2 BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus 6 * 5 4 MR 3 * 2 PD WR DLL TM CAS# Latency BT Burst Length Mode Register (Mx) M2 PD mode Fast Exit (Normal) Slow Exit (Low Power) M8 M7 Mode Normal Test DLL Reset No Yes M M M9 WRITE RECOVERY Reserved 2 M Reserved M6 M5 M4 Reserved M5 M4 Mode Register Definition Mode Register (MR) Extended Mode Register (EMR) Extended Mode Register (EMR2) Extended Mode Register (EMR3) M2 M M Burst Length Reserved Reserved 4 8 Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved CAS Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 4 23, 24, 25 Micron Technology, Inc. All rights reserved.

15 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Mode Register (MR) Table 6: Burst Definition Starting Column Order of Accesses Within a Burst Burst Length Address (A2, A, A) Burst Type = Sequential Burst Type = Interleaved 4,,2,3,,2,3,2,3,,,3,2 2,3,, 2,3,, 3,,,2 3,2,, 8,,2,3,4,5,6,7,,2,3,4,5,6,7,2,3,,5,6,7,4,,3,2,5,4,7,6 2,3,,,6,7,4,5 2,3,,,6,7,4,5 3,,,2,7,4,5,6 3,2,,,7,6,5,4 4,5,6,7,,,2,3 4,5,6,7,,,2,3 5,6,7,4,,2,3, 5,4,7,6,,,3,2 6,7,4,5,2,3,, 6,7,4,5,2,3,, 7,4,5,6,3,,,2 7,6,5,4,3,2,, Operating Mode DLL Reset Write Recovery The normal operating mode is selected by issuing a LOAD MODE command with bit M7 set to zero, and all other bits set to the desired values as shown in Figure 5, Mode Register (MR) Definition, on page 4. When bit M7 is, no other bits of the mode register are programmed. Programming bit M7 to places the DDR2 SDRAM device into a test mode that is only used by the Manufacturer and should NOT be used. No operation or functionality is guaranteed if M7 bit is. DLL reset is defined by bit M8 as shown in Figure 5, Mode Register (MR) Definition, on page 4. Programming bit M8 to will activate the DLL RESET function. Bit M8 is selfclearing, meaning it returns back to a value of after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 2 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the or t SCK parameters. Write recovery (WR) time is defined by bits M9 M as shown in Figure 5, Mode Register (MR) Definition, on page 4. The WR Register is used by the DDR2 SDRAM device during WRITE with AUTO PRECHARGE operation. During WRITE with AUTO PRECHARGE operation, the DDR2 SDRAM device delays the internal AUTO PRECHARGE operation by WR clocks (programmed in bits M9 M) from the last data burst. Write Recovery (WR) values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9 M. The user is required to program the value of write recovery, which is calculated by dividing t WR (in ns) by t CK (in ns) and rounding up a noninteger value to the next integer; WR [cycles] = t WR [ns] / t CK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 5 23, 24, 25 Micron Technology, Inc. All rights reserved.

16 Power-Down Mode 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Mode Register (MR) Active power-down (PD) mode is defined by bit M2 as shown in Figure 5, Mode Register (MR) Definition, on page 4. PD mode allows the user to determine the active powerdown mode, which determines performance vs. power savings. PD mode bit M2 does not apply to precharge power-down mode. When bit M2 =, standard Active Power-down mode or fast-exit active power-down mode is enabled. The t XARD parameter is used for fast-exit active power-down exit timing. The DLL is expected to be enabled and running during this mode. When bit M2 =, a lower power active power-down mode or slow-exit active powerdown mode is enabled. The t XARDS parameter is used for slow-exit active power-down exit timing. The DLL can be enabled, but frozen during active power-down mode since the exit-to-read command timing is relaxed. The power difference expected between PD normal and PD low-power mode is defined in the IDD table. CAS Latency (CL) The CAS Latency (CL) is defined by bits M4 M6 as shown in Figure 5, Mode Register (MR) Definition, on page 4. CAS Latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CAS Latency can be set to 3, 4, or 5 clocks. CAS Latency of 2 clocks is a JEDEC optional feature and may be enabled in future speed grades. DDR2 SDRAM devices do not support any half clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DDR2 SDRAM devices also support a feature called Posted CAS additive latency (AL). This feature allows the READ command to be issued prior to t RCD(MIN) by delaying the internal command to the DDR2 SDRAM device by AL clocks. The AL feature is described in more detail in the Extended Mode Register (EMR) and Operational sections. Examples of CL = 3 and CL = 4 are shown in Figure 6, CAS Latency (CL); both assume AL =. If a READ command is registered at clock edge n, and the CAS Latency is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes AL = ). pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 6 23, 24, 25 Micron Technology, Inc. All rights reserved.

17 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Mode Register (MR) Figure 6: CAS Latency (CL) CK# T T T2 T3 T4 T5 T6 CK COMMAND READ NOP NOP NOP NOP NOP NOP S, S# CL = 3 (AL = ) DOUT n DOUT n + DOUT n + 2 DOUT n + 3 CK# T T T2 T3 T4 T5 T6 CK COMMAND READ NOP NOP NOP NOP NOP NOP S, S# CL = 4 (AL = ) DOUT n DOUT n + DOUT n + 2 DOUT n + 3 Burst length = 4 Posted CAS# additive latency (AL) = Shown with nominal tac, tsck, and tsq TRANSITIONING DATA DON T CARE pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 7 23, 24, 25 Micron Technology, Inc. All rights reserved.

18 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Extended Mode Register (EMR) Extended Mode Register (EMR) The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, ODT (RTT), Posted CAS additive latency (AL), off-chip driver impedance calibration (OCD), S# enable/disable, RS/RS# enable/disable, and OUTPUT disable/enable. These functions are controlled via the bits shown in Figure 7, Extended Mode Register Definition. The extended mode register is programmed via the LOAD MODE (LM) command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t MRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. DLL Enable/Disable The DLL may be enabled or disabled by programming bit E during the LOAD MODE command as shown in Figure 7, Extended Mode Register Definition. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using a LOAD MODE command. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled and reset upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 2 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the or t SCK parameters. Output Drive Strength The output drive strength is defined by bit E as shown in Figure 7, Extended Mode Register Definition. The normal drive strength for all outputs are specified to be SSTL_8. Programming bit E = selects normal ( percent) drive strength for all outputs. Selecting a reduced drive strength option (bit E = ) will reduce all outputs to approximately 6 percent of the SSTL_8 drive strength. This option is intended for the support of the lighter load and/or point-to-point environments. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 8 23, 24, 25 Micron Technology, Inc. All rights reserved.

19 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM S# Enable/Disable Figure 7: Extended Mode Register Definition 256MB Address Bus BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus EMR out RS S# OCD Program RTT Posted CAS# RTT ODS DLL 52MB Address Bus BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Extended Mode Register (Ex) Address Bus BA2 5 4 EMR BA BA 3 GB Address Bus out RS S# OCD Program Rtt Posted CAS# Rtt ODS DLL A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Extended Mode Register (Ex) Address Bus EMR out RS S# OCD Program Rtt Posted CAS# Rtt ODS DLL Extended Mode Register (Ex) E2 Outputs Enabled Disabled E RS Enable Disabled Reserved E6 E2 Rtt (nominal) Rtt Disabled 75Ω 5Ω 5Ω E DLL Enable Enable (Normal) Disable (Test/Debug) E Output Drive Strength Full Strength Reduced Strength E S# Enable Enable Disable E9 E8 E7 OCD Operation OCD Not Supported Reserved Reserved Reserved OCD default state E5 E4 E3 Posted CAS# Additive Latency (AL) Reserved Reserved Reserved E5 E4 Mode Register Set Mode Register Set (MRS) Extended Mode Register (EMRS) Extended Mode Register (EMRS2) Extended Mode Register (EMRS3) During initialization, all three bits must be set to for OCD Default State, then must be set to before initialization is finished, as detailed in the initialization procedure. Available on -667 speed grade parts only. S# Enable/Disable The S# enable function is defined by bit E. When enabled (bit E = ), S# is the complement of the differential data strobe pair S/S#. When disabled (bit E = ), S is used in a single-ended mode and the S# pin is disabled. This function is also used to enable/disable RS#. If RS is enabled (E = ) and S# is enabled (E = ), then both S# and RS# will be enabled. RS/RS# is supported only on RDIMMs using x8 DDR2 SDRAM devices. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 9 23, 24, 25 Micron Technology, Inc. All rights reserved.

20 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM RS Enable/Disable RS Enable/Disable RS/RS# is supported only on RDIMMs using x8 DDR2 SDRAM devices. The RS enable function is defined by bit E as shown in Figure 7, Extended Mode Register Definition, on page 9. When enabled (E = ), RS is identical in function and timing to data strobe S during a READ. During a WRITE operation, RS is ignored by the DDR2 SDRAM device. Output Enable/Disable The OUTPUT enable function is defined by bit E2 as shown in Figure 7, Extended Mode Register Definition, on page 9. When enabled (E2 = ), all outputs (s, S, S#, RS, RS#) function normally. When disabled (E2 = ), all DDR2 SDRAM device outputs (s, S, S#, RS, RS#) are disabled removing output buffer current. The OUTPUT disable feature is intended to be used during IDD characterization of read current. On Die Termination (ODT) ODT effective resistance RTT(EFF) is defined by bits E2 and E6 of the EMR as shown in Figure 7, Extended Mode Register Definition, on page 9. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM device controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 75Ω and 5Ω are selectable and apply to each, S/S#, RS/ RS#, and DM signals. Additionally, the -667 speed modules offer a third option of 5Ω. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. The ODT control pin is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input pin are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge power-down modes of operation. If SELF REFRESH operation is used, RTT(EFF) should always be disabled and the ODT input pin is disabled by the DDR2 SDRAM device. During power-up and initialization of the DDR2 SDRAM device, ODT should be disabled until the EMR command is issued to enable the ODT feature, at which point the ODT pin will determine the RTT(EFF) value. Refer to the 256Mb, 52Mb, or Gb DDR2 SDRAM discrete data sheet for ODT timing diagrams. Off-Chip Driver (OCD) Impedance Calibration The OCD function is not supported and must be set to the default state. e Initialization on page, to properly set OCD defaults. Posted CAS Additive Latency (AL) Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM device. Bits E3 E5 define the value of AL as shown in Figure 7, Extended Mode Register Definition, on page 9. Bits E3 E5 allow the user to program the DDR2 SDRAM device with a CAS# additive latency of,, 2, 3, or 4 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result. In this operation, the DDR2 SDRAM device allows a READ or WRITE command to be issued prior to t RCD (MIN) with the requirement that AL t RCD(MIN). A typical application using this feature would set AL = t RCD (MIN) - x t CK. The READ or WRITE command is held for the time of the additive latency (AL) before it is issued internally to the DDR2 SDRAM device. READ Latency (RL) is controlled by the sum of the Posted CAS pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 2 23, 24, 25 Micron Technology, Inc. All rights reserved.

21 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Posted CAS Additive Latency (AL) additive latency (AL) and CAS Latency (CL); RL = AL + CL. Write latency (WL) is equal to READ latency minus one clock; WL = AL + CL - x t CK. An example of a READ latency is shown in Figure 8, READ Latency. An example of a WRITE latency is shown in Figure 9, Write Latency. Figure 8: READ Latency CK# T T T2 T3 T4 T5 T6 T7 T8 CK COMMAND ACTIVE n READ n NOP NOP NOP NOP NOP NOP NOP S, S# t RCD (MIN) AL = 2 CL = 3 DOUT n DOUT n + DOUT n + 2 DOUT n + 3 RL = 5 Burst length = 4 Shown with nominal, t SCK, and t SQ CAS# latency (CL) = 3 Additive latency (AL) = 2 READ latency (RL) = AL + CL = 5 TRANSITIONING DATA DON T CARE Figure 9: Write Latency CK# T T T2 T3 T4 T5 T6 T7 CK COMMAND ACTIVE n WRITE n NOP NOP NOP NOP NOP NOP t RCD (MIN) S, S# AL = 2 CL - = 2 WL = AL + CL - = 4 Din n Din n + Din n + 2 Din n + 3 Burst length = 4 CAS# latency (CL) = 3 Additive latency (AL) = 2 WRITE latency = AL + CL - = 4 TRANSITIONING DATA DON T CARE pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 2 23, 24, 25 Micron Technology, Inc. All rights reserved.

22 256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Extended Mode Register 2 (EMR2) Extended Mode Register 2 (EMR2) The Extended Mode Register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved as shown in Figure, Extended Mode Register 2 (EMR2) Definition. The EMR2 is programmed via the LOAD MODE command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t MRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Figure : Extended Mode Register 2 (EMR2) Definition 256MB Address Bus BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus Extended Mode EMR2 * * * * * * * * * * * * * Register (Ex) * E2 (A2) E (A) are reserved for future use and must all be programmed to '.' 52MB Address Bus BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus EMR2 * * * * * * * * * * * * * * * E3 (A3) E (A) are reserved for future use and must all be programmed to '.' GB Address Bus BA2 BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Extended Mode Register (Ex) Address Bus 6 * EMR2 * * * * * * * * * * * * * * Extended Mode Register (Ex) E5 E4 Mode Register Set Mode Register Set (MRS) Extended Mode Register (EMR) Extended Mode Register (EMR2) Extended Mode Register (EMR3) * E6 and E3 (A3) - E (A) are reserved for future use and must all be programmed to ''. pdf: 95aef8e6f86, source: 95aef8e5b799 HTF9C32_64_28x72AG_2.fm - Rev. C 6/5 EN 22 23, 24, 25 Micron Technology, Inc. All rights reserved.