ADOVE1B163B2G. 1. General Description. 2. Features. 3. Pin Assignment. 4. Pin Description. 5. Block Diagram. 6. Absolute Maximum Ratings

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1 Product Model Name ADOVE1B163B2G Product Specification DDR2-800(CL6) 200-Pin SO-DIMM 2GB (256M x 64-bits) Issuing Date 2009/12/09 Version 0 Item 1. General Description 2. Features 3. Pin Assignment 4. Pin Description 5. Block Diagram 6. Absolute Maximum Ratings 7. DC Operating Condition 8. ODT DC Electrical Characteristics 9. ODT Default Characteristics 10. Input DC Logic Level 11. Input AC Logic Level 12. AC Input Test condition 13. Differential Input DC Logic Level 14. Differential Input AC Logic Level 15. Differential AC Output parameters 16. Output AC Test Conditions 17. Output DC Current Drive 18. DC Characteristics 19. AC Timing for IDD Test Conditions 20. AC TIMING REQUIREMENTS 21. Package Dimensions

2 1. General Description ADOVE1B163B2G DDR2-800(CL6) 200-Pin SO-DIMM 2GB (256M x 64-bits) The ADATA s module is a 256Mx64 bits 2GB(2048MB) DDR2-800(CL6) SDRAM memory module. The SPD is programmed to JEDEC standard latency 800Mbps timing of at 1.8V. The module is composed of six-teen 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP (TSOP) package on a 200pin glass epoxy printed circuit board. The module is a Dual In-line Memory Module and intended for mounting onto 200-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. 2. Features Power supply (Normal): VDD & VDDQ = 1.8V ± 0.1V 1.8V (SSTL_18 compatible) I/O MRS Cycle with address key programs - CAS Latency (4, 5, 6) - Burst Length (4,8) Programmable Additive Latency: 0,1,2,3,4,5 Bi-directional, differential data strobe (DQS and /DQS) Differential clock input (CK, /CK) operation DLL aligns DQ and DQS transition with CK transition Double-data-rate architecture Auto refresh and self refresh Average Refresh period 7.8 us Off-Chip Driver (OCD) Impedance Adjustment On Die Termination Lead-free and Halogen-free products are RoHS Compliant ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 2 of 13

3 3. Pin Assignment Front Side Back Side PIN Name PIN Name PIN Name PIN Name PIN Name PIN Name PIN Name PIN Name 1 VREF 51 DQS2 101 A1 151 DQ42 2 VSS 52 DM2 102 A0 152 DQ46 3 VSS 53 VSS 103 VDD 153 DQ43 4 DQ4 54 VSS 104 VDD 154 DQ47 5 DQ0 55 DQ A10/AP 155 VSS 6 DQ5 56 DQ BA1 156 VSS 7 DQ1 57 DQ BA0 157 DQ48 8 VSS 58 DQ /RAS 158 DQ52 9 VSS 59 VSS 109 /WE 159 DQ49 10 DM0 60 VSS 110 /CS0 160 DQ53 11 /DQS0 61 DQ VDD 161 VSS 12 VSS 62 DQ VDD 162 VSS 13 DQS0 63 DQ /CAS 163 NC 14 DQ6 64 DQ ODT0 164 CK1 15 VSS 65 VSS 115 /CS1 165 VSS 16 DQ7 66 VSS 116 NC/A /CK1 17 DQ2 67 DM3 117 VDD 167 /DQS6 18 VSS 68 /DQS3 118 VDD 168 VSS 19 DQ3 69 NC 119 ODT1 169 DQS6 20 DQ12 70 DQS3 120 NC 170 DM6 21 VSS 71 VSS 121 VSS 171 VSS 22 DQ13 72 VSS 122 VSS 172 VSS 23 DQ8 73 DQ DQ DQ50 24 VSS 74 DQ DQ DQ54 25 DQ9 75 DQ DQ DQ51 26 DM1 76 DQ DQ DQ55 27 VSS 77 VSS 127 VSS 177 VSS 28 VSS 78 VSS 128 VSS 178 VSS 29 /DQS1 79 CKE0 129 /DQS4 179 DQ56 30 CK0 80 CKE1 130 DM4 180 DQ60 31 DQS1 81 VDD 131 DQS4 181 DQ57 32 /CK0 82 VDD 132 VSS 182 DQ61 33 VSS 83 NC 133 VSS 183 VSS 34 VSS 84 NC 134 DQ VSS 35 DQ10 85 NC/BA2 135 DQ DM7 36 DQ14 86 NC 136 DQ /DQS7 37 DQ11 87 VDD 137 DQ VSS 38 DQ15 88 VDD 138 VSS 188 DQS7 39 VSS 89 A VSS 189 DQ58 40 VSS 90 A DQ VSS 41 VSS 91 A9 141 DQ DQ59 42 VSS 92 A7 142 DQ DQ62 43 DQ16 93 A8 143 DQ VSS 44 DQ20 94 A6 144 VSS 194 DQ63 45 DQ17 95 VDD 145 VSS 195 SDA 46 DQ21 96 VDD 146 /DQS5 196 VSS 47 VSS 97 A5 147 DM5 197 SCL 48 VSS 98 A4 148 DQS5 198 SA0 49 /DQS2 99 A3 149 VSS 199 VDDSPD 50 NC 100 A2 150 VSS 200 SA1 ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 3 of 13

4 4. Pin Description PIN NAME FUNCTION CK0~CK1, /CK0~/CK1 System Clock Active on the positive and negative edge to sample all inputs. CKE0,CKE1 Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS0, /CS1 Chip Select Disables or Enables device operation by masking or enabling all input except CK, CKE and L(U)DQM A0~A13 Address Row / Column address are multiplexed on the same pins. (Row Address A0~A13, Column Address :A0~A9, Auto precharge A10/AP) BA0~BA2 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ63 Data Data and check bit inputs / outputs are multiplexed on the same pins. DQS0~DQS7, /DQS0~/DQS7 Data Strobe Bi-directional Data Strobe DM0~DM7 Data Mask Mask input data when DM is high. /RAS Row Address Strobe Latches row addresses on the positive edge of the CK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CK with /CAS low /WE Write Enable Enables write operation and row recharge. VDD / VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VREF Power Supply reference Power Supply for reference VDDSPD SPD Power Supply Serial EEPROM power Supply SDA Serial data I/O EEPROM serial data I/O SCL Serial clock EEPROM clock input SA0~SA1 Address in EEPROM EEPROM address input ODT0,ODT1 On Die Termination When high, termination resistance is enabled for all DQ, /DQ and DM pins, assuming the function is enabled in the Extended Mode Register Set. NC No Connection This pin is recommended to be left No Connection on the device. ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 4 of 13

5 5. Block Diagram ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 5 of 13

6 6. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on VDD supply relative to Vss VDD -1.0 ~ +2.3 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ +2.3 V Voltage on VDDL supply relative to Vss VDDQ -0.5 ~ +2.3 V Voltage on any pin relative to Vss VIN, Vout -0.5 ~ +2.3 V Storage temperature TSTG -55 ~ +100 Note: DDR2 SDRAM component specification Operation Temperature Condition Parameter Symbol Value Unit Note DRAM Component Case Temperature Range TC 0~+95 1 Note: 1. If the DRAM case temperature is above 85 C, the Auto-Refresh command interval has to be reduced to trefi=3.9us. 7. DC Operating Condition Voltage referenced to Vss = 0V, VDD&VDDQ=1.8V±0.1V, Tc = 0 to 85 Parameter Symbol Min Max Unit Note Supply Voltage VDD V 4,5 VDDSPD V Supply Voltage for DLL VDDL V 4 Supply Voltage for Output VDDQ V 4,5 Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 1,2 Termination Voltage VTT VREF VREF V 3 Note: 1. There is no specific device VDD supply voltage requirement for SSTL_1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically, the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (ac). 4. VTT of transmitting device must track VREF of receiving device. 5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together. ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 6 of 13

7 8. ODT DC Electrical Characteristics (TC=0 to 85, VDD&VDDQ=1.8V±0.1V) Parameter Symbol Min Max Unit Note Rtt effective impedance value for EMRS Rtt Ω 1 (A6,A2)=0,1;75Ω Rtt effective impedance value for EMRS Rtt Ω 1 (A6,A2)=0,1;150Ω Deviation of VM with respect to VDDQ/2 VM % 1 Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIH(ac)) and I(VIL(ac)) respectively. VIH(ac), VIL(ac), and VDDQ values defined in SSTL_18 Rtt(eff) = V IH(ac) V IL(ac) I(V IH(ac)) I(V IL(ac)) Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load. 2 x VM VM = - 1 X 100% VDDQ 9. ODT Default Characteristics (TC=0 to 85, VDD&VDDQ=1.8V±0.1V) Parameter Min Typ Max Unit Note Output impedance Ω 1 Pull-up and Pull-down mismatch 0-4 Ω 1,2 Output slew rate V/ns 3,4 Note : 1. Impedance measurement condition for output source DC current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/IOH must be less than 23.4 Ohm for values of VOUT between VDDQ and VDDQ-280mV.VOUT/IOL must be less than 23.4 Ohm for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull-up and pull-down, both are measured at the same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 10. Input DC Logic Level Parameter Symbol Min Max Unit DC Input logic high voltage VIH (DC) VREF VDDQ+0.3 V DC Input logic low voltage VIL (DC) -0.3 VREF V ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 7 of 13

8 11. Input AC Logic Level Parameter Symbol Min Max Unit AC Input logic high voltage VIH (AC) VREF V AC Input logic high voltage VIL (AC) - VREF V 12. AC Input Test condition Parameter Symbol Value Unit Note Input reference voltage VREF 0.5 x VDDQ V 1 Input signal maximum peak to peak swing VSWING(max) 1.0 V 1 Input signal maximum slew rate SLEW 1.0 V/ns 2,3 Note : 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL (dc) max to VIH (ac) min for rising edges and the range from VIH (dc) min to VIL (ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveform switch from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. 13. Differential Input DC Logic Level Symbol Parameter Min Max Units Notes VIN (DC) DC differential signal voltage -0.3 VDDQ V 1 VID (DC) DC differential input voltage 0.25 VDDQ V 2 Note : 1. VIN (DC) specifies the allowable DC execution of each input of differential pair such CK, /CK, DQS, /DQS, LDQS, /LDQS, UDQS, /UDQS. 2. VID (DC) specifies the input differential voltage VTR-VCP required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as /CK, /DQS, /LDQS, /UDQS) level. The timing value is equal to VIH(DC) - VIL(DC). ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 8 of 13

9 14. Differential Input AC Logic Level Symbol Parameter Min Max Units Notes VID (AC) AC differential input voltage 0.5 VDDQ V 1, 2 VIX (AC) AC differential cross point voltage 0.5 x VDDQ x VDDQ + V Note : 1. VID (AC) specifies the input differential voltage VTR-VCP required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as /CK, /DQS, /LDQS, /UDQS) level. The timing value is equal to VIH(DC) - VIL(DC). 2. The typical value of VIX(AC) is expected to be about 0.5*VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signal must cross. 15. Differential AC Output parameters Symbol Parameter Min Max Units Notes VOX (AC) AC differential cross point voltage 0.5 x VDDQ x VDDQ + V 1 Note : 1. The typical value of VOX(AC) is expected to be about 0.5*VDDQ of the transmitting device and VOX(AC) is expected to track variation VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross Output AC Test Conditions Symbol Parameter SSTL_18 Class II Units Notes VOH Minimum Required output Pull-up under AC test load VTT V 5 VOL Maximum Required output Pull-down under AC test load VTT V 5 VOTR Output Timing measurement reference level 0.5 x VDDQ V 1 Note : 1. The VDDQ of the device under test is referenced. 2. VDDQ = 1.7V; VOUT = 1.42V. 3. VDDQ = 1.7V; VOUT = 0.28V 4. The DC value of VREF applied to the receiving device is expected to be set to VTT. 5. After OCD calibration to 18Ω at TA = 25 C, VDD = VDDQ = 1.8V. ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 9 of 13

10 17. Output DC Current Drive Symbol Parameter SSTL_18 Class II Units Notes IOH (DC) Output Minimum source DC current ma 1, 2, 3 IOL (DC) Output Maximum sink DC current 13.4 ma 2, 3, 4 Note : 1. VDDQ=1.7V; VOUT=1420mV. (VOUT VDDQ)/IOH must be less than 21 ohm for value of VOUT between VDDQ and VDDQ 280mV. 2. VDDQ=1.7V; VOUT=280mV. VOUT/IOL must less than 21 ohm for value of VOUT between 0V and 280mV. 3. The dc Value of VREF applied to the receiving device is set to VTT. 4. The value of IOH(dc) and IOL(dc) are based on the conditions given in notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operation point along a 21 ohm load line to define a convent for measurement. 18. DC Characteristics (TC=0 to 85, VDD&VDDQ=1.8V±0.1V) Symbol Condition Typical Unit IDD0 One bank Active-Precharge 776 ma IDD1 One bank operation 936 ma IDD2P Precharge power-down standby current 112 ma IDD2Q Precharge quiet standby current 800 ma IDD2N Idle standby current 800 ma IDD3P-F Active power-down standby current 640 ma IDD3P-S Active power-down standby current 160 ma IDD3N Active standby current 960 ma IDD4R Operating current-burst read 1336 ma IDD4W Operating current-burst write 1336 ma IDD5 Auto refresh current 3760 ma IDD6 Self refesh current 112 ma IDD7 Operating current-four bank operation 2736 ma Note :: Module IDD was calculated on the basis of component IDD. Only for reference. ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 10 of 13

11 19. AC Timing for IDD Test Conditions Parameter DDR2-800 (6-6-6) Unit CL 6 tck trcd 15 ns trc 60 ns trrd 7.5 ns tck 2.5 ns tras(min) 45 ns tras(max) ns trp 15 ns trfc ns 20. AC TIMING REQUIREMENTS Symbol Parameter Min Max Unit tck(avg) Average clock period ps tch(avg) Average clock HIGH pulse width tck(avg) tcl(avg) Average clock LOW pulse width tck(avg) tdqss DQS latching rising transitions to associated clock edges tck(avg) tdss DQS falling edge to CK setup time tck(avg) tdsh DQS falling edge hold time from CK tck(avg) tdqsh DQS input HIGH pulse width tck(avg) tdqsl DQS input LOW pulse width tck(avg) twpre Write preamble tck(avg) twpst Write postamble tck(avg) tis(base) Address and control input setup time ps tih(base) Address and control input hold time ps tipw Control & Address input pulse width for each input tck(avg) tds(base) DQ and DM input setup time 50 - ps tdh(base) DQ and DM input hold time ps tdipw DQ and DM input pulse width for each input tck(avg) tac DQ output access time from CK/CK ps tdqsck DQS output access time from CK/CK ps thz Data-out high-impedance time from CK/CK - tac,max ps tlz(dqs) DQS/DQS low-impedance time from CK/CK tac,min tac,max ps tlz(dq) DQ low-impedance time from CK/CK 2 x tac,min tac,max ps ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 11 of 13

12 tdqsq DQS-DQ skew for DQS and associated DQ signals ps thp CK half pulse width Min(tCH(abs),tCL(abs)) - ps tqhs DQ hold skew factor ps tqh DQ/DQS output hold time from DQS thp - tqhs - ps trpre Read preamble tck(avg) trpst Read postamble tck(avg) tccd CAS to CAS command delay 2 - nck twr Write recovery time 15 - ns tdal Auto precharge write recovery + precharge time WR + tnrp - nck twtr Internal write to read command delay ns trtp Internal read to precharge command delay ns tcke CKE minimum pulse width (HIGH and LOW pulse width) 3 - nck txsnr Exit self refresh to a non-read command trfc ns txsrd Exit self refresh to a read command nck txp Exit precharge power down to any command 2 - nck txard Exit active power down to read command 2 - nck Exit active power down to read command (slow exit, lower txards 8 - AL - nck power) tmrd Mode register set command cycle time 2 - nck toit OCD drive mode output delay 0 12 ns Minimum time clocks remains ON after CKE asynchronously tdelay tis +tck(avg) +tih - ns drops LOW trap Active to auto-precharge delay trcd min - ns 85 <TCASE <95 0 <TCASE <85 trefi Average Periodic Refresh interval us /3.9 /7.8 ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 12 of 13

13 21. Package Dimensions ADOVE1B163B2G_DDR2-800(CL=6)_2GB(128Mx8_Halogen free)_so-dimm Rev /12/09 Page 13 of 13