DDR SDRAM UNBUFFERED DIMM

Transcription

1 DDR SDRAM UNBUFFERED DIMM Features 84-pin, dual in-line memory module (DIMM) Fast data transfer rates: PC2 or PC27 Utilizes 266 MT/s and 333 MT/s DDR SDRAM components 256MB (32 Meg x 64), 52MB (64 Meg x 64), GB (28 Meg x 64), and 2GB (256 Meg x 64) VDD = VD = +2.5V VDDSPD = +2.3V to +3.6V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge S edge-aligned with data for READs; centeraligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (S) transmitted/ received with data i.e., source-synchronous data capture Differential clock inputs (CK and CK#) Four internal device banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 5.6µs (256MB), 7.825µs (52MB, GB, and 2GB) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Programmable READ CAS latency Gold edge contacts 256MB, 52MB, GB, 2GB (x64, DR) MT6VDDT3264A 256MB MT6VDDT6464A 52MB MT6VDDT2864A GB MT6VDDT25664A 2GB (ADVANCE) For the latest data sheet, please refer to the Micron Web site: Figure : 84-Pin DIMM (MO-26) Standard.25in. (3.mm) Low-Profile.5in. (29.2mm) OPTIONS MARKING Package 84-pin DIMM (standard) G 84-pin DIMM (lead-free) Y Memory Clock, Speed, CAS Latency 2 6ns/66MHz (333 MT/s) CL = ns/33 MHz (266 MT/s) CL = ns/33 MHz (266 MT/s) CL = 2-26A 7.5ns/33 MHz (266 MT/s) CL = PCB Standard.25in. (3.mm) See page 2 note Low-Profile.2in. (3.48mm) See page 2 note NOTE:. Consult Micron for product availability. 2. CL = CAS (READ) Latency. Table : Address Table 256MB 52MB GB 2GB Refresh Count 4K 8K 8K 8K Row Addressing 4K (A A) 8K (A A2) 8K (A A2) 6K (A A3) Device Bank Addressing 4 (BA, BA) 4 (BA, BA) 4 (BA, BA) 4 (BA, BA) Device Configuration 28Mb (6 Meg x 8) 256Mb (32 Meg x 8) 52Mb (64 Meg x 8) Gb (28 Meg x 8) Column Addressing K (A A9) K (A A9) 2K (A A9, A) 2K (A A9, A) Module Rank Addressing 2 (S#, S#) 2 (S#, S#) 2 (S#, S#) 2 (S#, S#) pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 24 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON S PRODUCTION DATA SHEET SPECIFICATIONS.

2 Table 2: Part Numbers and Timing Parameters PART NUMBER MODULE DENSITY CONFIGURATION MODULE BANDWIDTH MEMORY CLOCK/ DATA RATE LATENCY (CL - t RCD - t RP) MT6VDDT3264AG MB 32 Meg x GB/s 6ns/333 MT/s MT6VDDT3264AY MB 32 Meg x GB/s 6ns/333 MT/s MT6VDDT3264AG MB 32 Meg x GB/s 7.5ns/266 MT/s MT6VDDT3264AY MB 32 Meg x GB/s 7.5ns/266 MT/s MT6VDDT3264AG-26A 256MB 32 Meg x GB/s 7.5ns/266 MT/s MT6VDDT3264AY-26A 256MB 32 Meg x GB/s 7.5ns/266 MT/s MT6VDDT3264AG MB 32 Meg x GB/s 7.5ns/266 MT/s MT6VDDT3264AY MB 32 Meg x GB/s 7.5ns/266 MT/s MT6VDDT6464AG MB 64 Meg x GB/s 6ns/333 MT/s MT6VDDT6464AY MB 64 Meg x GB/s 6ns/333 MT/s MT6VDDT6464AG MB 64 Meg x GB/s 7.5ns/266 MT/s MT6VDDT6464AY MB 64 Meg x GB/s 7.5ns/266 MT/s MT6VDDT6464AG-26A 52MB 64 Meg x GB/s 7.5ns/266 MT/s MT6VDDT6464AY-26A 52MB 64 Meg x GB/s 7.5ns/266 MT/s MT6VDDT6464AG MB 64 Meg x GB/s 7.5ns/266 MT/s MT6VDDT6464AY MB 64 Meg x GB/s 7.5ns/266 MT/s MT6VDDT2864AG-335 GB 28 Meg x GB/s 6ns/333 MT/s MT6VDDT2864AY-335 GB 28 Meg x GB/s 6ns/333 MT/s MT6VDDT2864AG-262 GB 28 Meg x GB/s 7.5ns/266 MT/s MT6VDDT2864AY-262 GB 28 Meg x GB/s 7.5ns/266 MT/s MT6VDDT2864AG-26A GB 28 Meg x GB/s 7.5ns/266 MT/s MT6VDDT2864AY-26A GB 28 Meg x GB/s 7.5ns/266 MT/s MT6VDDT2864AG-265 GB 28 Meg x GB/s 7.5ns/266 MT/s MT6VDDT2864AY-265 GB 28 Meg x GB/s 7.5ns/266 MT/s MT6VDDT25664AG-335 2GB 256 Meg x GB/s 6ns/333 MT/s MT6VDDT25664AY-335 2GB 256 Meg x GB/s 6ns/333 MT/s MT6VDDT25664AG-262 2GB 256 Meg x GB/s 7.5ns/266 MT/s MT6VDDT25664AY-262 2GB 256 Meg x GB/s 7.5ns/266 MT/s MT6VDDT25664AG-26A 2GB 256 Meg x GB/s 7.5ns/266 MT/s MT6VDDT25664AY-26A 2GB 256 Meg x GB/s 7.5ns/266 MT/s MT6VDDT25664AG-265 2GB 256 Meg x GB/s 7.5ns/266 MT/s MT6VDDT25664AY-265 2GB 256 Meg x GB/s 7.5ns/266 MT/s NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT6VDDT6464AG-265A. pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 2 24 Micron Technology, Inc.

3 Table 3: Pin Assignment (84-Pin DIMM Front) Table 4: Pin Assignment (84-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL VREF DNU 7 VDD 2 25 S2 48 A 7 NC 3 VSS 26 VSS 49 DNU A9 5 VSS S DNU 74 VSS A7 52 BA CK2# 7 VDD 3 VD CK VD 77 VD 9 NC 32 A S6 NC S VSS 34 VSS VSS 8 VSS S3 59 BA 82 NC 4 S 37 A VD 38 VDD CK VD 85 VDD 7 CK# WE# 86 S7 8 VSS 4 A VSS 65 CAS# A 66 VSS 89 VSS 2 CKE 44 DNU 67 S5 9 NC 22 VD 45 DNU SDA VDD SCL NOTE:. Pin 5 is No Connect for 256MB, or A2 for 52MB, GB, 2GB. 2. Pin 67 is No Connect (NC) for 256MB, 52MB, and GB, or A3 for 2GB. Figure 2: Pin Locations: 84-Pin DIMM PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 93 VSS 6 VSS 39 VSS DNU 63 NC A 4 A 64 VD 96 VD 9 DM2 42 DNU DM 2 VDD 43 VD DNU 67 2 NC/A A8 45 VSS 68 VDD VSS DM6 NC 24 VSS NC 25 A6 48 VDD NC DM4 72 VD 4 VD NC VD DM3 52 VSS 6 7 DM 3 A VSS 8 VDD RAS# 77 DM VSS VD CKE 34 DNU 57 S# 8 VD 2 VD 35 DNU 58 S# 8 SA 3 NC 36 VD 59 DM5 82 SA CK 6 VSS 83 SA2 5 NC/A2 38 CK# VDDSPD Front View Standard.25in. (3.mm) Front View Low-Profile.5in. (29.2mm) U U U2 U3 U4 U6 U7 U8 U9 U U2 U3 U4 U6 U7 U8 U9 PIN PIN 52 PIN 53 PIN 92 PIN PIN 52 PIN 53 PIN 92 Back View Back View U9 U U U2 U3 U5 U6 U7 U8 U9 U8 U7 U6 U4 U3 U2 U PIN 84 PIN 45 PIN 44 PIN 93 PIN 84 PIN 45 PIN 44 PIN 93 Indicates a VDD or VD pin Indicates a VSS pin Indicates a VDD or VD pin Indicates a VSS pin pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 3 24 Micron Technology, Inc.

4 Table 5: Pin Descriptions 256MB, 52MB, GB, 2GB (x64, DR) Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 63, 65, 54 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 6, 7,, 76, 37, 38 CK, CK#, CK, CK#, CK2, CK2# Input Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (s and S) is referenced to the crossings of CK and CK#. 2, CKE, CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER- DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. 57, 58 S#, S# Input Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 52, 59 BA, BA Input Bank Address: BA and BA define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 27, 29, 32, 37, 4, 43, 48, 5 (52MB, GB, 2GB), 8, 22, 25, 3, 4, 67 (2GB) A A (256MB) A A2 (52MB, GB) A A3 (2GB) Input 5, 4, 25, 36, 56, 67, 78, 86 S S7 Input/ Output 97, 7, 9, 29, 49, 59, 69, 77 Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A LOW, device bank selected by BA, BA) or all device banks (A HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA and BA define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Strobe: Output with READ data, input with WRITE data. S is edge-aligned with READ data, centered in WRITE data. Used to capture data. DM DM7 Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM lines do not affect READ operation. pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 4 24 Micron Technology, Inc.

5 Table 5: 2, 4, 6, 8, 2, 3, 9, 2, 23, 24, 28, 3, 33, 35, 39, 4, 53, 55, 57, 6, 6, 64, 68, 69, 72, 73, 79, 8, 83, 84, 87, 88, 94, 95, 98, 99, 5, 6, 9,, 4, 7, 2, 23, 26, 27, 3, 33, 46, 47, 5, 5, 53, 55, 6, 62, 65, 66, 7, 7, 74,, 78, Input/ Output 256MB, 52MB, GB, 2GB (x64, DR) Data I/Os: Data bus. 92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 8,82, 83 SA SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 9 SDA Input/ Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect device. VREF Supply SSTL_2 reference voltage. 5, 22, 3, 54, 62, 77, 96, 4, VD Supply Power Supply: +2.5V ±.2V. 2, 28, 36, 43, 56, 64, 72, 8 7, 38, 46, 7, 85, 8, 2, VDD Supply Power Supply: +2.5V ±.2V. 48, 68 3,, 8, 26, 34, 42, 5, 58, VSS Supply Ground. 66, 74, 8, 89, 93,, 6, 24, 32, 39, 45, 52, 6, VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V. 44, 45, 47, 49, 5, 34, 35, 4, 42, 44 9,, 7, 82, 9,, 2, 3, 3, 5 (256MB), 63, 67 (256MB, 52MB, GB), 73 Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION DNU Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC No Connect: These pins should be left unconnected. pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 5 24 Micron Technology, Inc.

6 Figure 3: Functional Block Diagram Standard PCB S# S# S DM S DM S2 DM2 S3 DM DM CS# S U DM CS# S U7 DM CS# S DM CS# S U6 U2 DM CS# S U3 DM CS# S U5 S4 DM4 S5 DM5 S6 DM S7 DM7 DM CS# S DM CS# S DM CS# S 56 U4 U U8 DM CS# S DM CS# S U3 U5 DM CS# S U6 DM CS# S U DM CS# S U2 DM CS# S U7 DM CS# S U BA, BA A-A (256MB) A-A2 (52MB, GB) A-A3 (2GB) RAS# CAS# WE# CKE CKE BA, BA: DDR SDRAMS A-A: DDR SDRAMS A-A2: DDR SDRAMS A-A3: DDR SDRAMS RAS#: DDR SDRAMS CAS#: DDR SDRAMS WE#: DDR SDRAMS CKE: DDR SDRAMS U, U3, U6, U8, U, U3, U4, U6 CKE: DDR SDRAMS U2, U4, U5, U7, U, U2, U5, U7 CK CK# CK CK# CK2 CK2# 2 3pF 2 2 U4, U6, U3, U5 U-U3, U6-U8 U7-U2 VDDSPD VD SPD/EEPROM DDR SDRAMS SCL WP SERIAL PD U9 A A A2 SDA VDD DDR SDRAMS SA SA SA2 VREF DDR SDRAMS NOTE: VSS DDR SDRAMS. All resistor values are 22Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at Standard modules use the following SDRAM devices: MT46V6M8TG (256MB); MT46V32M8TG (52MB); MT46V64M8TG (GB); MT46V28M8TG (2GB) Lead-free modules use the following SDRAM devices: MT46V6M8P (256MB); MT46V32M8P (52MB); MT46V64M8P (GB); MT46V28M8P (2GB) pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 6 24 Micron Technology, Inc.

7 Figure 4: Functional Block Diagram Low-Profile PCB S# S# S DM S DM S2 DM2 S3 DM DM CS# S U DM CS# S U DM CS# S DM CS# S U2 U2 DM CS# S U3 DM CS# S U3 S4 DM4 S5 DM5 S6 DM S7 DM7 DM CS# S DM CS# S DM CS# S U4 U4 59 U DM CS# S DM CS# S U6 U6 DM CS# S U7 DM CS# S U8 DM CS# S U7 DM CS# S U8 DM CS# S U9 NOTE: BA, BA A-A (256MB) A-A2 (52MB, GB) RAS# CAS# CKE CKE WE# BA, BA: DDR SDRAMS A-A: DDR SDRAMS SCL SERIAL PD U A-A2: DDR SDRAMS RAS#: DDR SDRAMS WP A SA A SA A2 SA2 CAS#: DDR SDRAMS CKE: DDR SDRAMS U U4, U6 U9 CKE: DDR SDRAMS U, U4, U6 U9 WE#: DDR SDRAMS 2 DDR CK SDRAM CK# X 4. All resistor values are 22Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at 3pF SDA CK CK# 2 3pF VDDSPD VD VDD VREF VSS DDR SDRAM X 6 CK2 CK2# SPD DDR SDRAMS DDR SDRAMS DDR SDRAMS DDR SDRAMS 2 3pF DDR SDRAM X 6 Standard modules use MT46V6M8TG for 256MB; MT46V32M8TG for 52MB; MT46V64M8TG for GB Lead-free modules use MT46V6M8P for 256MB; MT46V32M8P for 52MB; MT46V64M8P for GB pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 7 24 Micron Technology, Inc.

8 General Description The MT6VDDT3264A, MT6VDDT6464A, MT6VDDT2864A, and MT6VDDT25664A are highspeed CMOS, dynamic random-access, 256MB, 52MB, GB and 2GB memory modules organized in x64 configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. Double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (S) is transmitted externally, along with data, for use in data capture at the receiver. S is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. S is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of S, and output data is referenced to both edges of S, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA, BA select devices bank; A A select device row for 256MB; A A2 select device row for 52MB, GB; A A3 select device row for 2GB). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 28Mb, 256Mb, 52Mb, or Gb DDR SDRAM component data sheets. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using a 2,48-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 28 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 28 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I 2 C bus using the DIMM s SCL (clock) and SDA (data) signals, together with SA (2:), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 5, Mode Register Definition Diagram, on page 9. The mode register is programmed via the MODE REG- ISTER SET command (with BA = and BA = ) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 8 24 Micron Technology, Inc.

9 Mode register bits A A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4 A6 specify the CAS latency, and A7 A (256MB) or A7 A2 (52MB, GB), or A7 A3 (2GB) specify the operating mode. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3- Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration; see Note 5, of Table 6, Burst Definition Table, on page ). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS Latency Diagram. Figure 5: Mode Register Definition Diagram 256MB Module BA 4 * BA BA A A 3 2 * * Operating Mode CAS Latency BT Burst Length BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A * M3 and M2 (BA and BA) must be, to select the base mode register (vs. the extended mode register). 52MB and GB Modules A9 A8 A7 A6 A5 A4 A3 A2 A A * Operating Mode CAS Latency BT Burst Length * M4 and M3 (BA and BA) must be, to select the base mode register (vs. the extended mode register). 2GB Module BA BA A3 A2 A A 5 4 * * A9 A8 A7 A6 A5 A4 A3 A2 A A Operating Mode CAS Latency BT Burst Length * M5 and M4 (BA and BA) must be, to select the base mode register (vs. the extended mode register). M6 M5 M4 M3 M3 M2 M M M9 M8 M7 M6-M Valid Valid - M2 M M CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved Address Bus Mode Register (Mx) Address Bus Mode Register (Mx) Address Bus Mode Register (Mx) Burst Length M3 = Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 9 24 Micron Technology, Inc.

10 Table 6: Burst Definition Table 256MB, 52MB, GB, 2GB (x64, DR) Figure 6: CAS Latency Diagram BURST LENGTH STARTING COLUMN ADDRESS A A ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED A A2 A A NOTE:. For a burst length of two, A Ai select the two-dataelement block; A selects the first access within the block. 2. For a burst length of four, A2 Ai select the four-dataelement block; A A select the first access within the block. 3. For a burst length of eight, A3 Ai select the eight-dataelement block; A A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 for 256MB, 52MB; i = 9, for GB, 2GB. Table 7: CAS Latency (CL) Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = f 33 f f 33 f 33-26A f 33 f f f 33 CK# CK COMMAND S CK# CK COMMAND S T T T2 T2n T3 T3n READ NOP NOP NOP CL = 2 T T T2 T2n T3 T3n READ NOP NOP NOP CL = 2.5 Burst Length = 4 in the cases shown Shown with nominal t AC, t SCK, and t SQ TRANSITIONING DATA DON T CARE If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Figure 7, CAS Latency (CL) Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 A (256MB), A7 A2 (52MB, GB), or A7 A3 (2GB) each set to zero, and bits A A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9 A (256MB), A7 and A9 A2 (52MB, GB), or A7 and A9 A3 (2GB)each set to zero, bit A8 set to one, and bits A A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7 A (256MB), A7 A2 (52MB, GB), or A7 A3 (2GB) are reserved for future use and/or test modes. Test modes pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 24 Micron Technology, Inc.

11 and reserved states should not be used because unknown operation or incompatibility with future versions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 7, Extended Mode Register Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA = and BA = ) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA/BA both LOW) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 2 clock cycles with CKE HIGH must occur before a READ command can be issued. Figure 7: Extended Mode Register Definition Diagram 256MB Module BA BA A A MB and GB Modules BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A 4 3 2GB Module BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Operating Mode DS DLL Operating Mode DS DLL A9 A8 A7 A6 A5 A4 A3 A2 A A Operating Mode DS DLL E3 E2 E E E9 E8 E7 E6 E5 E4 E3 E2 E, E Valid Address Bus Extended Mode Register (Ex) Address Bus Extended Mode Register (Ex) Operating Mode Reserved Reserved NOTE:. BA and BA (E3 and E2 for 256MB, E4 and E3 for 52MB, GB, or E5 and E4 for 2GB) must be, to select the Extended Mode Register (vs. the base Mode Register). 2. QFC# is not supported. E E Address Bus Extended Mode Register (Ex) DLL Enable Disable Drive Strength Normal pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 24 Micron Technology, Inc.

12 Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description of commands and operations, refer to the 28Mb, 256Mb, 52Mb, or Gb DDR SDRAM component data sheets. Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES DESELECT (NOP) H X X X X NO OPERATION (NOP) L H H H X ACTIVE (Select bank and activate row) L L H H Bank/Row 2 READ (Select bank and column, and start READ burst) L H L H Bank/Col 3 WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3 BURST TERMINATE L H H L X 4 PRECHARGE (Deactivate row in bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X 6, 7 LOAD MODE REGISTER L L L L Op-Code 8 NOTE:. DESELECT and NOP are functionally interchangeable. 2. BA BA provide device bank address and A A (256MB), A A2 (52MB, GB), or A A3 (2GB) provide row address. 3. BA BA provide device bank address; A A9 (256MB, 52MB) or A A9, A(GB, 2GB), provide column address; A HIGH enables the auto precharge feature (nonpersistent), and A LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A LOW: BA BA determine which device bank is precharged. A HIGH: all device banks are precharged and BA BA are Don t Care. 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are Don t Care except for CKE. 8. BA BA select either the mode register or the extended mode register (BA =, BA = select the mode register; BA =, BA = select extended mode register; other combinations of BA BA are reserved). A A (256MB), A A2 (52MB, GB), or A A3 (2GB) provide the op-code to be written to the selected mode register. Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) DM S WRITE Enable L Valid WRITE Inhibit H X pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 2 24 Micron Technology, Inc.

13 Voltage on VDD Supply Relative to VSS V to +3.6V Voltage on VD Supply Relative to VSS V to +3.6V Voltage on VREF and Inputs Relative to VSS V to +3.6V Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on I/O Pins Relative to VSS V to VD +.5V Operating Temperature T A (ambient) C to +7 C Storage Temperature (plastic) C to +5 C Short Circuit Output Current mA Table : DC Electrical Characteristics and Operating Conditions Notes: 5, 4, 48; notes appear on pages 2 23; C T A +7 C PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage VDD V 32, 36 I/O Supply Voltage VD V 32, 36, 39 I/O Reference Voltage VREF.49 VD.5 VD V 6, 39 I/O Termination Voltage (system) VTT VREF -.4 VREF +.4 V 7, 39 Input High (Logic ) Voltage VIH(DC) VREF +.5 VDD +.3 V 25 Input Low (Logic ) Voltage VIL(DC) -.3 VREF -.5 V 25 INPUT LEAKAGE CURRENT Any input V VIN VDD, VREF pin V VIN.35V (All other pins not under test = V) Command/ Address, RAS#, CAS#, WE# CKE, S# -6 6 II CK, CK# -8 8 µa 47 CK, CK# -2 2 CK2, CK2# DM -4 4 OUTPUT LEAKAGE CURRENT, S IOZ - µa 47 (s are disabled; V VOUT VD) OUTPUT LEVELS High Current (VOUT = VD-.373V, minimum VREF, minimum VTT) IOH -6.8 ma 33, 34 Low Current (VOUT =.373V, maximum VREF, maximum VTT) IOL 6.8 ma Table : AC Input Operating Conditions Notes: 5, 4, 48, 49; notes appear on pages 2 23; C T A +7 C; VDD = VD = +2.5V ±.2V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Input High (Logic ) Voltage VIH(AC) VREF +.3 V 2, 25, 35 Input Low (Logic ) Voltage VIL(AC) VREF -.3 V 2, 25, 35 I/O Reference Voltage VREF(AC).49 VD.5 VD V 6 pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 3 24 Micron Technology, Inc.

14 Table 2: IDD Specifications and Conditions 256MB DDR SDRAM components only Notes: 5, 8,, 4, 48; notes appear on pages 2 23; C T A +7 C; VDD = VD = +2.5V ±.2V PARAMETER/CONDITION SYM A/ -265 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; t RC = t RC IDD a, ma 2, 42 (MIN); t CK = t CK (MIN);, DM and S inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; IDD a, ma 2, 42 Burst = 2; t RC = t RC (MIN); t CK = t CK (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (MIN); CKE = (LOW) IDD2N b ma 2, 28, 44 IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = t CK IDD2F b ma 45 MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for, S, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW IDD3P b ma 2, 28, 44 ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3N b ma 4 bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN);, DM ands inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank IDD4R a,44,64,24 ma 2, 42 active; Address and control inputs chan-ging once per clock cycle; t CK = t CK (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One IDD4W a,44,24,24 ma 2 device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle AUTO REFRESH CURRENT t REFC = t RFC (MIN) IDD5 b 4,24 3,52 3,52 ma 2, 24, 44 REFC = 5.625µs IDD5A b ma SELF REFRESH CURRENT: CKE.2V IDD6 b ma 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, t RC = t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7 a 2,864 2,664 2,624 ma 2, 43 NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. MAX pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 4 24 Micron Technology, Inc.

15 Table 3: IDD Specifications and Conditions 52MB DDR SDRAM Components only Notes: 5, 8,, 4, 48; notes appear on pages 2 23; C T A +7 C; VDD = VD = +2.5V ±.2V MAX PARAMETER/CONDITION SYM OPERATING CURRENT: One device bank; Active-Precharge; t RC = t RC (MIN); t CK = t CK (MIN);, DM and S inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; t RC = t RC (MIN); t CK = t CK (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = t CK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for, S, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN);, DM ands inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle -26A/ -265 UNITS NOTES IDD a,32, ma 2, 42 IDD a,392,32,92 ma 2, 42 IDD2P b ma 2, 28, 44 IDD2F b ma 45 IDD3P b ma 2, 28, 44 IDD3N b ma 4 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R a,432,232,232 ma 2, 42 One bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W a,432,232,232 ma 2 One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle AUTO REFRESH CURRENT t REFC = t RFC (MIN) IDD5 b 4,8 3,76 3,76 ma 2, 44 t REFC = 7.825µs IDD5A b ma 2, 44 SELF REFRESH CURRENT: CKE.2V IDD6 b ma 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, t RC = t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7 a 3,32 2,832 2,832 ma 2, 43 NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 5 24 Micron Technology, Inc.

16 Table 4: IDD Specifications and Conditions GB DDR SDRAM Components only Notes: 5, 8,, 4, 48; notes appear on pages 2 23; C T A +7 C; VDD = VD = +2.5V ±.2VV MAX PARAMETER/CONDITION SYM OPERATING CURRENT: One device bank; Active-Precharge; t RC = t RC (MIN); t CK = t CK (MIN);, DM and S inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; t RC = t RC (MIN); t CK = t CK (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = t CK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for, S, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN);, DM ands inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle -26A/ -265 UNITS NOTES IDD a,8,8 96 ma 2, 42 IDD a,32,32,2 ma 2, 42 IDD2P b ma 2, 28, 44 IDD2F b ma 45 IDD3P b ma 2, 28, 44 IDD3N b ma 4 IDD4R a,36,36,2 ma 2, 42 IDD4W a,44,28,2 ma 2 AUTO REFRESH CURRENT t REFC = t RFC (MIN) IDD5 b 4,64 4,64 4,48 ma 2, 44 t REFC = 7.825µs IDD5A b ma 2, 44 SELF REFRESH CURRENT: CKE.2V IDD6 b ma 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, t RC = t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7 a 3,28 3,24 2,84 ma 2, 43 NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 6 24 Micron Technology, Inc.

17 Table 5: IDD Specifications and Conditions 2GB DDR SDRAM Components only Notes: 5, 8,, 4, 48; notes appear on pages 2 23; C T A +7 C; VDD = VD = +2.5V ±.2VV MAX PARAMETER/CONDITION SYM OPERATING CURRENT: One device bank; Active-Precharge; t RC = t RC (MIN); t CK = t CK (MIN);, DM and S inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; t RC = t RC (MIN); t CK = t CK (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = t CK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for, S, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN);, DM ands inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN);, DM, and S inputs changing twice per clock cycle -26A/ -265 UNITS NOTES IDD a,8,8,24 ma 2, 42 IDD a,32,32,52 ma 2, 42 IDD2P b ma 2, 28, 44 IDD2F b ma 45 IDD3P b ma 2, 28, 44 IDD3N b ma 4 IDD4R a,36,36,68 ma 2, 42 IDD4W a,28,28,76 ma 2 AUTO REFRESH CURRENT t REFC = t RFC (MIN) IDD5 b 4,64 4,64 5,28 ma 2, 44 t REFC = 7.825µs IDD5A b ma 2, 44 SELF REFRESH CURRENT: CKE.2V IDD6 b ma 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, t RC = t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7 a 3,28 3,24 3,96 ma 2, 43 NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 7 24 Micron Technology, Inc.

18 Table 6: Capacitance Note: ; notes appear on pages 2 23 PARAMETER SYMBOL MIN MAX UNITS Input/Output Capacitance:, S, DM CIO 8 pf Input Capacitance: Command and Address CI pf Input Capacitance: S#, CKE CI 6 24 pf Input Capacitance: CK, CK# CI2 5 pf Input Capacitance: CK, CK#; CK2, CK2# CI3 2 8 pf Table 7: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 3-5, 29, 48, 49; notes appear on pages 2 23; C T A +7 C; VDD = VD = +2.5V ±.2V AC CHARACTERISTICS A/-265 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Access window of s from CK/ AC ns CK# CK high-level width t CH t CK 26 CK low-level width t CL t CK 26 Clock cycle time CL = 2.5 t CK (2.5) ns 4, 46 CL = 2 t CK (2) / 3 7.5/ 3 ns 4, 46 and DM input hold time relative to S t DH ns 23, 27 and DM input setup time relative to S t DS ns 23, 27 and DM input pulse width (for each input) t DIPW... ns 27 Access window of S from CK/ SCK ns CK# S input high pulse width t SH t CK S input low pulse width t SL t CK S- skew, S to last valid, per group, SQ ns 22, 23 per access Write command to first S latching transition t SS t CK S falling edge to CK rising - DSS setup time t CK S falling edge from CK rising - DSH hold time t CK Half clock period t HP t CH, t CL t CH, t CL t CH, t CL ns 3 Data-out high-impedance window from CK/CK# t HZ ns 6, 37 Data-out low-impedance window from CK/CK# t LZ ns 6, 37 Address and control input hold time (fast slew IH..9.9 ns 2 F rate) Address and control input setup time (fast slew IS..9.9 ns 2 F rate) Address and control input hold time (slow slew IH.8 ns 2 S rate) pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 8 24 Micron Technology, Inc.

19 Table 7: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 5, 3-5, 29, 48, 49; notes appear on pages 2 23; C T A +7 C; VDD = VD = +2.5V ±.2V AC CHARACTERISTICS A/-265 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Address and control input setup time (slow slew IS.8 ns 2 S rate) Address and Control input pulse width (for IPW ns each input) LOAD MODE REGISTER command cycle time t MRD ns -S hold, S to first to go non-valid, QH HP - HP - HP - ns 22, 23 per access QHS QHS QHS Data hold skew factor t QHS.55.. ns ACTIVE to PRECHARGE command t RAS 42 7, 4 2, 4 2, ns 3, 49 ACTIVE to READ with Auto precharge command ns RAP ACTIVE to ACTIVE/AUTO REFRESH command RC ns period AUTO REFRESH command period 256MB, ns 44 52MB, GB t RFC 2GB ns ACTIVE to READ or WRITE delay t RCD ns PRECHARGE command period t RP ns S read preamble t RPRE t CK 38 S read postamble t RPST t CK 38 ACTIVE bank a to ACTIVE bank b command t RRD ns S write preamble t WPRE t CK S write preamble setup time t WPRES ns 8, 9 S write postamble t WPST t CK 7 Write recovery time t WR ns Internal WRITE to READ command delay t WTR t CK Data valid output window na t QH - t SQ t QH - t SQ t QH - t SQ ns 22 REFRESH to REFRESH command 256MB µs 2 interval 52MB, GB, t REFC µs 2 2GB Average periodic refresh interval 256MB µs 2 52MB, GB, t REFI µs 2 2GB Terminating voltage delay to VDD t VTD ns Exit SELF REFRESH to non-read command t XSNR ns Exit SELF REFRESH to READ command t XSRD t CK pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 9 24 Micron Technology, Inc.

20 Notes. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: Output (VOUT) VTT 5Ω Reference Point 3pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to.5v in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VD/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VD/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, and -26A, CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters.. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate.. This parameter is sampled. VDD = +2.5V ±.2V, VD = +2.5V ±.2V, VREF = VSS, f = MHz, T A = 25 C, VOUT (DC) = VD/2, VOUT (peak to peak) =.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 2. For slew rates less than V/ns and greater than or equal to.5 V/ns. If slew rate is less than.5 V/ns, timing must be derated: t IS has an additional 5ps per each mv/ns reduction in slew rate from 5mV/ns, while t IH is unaffected. If slew rate exceeds 4.5V/ns, functionality is uncertain. 3. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 4. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE.3 x VD is recognized as LOW. 5. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 6. t HZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 7. The intent of the Don t Care state after completion of the postamble is the S-driven signal should either be high, low, or high-z and that any signal transition within the input switching region must follow valid input requirements. That is, if S transitions high [above VIHDC (MIN)] then it must not transition low (below VIHDC) prior to t SH(MIN). 8. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 9. It is recommended that S be valid (HIGH or LOW) on or before the WRITE command. The case shown (S going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, S could be HIGH during this time, depending on t SS. 2. MIN ( t RC or t RFC) for IDD measurements is the smallest multiple of t CK that meets the minimum absolute value for the respective parameter. t RAS (MAX) for IDD measurements is the largest multiple of t CK that meets the maximum absolute value for t RAS. 2. The refresh period 64ms. This equates to an average refresh rate of 5.625µs (256MB) or 7.825µs (52MB, GB, 2GB). However, an AUTO REFRESH command must be asserted at least once every pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 2 24 Micron Technology, Inc.

21 4.6µs (256MB) or 7.3µs (52MB, GB, 2GB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: t HP ( t CK/2), t SQ, and t QH ( t QH = t HP - t QHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 8, Derating Data Valid Window t HP - t QHS, shows derating curves for duty cycles ranging between 5/5 and 45/ Each byte lane has a corresponding S. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period ( t RFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). 26. JEDEC specifies CK and CK# input slew rate must be V/ns (2V/ns differentially). 27. and DM input slew rates must not deviate from S by more than percent. If the / DM/S slew rate is less than.5v/ns, timing must be derated: 5ps must be added to t DS and t DH for each mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 28. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to ±5ps of jitter. Each timing parameter is allowed to vary by the same amount. 3. t HP min is the lesser of t CL minimum and t CH minimum actually applied to the device CK and CK# inputs, collectively during bank active. Figure 8: Derating Data Valid Window t HP - t QHS NA t CK = ns t CK = 7.5ns t CK = 6ns ns /5 49.5/5.5 49/5 48.5/ / / / / / / /55 Clock Duty Cycle pdf: 95aef8739fa5, source: 95aef87397e5 DD6C32_64_28_256x64AG.fm - Rev. C 9/4 EN 2 24 Micron Technology, Inc.