MC74CGT2 Noninverting Buffer / CMOS ogic evel Shifter with STT Compatible Inputs The MC74CGT2 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC74CGT2 requires the 3 state control input () to be set igh to place the output into the high impedance state. The device input is compatible with TT type input thresholds and the output has a full CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic level translator from 3 CMOS logic to CMOS ogic or from.8 CMOS logic to 3 CMOS ogic while operating at the high voltage power supply. The MC74CGT2 input structure provides protection when voltages up to 7 are applied, regardless of the supply voltage. This allows the MC74CGT2 to be used to interface circuits to 3 circuits. The output structures also provide protection when CC = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. Features igh Speed: t PD = 3. ns (Typ) at CC = ow Power Dissipation: I CC = A (Max) at T A = 2 C TT Compatible Inputs: I = 0.8 ; I = 2 CMOS Compatible Outputs: O > 0.8 CC ; O < 0. CC @oad Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard ogic Families Chip Complexity: FETs = 62; Equivalent Gates = 6 Pb Free Packages are Available SC 88A/SOT 33/SC 70 DF SUFFIX CASE 49A TSOP /SOT 23/SC 9 DT SUFFIX CASE 483 PIN ASSIGNMENT 2 IN A 3 GND 4 OUT Y MARKING DIAGRAMS W M W = Device Code M = Date Code* = Pb Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. M W M CC CC IN A GND 2 3 4 OUT Y A Input FUNCTION TABE Input Y Output Figure. Pinout (Top iew) X Z IN A Figure 2. ogic Symbol OUT Y ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Semiconductor Components Industries, C, 2007 February, 2007 Rev. 2 Publication Order Number: MC74CGT2/D
MC74CGT2 MAXIMUM RATINGS Symbol Characteristics alue Unit CC DC Supply oltage 0. to +7.0 IN DC Input oltage 0. to +7.0 OUT DC Output oltage CC = 0 igh or ow State 0. to 7.0 0. to CC + 0. I IK Input Diode Current 20 ma I OK Output Diode Current OUT < GND; OUT > CC +20 ma I OUT DC Output Current, per Pin +2 ma I CC DC Supply Current, CC and GND +0 ma P D Power Dissipation in Still Air SC 88A, TSOP 200 mw JA Thermal Resistance SC 88A, TSOP 333 C/W T ead Temperature, mm from Case for 0 s 260 C T J Junction Temperature Under Bias +0 C T stg Storage Temperature 6 to +0 C ESD ESD Withstand oltage uman Body Model (Note ) Machine Model (Note 2) Charged Device Model (Note 3) > 2000 > 200 N/A I atchup atchup Performance Above CC and Below GND at 2 C (Note 4) ±00 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Tested to EIA/JESD22 A4 A 2. Tested to EIA/JESD22 A A 3. Tested to JESD22 C0 A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit CC DC Supply oltage. IN DC Input oltage 0.0. OUT DC Output oltage 0.0 CC T A Operating Temperature Range +2 C t r, t f Input Rise and Fall Time CC =.0 ± 0. 0 20 ns/ Device Junction Temperature versus Time to 0.% Bond Failures Junction Temperature C Time, ours Time, Years 80,032,200 7.8 90 49,300 47.9 00 78,700 20.4 0 79,600 9.4 20 37,000 4.2 30 7,800 2.0 NORMAIZED FAIURE RATE FAIURE RATE OF PASTIC = CERAMIC UNTI INTERMETAICS OCCUR TJ = 30 C TJ = 20 C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C 0 00 000 TIME, YEARS 40 8,900.0 Figure 3. Failure Rate vs. Time Junction Temperature 2
MC74CGT2 Î DC EECTRICA CARACTERISTICS CC T A = 2 C Î T A 8 C T A 2 C Symbol Parameter Test Conditions () Min Typ Max Min Max Min Max Î Î Unit I Minimum igh evel.4.4.4 Î Input oltage Î 4. Î 2.0 2.0. Î 2.0 2.0 I Maximum ow evel 0.3 0.3 0.3 Î Input oltage Î 4. 0.8 Î Î 0.8. 0.8 Î Î 0.8 O Î Minimum igh evel Î IN = I or I Output oltage I O Î Î 2.9 Î 2.9 = 0 A 4. 4.4 4. 4.4 4.4 IN = I or I Î IN = I or I Î I O = 4 ma Î Î 2.8 Î Î Î Î 2.48 2.34 I O = 8 ma 4. 3.94 3.80 3.66 O Î Î Maximum ow evel IN = I or I Î Î Output oltage Î I O = 0 A Î 4. Î Î Î 0.0 0.0 Î 0. 0. Î Î Î 0. Î Î 0. 0. IN = I or I Î IN = I or I Î I O = 4 ma I O = 8 ma Î 4. Î Î Î 0.36 0.36 Î Î Î 0.44 Î 0.2 Î 0.2 I IN Î Maximum Input Î IN =. or GND Î 0 to ± 0.0Î ±.0 ± A eakage Current. I CC Î Î Maximum Quiescent IN = CC Î or GND. Supply Current Î Î.0Î Î Î Î 20 Î 40 A I CCT Î Quiescent Supply Î Input: IN = 3.4 Î. Current Other Input: CC or GND Î Î Î.3Î.0.6 Î Î ma I OPD Î Output eakage Î OUT =. Î 0.0 0.Î.0 0 A Current I OZ Maximum 3 State Î eakage Current Î IN = I or I. OUT = CC or GND Î Î ± 0.2 Î Î ± 2. Î ± 2. A I OPD Î Output eakage Î OUT =. Î 0.0 0.Î.0 0 A Current Î AC EECTRICA CARACTERISTICS Input t r = t f = ns T A = 2 C T A 8 C T A 2 C Symbol Parameter Î Test Conditions MinÎ TypÎ Max MinÎ Max Min Î Max Unit t P, Maximum Propagation Î CC = 3.3 ± 0.3 C = pf t P Delay, A to Y.6 Î 8.0.0 Î 9. 2.0 ns C = 0pF 8...0 6.0 (Figures 3 and.) Î CC =.0 ± 0. C = pf Î C = 0pF Î Î Î 3.8..3Î 7..0.0 Î 6. 8. Î 8. Î 0. t PZ, Maximum Output Î CC = 3.3 ± 0.3 C = pf t PZ Enable TIme, to Y.4 Î 8.0.0 Î 9.. ns R = R I = 00 C = 0pF 7.9..0.0 (Figures 4 and ) Î CC =.0 ± 0. C = pf Î Î Î R = R I = 00 C = 0pF 3.6..Î 7..0.0 Î 6.0 8.0 Î 7. Î 9. t PZ, Maximum Output Î CC = 3.3 ± 0.3 C = pf t PZ Disable Time, to Y 6. Î 9.7 R = R I = 00 C = 0pF 8.0 (Figures 4 and ).0 3.2 Î..0 Î 4..0 ns 8.0 Î CC =.0 ± 0. C = pf 4.8 6.8.0 8.0 0.0 Î R = R I = 00 C = 0pF 7.0Î 8.8.0 Î 0.0 2.0 C in Maximum Input Capacitance Î 4 Î 0 0 pf C out Maximum Three State 6 Î pf Output Capacitance Î (Output in igh Impedance Î State) Î Typical @ 2 C, CC =.0 C PD Power Dissipation Capacitance (Note ) 4 pf. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC / 4 (per buffer). C PD is used to determine the no load dynamic power consumption; P D = C PD 2 CC f in + I CC CC. 3
MC74CGT2 SWITCING WAEFORMS A Y 0% CC 0% GND t PZ t PZ t P t P Y 0% CC 0% CC t PZ t PZ Y 0% CC Figure 4. Switching Waveforms Figure. CC GND IG IMPEDANCE O + 0.3 O 0.3 IG IMPEDANCE DEICE UNDER TEST OUTPUT TEST POINT C * DEICE UNDER TEST TEST POINT k OUTPUT C * CONNECT TO CC WEN TESTING t PZ AND t PZ. CONNECT TO GND WEN TESTING t PZ AND t PZ. *Includes all probe and jig capacitance Figure 6. Test Circuit *Includes all probe and jig capacitance Figure 7. Test Circuit INPUT Figure 8. Input Equivalent Circuit ORDERING INFORMATION Device Package Shipping MC74CGT2DF M74CGT2DFG MC74CGT2DF2 M74CGT2DF2G SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC 70 (Pb Free) SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC 70 (Pb Free) 3000/Tape & Reel MC74CGT2DT M74CGT2DTG TSOP / SOT 23 / SC 9 TSOP / SOT 23 / SC 9 (Pb Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 4
MC74CGT2 PACKAGE DIMENSIONS SC 88A, SOT 33, SC 70 CASE 49A 02 ISSUE J S A G 4 B 2 3 D P 0.2 (0.008) M B M N NOTES:. DIMENSIONING AND TRANCING PER ANSI Y4.M, 982. 2. CONTROING DIMENSION: INC. 3. 49A 0 OBSTE. NEW STANDARD 49A 02. 4. DIMENSIONS A AND B DO NOT INCUDE MOD FAS, PROTRUSIONS, OR GATE BURRS. INCES MIIMETERS DIM MIN MAX MIN MAX A 0.07 0.087.80 2.20 B 0.04 0.03..3 C 0.03 0.043 0.80.0 D 0.004 0.02 0.0 0.30 G 0.026 BSC 0.6 BSC 0.004 0.0 J 0.004 0.00 0.0 0.2 K 0.004 0.02 0.0 0.30 N 0.008 REF 0.20 REF S 0.079 0.087 2.00 2.20 C J K SODERING FOOTPRINT* 0.0 0.097 0.6 0.02 0.40 0.07 0.6 0.02.9 0.0748 SCAE 20: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D.
MC74CGT2 PACKAGE DIMENSIONS TSOP CASE 483 02 ISSUE F 2X 2X NOTE 0.0 T 0.20 T 0.0 4 2 3 G A B C D X 0.20 C A B T S SEATING PANE J K DETAI Z M DETAI Z NOTES:. DIMENSIONING AND TRANCING PER ASME Y4.M, 994. 2. CONTROING DIMENSION: MIIMETERS. 3. MAXIMUM EAD TICKNESS INCUDES EAD FINIS TICKNESS. MINIMUM EAD TICKNESS IS TE MINIMUM TICKNESS OF BASE MATERIA. 4. DIMENSIONS A AND B DO NOT INCUDE MOD FAS, PROTRUSIONS, OR GATE BURRS.. OPTIONA CONSTRUCTION: AN ADDITIONA TRIMMED EAD IS AOWED IN TIS OCATION. TRIMMED EAD NOT TO EXTEND MORE TAN 0.2 FROM BODY. MIIMETERS DIM MIN MAX A 0 BSC B.0 BSC C 0.90.0 D 0.2 0.0 G 0.9 BSC 0.0 0.0 J 0.0 0.26 K 0.20 0.60.2. M 0 0 S 2.0 0 SODERING FOOTPRINT* 0.9 0.037.9 0.074 2.4 0.094.0 0.039 0.7 0.028 SCAE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 8027 USA Phone: 303 67 27 or 800 344 3860 Toll Free USA/Canada Fax: 303 67 276 or 800 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800 282 98 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 790 290 Japan Customer Focus Center Phone: 8 3 773 380 6 ON Semiconductor Website: www.onsemi.com Order iterature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74CGT2/D