INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS ogic Package Outlines File under Integrated Circuits, IC06 December 1990

2 FEATURES Non-inverting outputs Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The are octal non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE 1 and OE 2. A HIGH on OE n causes the outputs to assume a high impedance OFF-state. The 541 is identical to the 540 but has non-inverting outputs. QUICK REFERENCE DATA GND = 0 V; T amb = 25 C; t r = t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS HC HCT UNIT t PH / t PH propagation delay A n to Y n C = 15 pf; V CC = 5 V ns C I input capacitance pf C PD power dissipation capacitance per buffer notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS ogic Package Information. December

3 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1, 19 OE 1, OE 2 output enable input (active OW) 2, 3, 4, 5, 6, 7, 8, 9 A 0 to A 7 data inputs 10 GND ground (0 V) 18, 17, 16, 15, 14, 13, 12, 11 Y 0 to Y 7 bus outputs 20 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December

4 FUNCTION TABE INPUTS OUTPUT OE 1 OE 2 A n Y n X H H X H X X Notes 1. H = HIGH voltage level = OW voltage level X = don t care Z = high impedance OFF-state H Z Z Fig.4 Functional diagram. Fig.5 ogic diagram. December

5 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; t r = t f = 6 ns; C = 50 pf T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74HC to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t PH / t PH propagation delay 33 A n to Y n ns Fig.6 t PZH / t PZ 3-state output enable time OE to Y n ns Fig.7 t PHZ / t PZ 3-state output disable time OE to Y n ns Fig.7 t TH / t TH output transition time ns Fig.6 December

6 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to HCT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE 1 OE 2 A n UNIT OAD COEFFICIENT AC CHARACTERISTICS FOR 74HCT GND = 0 V; t r = t f = 6 ns; C = 50 pf SYMBO t PH / t PH t PZH / t PZ t PHZ / t PZ t TH / t TH T amb ( C) TEST CONDITIONS 74HCT PARAMETER UNIT V to to +125 CC (V) WAVEFORMS min. typ. max. min. max. min. max. propagation delay A n to Y n ns 4.5 Fig.6 3-state output enable time OE to Y n ns 4.5 Fig.7 3-state output disable time OE to Y n ns 4.5 Fig.7 output transition time ns 4.5 Fig.6 December

7 AC WAVEFORMS (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the input (A n ) to output (Y n ) propagation delays and the output transition times. (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTINES See 74HC/HCT/HCU/HCMOS ogic Package Outlines. December

8 This datasheet has been download from: Datasheets for electronics components.