74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs

Transcription

1 74HC574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Ordering Code: March 1993 Revised May 2005 The HC574 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit eures that 0 to 7 can be applied to the input pi without regard to the supply voltage. This device can be used to interface 5 to 3 systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features High Speed: t PD 5.6 (typ) at CC 5 High Noise Immunity: NIH NIL 28% CC (Min) Power Down Protection is provided on all inputs Low Noise: OLP 0.6 (typ) Low Power Dissipation: I CC 4 PA T A 25qC Pin and Function Compatible with 74HC574 Order Number Package Number Package Description 74HC574M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74HC574SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74HC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74HC574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering code. Pb-Free package per JEDEC J-STD-020B. 74HC574 Octal D-Type Flip-Flop with 3-STATE Outputs Logic Symbol Connection Diagram IEEE/IEC Pin Descriptio Pin Names D 0 D 7 CP OE O 0 O 7 Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs 2005 Fairchild Semiconductor Corporation DS

2 74HC574 Functional Description The HC574 coists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) traition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Logic Diagram Truth Table H HIGH oltage Level L LOW oltage Level X Immaterial Z High Impedance LOW-to-HIGH Traition Inputs Outputs D n CP OE O n H L H L L L X X H Z Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays. 2

3 Absolute Maximum Ratings(Note 1) Supply oltage ( CC ) 0.5 to 7.0 DC Input oltage ( IN ) 0.5 to 7.0 DC Output oltage ( OUT ) 0.5 to CC 0.5 Input Diode Current (I IK ) 20 ma Output Diode Current r20 ma DC Output Current (I OUT ) r25 ma DC CC /GND Current (I CC ) r75 ma Storage Temperature (T STG ) 65qC to 150qC Lead Temperature (T L ) (Soldering, 10 seconds) 260qC DC Electrical Characteristics Recommended Operating Conditio (Note 2) Supply oltage ( CC ) 2.0 to 5.5 Input oltage ( IN ) 0 to 5.5 Output oltage ( OUT ) 0 to CC Operating Temperature (T OPR ) 40qC to 85qC Input Rise and Fall Time (t r, t f ) CC 3.3 r a 100 / CC 5.0 r a 20 / Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specificatio should be met, without exception, to eure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specificatio. Note 2: Unused inputs must be held HIGH or LOW. They may not float. 74HC574 T Symbol Parameter CC A 25qC T A 40qC to 85qC () Min Typ Max Min Max IH HIGH Level Noise Characteristics Note 3: Parameter guaranteed by design. Units Conditio Input oltage CC 0.7 CC IL LOW Level Input oltage CC 0.3 CC OH HIGH Level IN IH I OH 50 PA Output oltage or IL I OH 4 ma I OH 8 ma OL LOW Level IN IH I OL 50 PA Output oltage or IL I OL 4 ma I OL 8 ma I OZ 3-STATE 5.5 r0.25 r2.5 PA IN IH or IL Output Off-State Current OUT CC or GND I IN Input Leakage r0.1 r1.0 PA IN 5.5 or GND Current I CC Quiescent Supply PA IN CC or GND Current Symbol OLP (Note 3) OL (Note 3) IHD (Note 3) ILD (Note 3) Parameter CC () Typ T A 25qC Limits Quiet Output Maximum Dynamic OL C L 50 pf Quiet Output Minimum Dynamic OL C L 50 pf Minimum HIGH Level Dynamic Input oltage C L 50 pf Maximum LOW Level Dynamic Input oltage C L 50 pf Units Conditio 3

4 74HC574 AC Electrical Characteristics Symbol Parameter CC T A 25qC T A 40qC to 85qC () Min Typ Max Min Max Units Conditio t PLH Propagation Delay 3.3 r C L 15 pf t PHL Time (CP to O n ) C L 50 pf 5.0 r C L 15 pf C L 50 pf t PZL 3-STATE Output 3.3 r R L 1 k: C L 15 pf t PZH Enable Time C L 50 pf 5.0 r C L 15 pf C L 50 pf t PLZ 3-STATE Output 3.3 r R L 1 k: C L 50 pf t PHZ Disable Time 5.0 r C L 50 pf t OSLH Output to 3.3 r (Note 4) C L 50 pf t OSHL Output Skew 5.0 r C L 50 pf f MAX Maximum Clock 3.3 r C L 15 pf Frequency C L 50 pf MHz 5.0 r C L 15 pf C L 50 pf C IN Input pf CC Open Capacitance C OUT Output 6 pf CC 5.0 Capacitance C PD Power Dissipation 28 pf (Note 5) Capacitance Note 4: Parameter guaranteed by design. t OSLH t PLH max t PLH min ; t OSHL t PHL max t PHL min Note 5: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: I CC (opr.) C PD * CC * f IN I CC /8 (per F/F). The total C PD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: C PD (total) 20 8n. AC Operating Requirements Symbol Parameter CC T A 25qC T A 40qC to 85qC () Min Typ Max Min Max t W (H) Minimum Pulse Width (CP) 3.3 r t W (L) 5.0 r t S Minimum Set-Up Time 3.3 r r t H Minimum Hold Time 3.3 r r Units 4

5 Physical Dimeio inches (millimeters) unless otherwise noted 74HC Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5

6 74HC574 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 6

7 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 74HC Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7

8 74HC574 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.