MC74HC132A. Quad 2-Input NAND Gate with Schmitt-Trigger Inputs. High Performance Silicon Gate CMOS

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1 MC74HC32A Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High Performance Silicon Gate CMOS The MC74HC32A is identical in pinout to the LS32. The device inputs are compatible with standard CMOS outputs; with pull up resistors, they are compatible with LSTTL outputs. The HC32A can be used to enhance noise immunity or to square up slowly changing waveforms. Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: 2.0 to 6.0 Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements as Defined by JEDEC Standard No. 7A Chip Complexity: 72 FETs or 8 Equivalent Gates NL Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant PDIP 4 N SUFFIX CASE SOIC 4 D SUFFIX CASE 75A TSSOP 4 DT SUFFIX CASE 948G MARKING DIAGRAMS MC74HC32AN AWLYYWWG 4 HC32AG AWLYWW HC 32A ALYW A B B4 Y 3 2 A4 A2 4 Y4 B2 5 0 B3 Y2 6 9 A3 GND 7 8 Y3 Figure. Pin Assignment A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs Output A B Y L L H L H H H L H H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 203 May, 203 Rev. 5 Publication Order Number: MC74HC32A/D

2 MC74HC32A A B A Y B2 A3 B3 A Y2 Y = AB 8 Y3 B4 3 Y4 PIN 4 = PIN 7 = GND Figure 2. Logic Diagram ORDERING INFORMATION MC74HC32ANG Device Package Shipping PDIP 4 25 / Tape & Ammo Box MC74HC32ADG MC74HC32ADR2G MC74HC32ADTG MC74HC32ADTR2G NL74HC32ADG* NL74HC32ADR2G* NL74HC32ADTG* SOIC 4 SOIC 4 TSSOP 4 TSSOP 4 SOIC 4 SOIC 4 TSSOP 4 55 Units / Rail 2500 / Tape & Reel 96 Units / Rail 2500 / Tape & Reel 55 Units / Rail 2500 / Tape & Reel 96 Units / Rail NL74HC32ADTR2G* TSSOP / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *NL Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable 2

3 MC74HC32A MAXIMUM RATINGS Symbol Parameter alue Unit Positive DC Supply oltage 0.5 to 7.0 IN Digital Input oltage 0.5 to 7.0 OUT DC Output oltage Output in 3 State High or Low State 0.5 to to 0.5 I IK Input Diode Current 20 ma I OK Output Diode Current 20 ma I OUT DC Output Current, per Pin 25 ma I CC DC Supply Current, and GND Pins 75 ma I GND DC Ground Current per Ground Pin 75 ma T STG Storage Temperature Range 65 to 50 C T L Lead Temperature, mm from Case for 0 Seconds 260 C T J Junction Temperature Under Bias 50 C JA Thermal Resistance 4 PDIP 4 SOIC 4 TSSOP P D Power Dissipation in Still Air at 85 C PDIP SOIC TSSOP MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 30% 35% UL in ESD ESD Withstand oltage Human Body Model (Note ) Machine Model (Note 2) Charged Device Model (Note 3) I Latch Up Latch Up Performance Above and Below GND at 85 C (Note 4) 300 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Tested to EIA/JESD22 A4 A. 2. Tested to EIA/JESD22 A5 A. 3. Tested to JESD22 C0 A. 4. Tested to EIA/JESD78. C/W mw RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit Î DC Supply oltage (Referenced to GND) Î Î IN, OUT Î DC Input oltage, Output oltage (Referenced to GND) 0 Î Î T A Operating Temperature, All Package Types Î C t r, t f Î Input Rise and Fall Time (Figure 3) No Limit ns Î (Note 5) Î Î 5. When IN Î 0.5, I CC >> quiescent current. 6. Unused inputs may not be left open. All inputs must be tied to a high logic voltage level or a low logic input voltage level. 3

4 MC74HC32A DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions 55 C to 25 C 85 C 25 C Unit T+ max Maximum Positive Going OUT = 0. Î 2.0 Î Input Threshold oltage I OUT 20 A (Figure 5) T+ min Minimum Positive Going OUT = Input Threshold oltage I OUT 20 A Î 4.5 Î (Figure 5) Î Î T max Maximum Negative Going Input Threshold oltage OUT = I OUT 20 A Î 4.5 Î (Figure 5) Î T min Minimum Negative Going OUT = Input Threshold oltage I OUT 20 A Î (Figure 5) 6.0 Î H max Maximum Hysteresis OUT = 0. or 0. Î 2.0 Î (Note 7) oltage I Î (Figure 5) OUT 20 A Î 6.0 Î H min Minimum Hysteresis OUT = 0. or 0. Î 2.0 Î (Note 7) oltage I (Figure 5) OUT 20 A Î 6.0 Î OH Minimum High Level IN T min or T+ max Î 2.0 Î Î Output oltage I OUT 20 A Î 4.5 Î Î Î IN T min or T+ max I OUT 4.0 maî I OUT 5.2 ma 4.5 Î Î OL Maximum Low Level Output oltage IN T+ max I OUT 20 A Î 4.5 Î Î IN T+ max I OUT 4.0 ma Î 4.5 Î I OUT 5.2 ma Î Î I IN Maximum Input Leakage Current IN = or GND A I CC Maximum Quiescent IN = or GND Î 6.0 Î A Supply Current I Î (per Package) OUT = 0 A Î 7. H min ( T+ min) ( T max); H max = ( T+ max) ( T min). 4

5 MC74HC32A AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6.0 ns) Guaranteed Limit Symbol Parameter 55 C to 25 C 85 C 25 C Unit t PLH, Î Maximum Propagation Delay, Input A or B to Output Y Î 2.0 Î ns t (Figures 3 and 4) PHL t TLH, Maximum Output Transition Time, Any Output ns t THL Î (Figures 3 and 4) Î 4.5 Î Î Î Î C in Maximum Input Capacitance Î pf 25 C, = 5.0 C PD Power Dissipation Capacitance (per Gate) (Note 8) 24 pf 8. Used to determine the no load dynamic power consumption: P D = C PD 2 CC f + I CC. TEST POINT t r t f INPUT A OR B Y 90% 50% 0% t PHL 90% 50% 0% t PLH GND DEICE UNDER TEST OUTPUT C L * t THL t TLH *Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit 5

6 MC74HC32A T, TYPICAL INPUT THRESHOLD OLTAGE (OLTS) , POWER SUPPLY OLTAGE (OLTS) H typ = ( T + typ) - ( T - typ) H typ Figure 5. Typical Input Threshold, T+, T ersus Power Supply oltage H H IN T + T - IN T + T - GND GND OH OH OUT OUT OL OL (a) A SCHMITT TRIGGER SQUARES UP INPUTS (a) WITH SLOW RISE AND FALL TIMES IN OUT (b) A SCHMITT TRIGGER OFFERS MAXIMUM NOISE IMMUNITY Figure 6. Typical Schmitt Trigger Applications 6

7 MC74HC32A PACKAGE DIMENSIONS SOIC 4 NB CASE 75A 03 ISSUE K H M B M e D 7 3X b A B E 0.25 M C A S B S A A C SEATING PLANE L DETAIL A h X 45 M A3 DETAIL A NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. MILLIMETERS INCHES DIM MIN MAX MIN MAX A A A b D E e.27 BSC BSC H h L M SOLDERING FOOTPRINT* X.8.27 PITCH 4X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 MC74HC32A PACKAGE DIMENSIONS TSSOP 4 DT SUFFIX CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 G 4X K REF A 0.0 (0.004) M T U S S 8 7 B U H N N J J F DETAIL E DETAIL E 0.25 (0.00) K K M ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ SECTION N N W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 4X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8

9 MC74HC32A PACKAGE DIMENSIONS PDIP 4 N SUFFIX CASE ISSUE P B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G 0.00 BSC 2.54 BSC H J K K J L M 0 0 H G D 4 PL M N (0.005) M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74HC32A/D