SN74LS74AMEL. Dual D Type Positive Edge Triggered Flip Flop LOW POWER SCHOTTKY

Transcription

1 SN74S74A ual Type Positive Edge Triggered Flip Flop The SN74S74A dual edge-triggered flip-flop utilizes Schottky TT circuitry to produce high speed -type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary and outputs. Information at input is transferred to the output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the IG or the OW level, the input signal has no effect. OW POWER SCOTTKY MOE SEECT TRUT TABE OPERATING MOE Set Reset (Clear) *Undetermined oad (Set) oad 0 (Reset) INPUTS OUTPUTS S C * Both outputs will be IG while both S and C are OW, but the output states are unpredictable if S and C go IG simultaneously. If the levels at the set and clear are near V I maximum then we cannot guarantee to meet the minimum level for V O., h = IG Voltage evel, I = OW Voltage evel X = on t Care l, h (q) = ower case letters indicate the state of the referenced input i, h (q) = (or output) one set-up time prior to the IG to OW clock transition. X X X h l 4 4 SOIC SUFFIX CASE 75A 4 PASTIC N SUFFIX CASE 646 SOEIAJ M SUFFIX CASE 965 GUARANTEE OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I O Output Current igh 0.4 ma I O Output Current ow 8.0 ma ORERING INFORMATION evice Package Shipping SN74S74AN 4 Pin IP 2000 Units/Box SN74S74A SOIC 4 55 Units/Rail SN74S74AR2 SOIC /Tape & Reel SN74S74AM SOEIAJ 4 See Note SN74S74AME SOEIAJ 4 See Note. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, C, 2006 July, 2006 Rev. 8 Publication Order Number: SN74S74A/

2 SN74S74A OGIC IAGRAM (Each Flip-Flop) SET (S ) 4 (0) CEAR (C) (3) 5 (9) COCK 3 () 2 (2) 6 (8) OGIC SYMBO S 5 2 S 9 3 CP CP C 6 C 8 3 V CC = PIN 4 GN = PIN 7 2

3 SN74S74A C CARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter imits Min Typ Max V I Input IG Voltage 2.0 V V I Input OW Voltage 0.8 Unit V Test Conditions Guaranteed Input IG Voltage for All Inputs Guaranteed Input OW Voltage for All Inputs V IK Input Clamp iode Voltage V V CC = MIN, I IN = 8 ma V O Output IG Voltage V V CC = MIN, I O = MAX, V IN = V I or V I per Truth Table V O I I I I Output OW Voltage Input igh Current ata, Clock Set, Clear ata, Clock Set, Clear Input OW Current ata, Clock Set, Clear V I O = 4.0 ma V CC = V CC MIN, V IN = V I or V I V I O = 8.0 ma per Truth Table I OS Output Short Circuit Current (Note 2) ma V CC = MAX I CC Power Supply Current 8.0 ma V CC = MAX 2. Not more than one output should be shorted at a time, nor for more than second. μa ma ma V CC = MAX, V IN = 2.7 V V CC = MAX, V IN = 7.0 V V CC = MAX, V IN = 0.4 V AC CARACTERISTICS (T A = 25 C, V CC = 5.0 V) Symbol Parameter imits Min Typ Max f MAX Maximum Clock Frequency Mz Figure t P t P Clock, Clear, Set to Output AC SETUP REUIREMENTS (T A = 25 C) Symbol Parameter Unit 3 25 ns ns imits Min Typ Max Figure t W() Clock 25 ns Figure t W() Clear, Set 25 ns Figure 2 t s ata Setup Time IG ata Setup Time OW Unit 20 ns 20 ns Figure t h old Time 5.0 ns Figure Test Conditions Test Conditions V CC = 5.0 V C = 5 pf V CC = 5.0 V 3

4 SN74S74A AC WAVEFORMS * t h() t s() tw() t W() t s() t h() CP t P f MAX t P t P t P *The shaded areas indicate when the input is permitted to change for predictable output performance. Figure. Clock to Output elays, ata Set-Up and old Times, Clock Pulse Width t W SET t W CEAR t P t P t P t P Figure 2. Set and Clear to Output elays, Set and Clear Pulse Widths 4

5 SN74S74A PACKAGE IMENSIONS B N SUFFIX PASTIC PACKAGE CASE ISSUE M NOTES:. IMENSIONING AN TOERANCING PER ANSI Y4.5M, CONTROING IMENSION: INC. 3. IMENSION TO CENTER OF EAS WEN FORME PARAE. 4. IMENSION B OES NOT INCUE MO FAS. 5. ROUNE CORNERS OPTIONA. T SEATING PANE N A INCES MIIMETERS IM MIN MAX MIN MAX A F B C C F G 0.00 BSC 2.54 BSC J K K J M 0 0 G 4 P M N (0.005) M 5

6 SN74S74A PACKAGE IMENSIONS T SEATING PANE G A P 7 B K P 7 P C 0.25 (0.00) M T B S A S SUFFIX PASTIC SOIC PACKAGE CASE 75A 03 ISSUE F 0.25 (0.00) M B M NOTES:. IMENSIONING AN TOERANCING PER ANSI Y4.5M, CONTROING IMENSION: MIIMETER. 3. IMENSIONS A AN B O NOT INCUE MO PROTRUSION. 4. MAXIMUM MO PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCUE AMBAR PROTRUSION. AOWABE AMBAR PROTRUSION SA BE 0.27 (0.005) TOTA IN EXCESS OF TE IMENSION AT MAXIMUM MATERIA CONITION. MIIMETERS INCES R X 45 F IM MIN MAX MIN MAX A B C M J F G.27 BSC BSC J K M P R

7 SN74S74A PACKAGE IMENSIONS e 4 8 Z E b A 0.3 (0.005) M 0.0 (0.004) 7 E A VIEW P M M SUFFIX SOEIAJ PACKAGE CASE ISSUE O E ETAI P c NOTES:. IMENSIONING AN TOERANCING PER ANSI Y4.5M, CONTROING IMENSION: MIIMETER. 3. IMENSIONS AN E O NOT INCUE MO FAS OR PROTRUSIONS AN ARE MEASURE AT TE PARTING INE. MO FAS OR PROTRUSIONS SA NOT EXCEE 0.5 (0.006) PER SIE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EA WIT IMENSION (b) OES NOT INCUE AMBAR PROTRUSION. AOWABE AMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE EA WIT IMENSION AT MAXIMUM MATERIA CONITION. AMBAR CANNOT BE OCATE ON TE OWER RAIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AN AJACENT EA TO BE 0.46 ( 0.08). MIIMETERS INCES IM MIN MAX MIN MAX A A b c E e.27 BSC BSC E E M Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORERING INFORMATION ITERATURE FUFIMENT: iterature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative SN74S74A/